712 lines
21 KiB
C
712 lines
21 KiB
C
/* Opcode table for the TXVU
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Copyright 1998 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "ansidecl.h"
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#include "dis-asm.h"
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#include "opcode/txvu.h"
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#ifndef NULL
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#define NULL 0
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#endif
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#if defined (__STDC__) || defined (ALMOST_STDC)
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#define XCONCAT2(a,b) a##b
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#else
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#define XCONCAT2(a,b) a/**/b
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#endif
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#define CONCAT2(a,b) XCONCAT2(a,b)
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/* ??? One can argue it's preferable to have the PARSE_FN support in tc-vxvu.c
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and the PRINT_FN support in txvu-dis.c. For this project I like having
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them all in one place. */
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#define PARSE_FN(fn) \
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static long CONCAT2 (parse_,fn) \
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PARAMS ((char **, const char **));
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#define INSERT_FN(fn) \
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static TXVU_INSN CONCAT2 (insert_,fn) \
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PARAMS ((TXVU_INSN, const struct txvu_operand *, \
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int, long, const char **))
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#define EXTRACT_FN(fn) \
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static long CONCAT2 (extract_,fn) \
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PARAMS ((TXVU_INSN, const struct txvu_operand *, \
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int, int *))
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#define PRINT_FN(fn) \
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static void CONCAT2 (print_,fn) \
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PARAMS ((disassemble_info *, TXVU_INSN, long));
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PARSE_FN (dotdest);
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INSERT_FN (dotdest);
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EXTRACT_FN (dotdest);
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PRINT_FN (dotdest);
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PARSE_FN (vfreg);
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PRINT_FN (vfreg);
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PARSE_FN (bc);
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PRINT_FN (bc);
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PARSE_FN (ftregbc);
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PRINT_FN (ftregbc);
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PARSE_FN (accdest);
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PRINT_FN (accdest);
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PARSE_FN (xyz);
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/* Various types of TXVU operands, including insn suffixes.
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Fields are:
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BITS SHIFT FLAGS PARSE_FN INSERT_FN EXTRACT_FN PRINT_FN
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Operand values are 128 + table index. This allows ASCII chars to be
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included in the syntax spec. */
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const struct txvu_operand txvu_operands[] =
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{
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/* place holder (??? not sure if needed) */
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#define UNUSED 128
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{ 0 },
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/* Destination indicator, with leading '.'. */
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#define DOTDEST (UNUSED + 1)
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{ 4, TXVU_SHIFT_DEST, TXVU_OPERAND_SUFFIX,
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parse_dotdest, insert_dotdest, extract_dotdest, print_dotdest },
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/* ft reg */
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#define FTREG (DOTDEST + 1)
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{ 5, TXVU_SHIFT_FTREG, 0, parse_vfreg, 0, 0, print_vfreg },
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/* fs reg */
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#define FSREG (FTREG + 1)
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{ 5, TXVU_SHIFT_FSREG, 0, parse_vfreg, 0, 0, print_vfreg },
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/* fd reg */
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#define FDREG (FSREG + 1)
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{ 5, TXVU_SHIFT_FDREG, 0, parse_vfreg, 0, 0, print_vfreg },
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/* broadcast */
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#define BC (FDREG + 1)
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{ 2, 0, 0, parse_bc, 0, 0, print_bc },
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/* ftreg in broadcast case */
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#define FTREGBC (BC + 1)
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{ 5, TXVU_SHIFT_FTREG, 0, parse_ftregbc, 0, 0, print_ftregbc },
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/* accumulator dest */
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#define ACCDEST (FTREGBC + 1)
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{ 0, 0, TXVU_OPERAND_FAKE, parse_accdest, 0, 0, print_accdest },
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/* The XYZ operand is a fake one that is used to ensure only "xyz" is
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specified. It simplifies the opmula and opmsub entries. */
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#define XYZ (FDREG + 1)
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{ 0, 0, TXVU_OPERAND_FAKE, parse_xyz, 0, 0, 0 },
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/* end of list place holder */
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{ 0 }
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};
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/* Macros to put a field's value into the right place. */
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/* FIXME: If assembler needs these, move to opcode/txvu.h. */
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#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
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/* Upper Flag bits. */
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#define UF(x) R ((x), 27, 31)
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/* Upper REServed two bits next to flag bits. */
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#define URES(x) R ((x), 25, 3)
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/* The DEST field. */
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#define UDEST(x) R ((x), 21, 15)
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/* The FT reg field. */
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#define UFT(x) R ((x), TXVU_SHIFT_FTREG, TXVU_MASK_VFREG)
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/* The FS reg field. */
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#define UFS(x) R ((x), TXVU_SHIFT_FSREG, TXVU_MASK_VFREG)
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/* The FD reg field. */
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#define UFD(x) R ((x), TXVU_SHIFT_FDREG, TXVU_MASK_VFREG)
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/* The 4 bit opcode field. */
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#define UOP4(x) R ((x), 2, 15)
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/* The 6 bit opcode field. */
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#define UOP6(x) R ((x), 0, 63)
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/* The 9 bit opcode field. */
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#define UOP9(x) R ((x), 2, 0x1ff)
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/* The 11 bit opcode field. */
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#define UOP11(x) R ((x), 0, 0x7ff)
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/* The BroadCast field. */
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#define UBC(x) R ((x), 0, 3)
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/* Macros for special field values. */
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/* The upper 7 bits of the upper word. */
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#define UUBITS (UF (0) + URES (0))
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/* Mask for UBITS. */
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#define MUUBITS (UF (~0) + URES (~0))
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/* Mask for URES. */
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#define MURES URES (~0)
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/* Mask for OP4. */
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#define MUOP4 UOP4 (~0)
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/* Mask for OP6. */
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#define MUOP6 UOP6 (~0)
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/* Mask for OP9. */
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#define MUOP9 UOP9 (~0)
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/* Mask for OP11. */
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#define MUOP11 UOP11 (~0)
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/* A space, separates instruction name (mnemonic + mnemonic operands) from operands. */
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#define SP ' '
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/* TXVU instructions.
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[??? some of these comments are left over from the ARC port from which
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this code is borrowed, delete in time]
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Longer versions of insns must appear before shorter ones (if gas sees
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"lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is
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junk). This isn't necessary for `ld' because of the trailing ']'.
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Instructions that are really macros based on other insns must appear
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before the real insn so they're chosen when disassembling. Eg: The `mov'
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insn is really the `and' insn.
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This table is best viewed on a wide screen (161 columns). I'd prefer to
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keep it this way. The rest of the file, however, should be viewable on an
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80 column terminal. */
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/* ??? This table also includes macros: asl, lsl, and mov. The ppc port has
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a more general facility for dealing with macros which could be used if
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we need to. */
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/* These tables can't be `const' because members `next_asm' and `next_dis' are
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computed at run-time. We could split this into two, as that would put the
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constant stuff into a readonly section. */
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struct txvu_opcode txvu_upper_opcodes[] = {
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/* Macros appear first. */
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/* ??? Any aliases? */
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/* The rest of these needn't be sorted, but it helps to find them if they are. */
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{ "abs", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x1fd) },
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{ "add", { DOTDEST, SP, FDREG, FSREG, FTREG }, MURES + MUOP6, UOP6 (0x28) },
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{ "addi", { DOTDEST, SP, FDREG, FSREG, 'i' }, MURES + UFT (~0) + MUOP6, UOP6 (0x22) },
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{ "addq", { DOTDEST, SP, FDREG, FSREG, 'q' }, MURES + UFT (~0) + MUOP6, UOP6 (0x20) },
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{ "add", { BC, DOTDEST, SP, FDREG, FSREG, FTREGBC }, MURES + UOP4 (~0), UOP4 (0) },
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{ "adda", { DOTDEST, SP, ACCDEST, FSREG, FTREG }, MURES + MUOP11, UOP11 (0x2bc) },
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{ "addai", { DOTDEST, SP, ACCDEST, FSREG, 'i' }, MURES + UFT (~0) + MUOP11, UOP11 (0x23e) },
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{ "addaq", { DOTDEST, SP, ACCDEST, FSREG, 'q' }, MURES + UFT (~0) + MUOP11, UOP11 (0x23c) },
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{ "adda", { BC, DOTDEST, SP, ACCDEST, FSREG, FTREGBC }, MURES + MUOP9, UOP9 (0xf) },
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{ "clip", { DOTDEST, SP, FSREG }, MURES + UDEST (~0) + UFT (~0) + MUOP11, UDEST (0xf) + UOP11 (0x1ff) },
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{ "ftoi0", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x17c) },
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{ "ftoi4", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x17d) },
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{ "ftoi12", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x17e) },
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{ "ftoi15", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x17f) },
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{ "itof0", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x13c) },
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{ "itof4", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x13d) },
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{ "itof12", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x13e) },
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{ "itof15", { DOTDEST, SP, FTREG, FSREG }, MURES + MUOP11, UOP11 (0x13f) },
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{ "madd", { DOTDEST, SP, FDREG, FSREG, FTREG }, MURES + MUOP6, UOP6 (0x29) },
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{ "maddi", { DOTDEST, SP, FDREG, FSREG, 'i' }, MURES + UFT (~0) + MUOP6, UOP6 (0x23) },
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{ "maddq", { DOTDEST, SP, FDREG, FSREG, 'q' }, MURES + UFT (~0) + MUOP6, UOP6 (0x21) },
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{ "madd", { BC, DOTDEST, SP, FDREG, FSREG, FTREGBC }, MURES + MUOP4, UOP4 (0x2) },
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{ "madda", { DOTDEST, SP, ACCDEST, FSREG, FTREG }, MURES + MUOP11, UOP11 (0x2bd) },
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{ "maddai", { DOTDEST, SP, ACCDEST, FSREG, 'i' }, MURES + UFT (~0) + MUOP11, UOP11 (0x23f) },
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{ "maddaq", { DOTDEST, SP, ACCDEST, FSREG, 'q' }, MURES + UFT (~0) + MUOP11, UOP11 (0x23d) },
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{ "madda", { BC, DOTDEST, SP, ACCDEST, FSREG, FTREGBC }, MURES + MUOP9, UOP9 (0x2f) },
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{ "max", { DOTDEST, SP, FDREG, FSREG, FTREG }, MURES + MUOP6, UOP6 (0x2b) },
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{ "maxi", { DOTDEST, SP, FDREG, FSREG, 'i' }, MURES + UFT (~0) + MUOP6, UOP6 (0x2d) },
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{ "max", { BC, DOTDEST, SP, FDREG, FSREG, FTREGBC }, MURES + MUOP4, UOP4 (0x4) },
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/* FIXME: mini or min? */
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{ "mini", { DOTDEST, SP, FDREG, FSREG, FTREG }, MURES + MUOP6, UOP6 (0x2f) },
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{ "mini", { DOTDEST, SP, FDREG, FSREG, 'i' }, MURES + UFT (~0) + MUOP6, UOP6 (0x1f) },
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{ "mini", { BC, DOTDEST, SP, FDREG, FSREG, FTREGBC }, MURES + MUOP4, UOP4 (0x5) },
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{ "msub", { DOTDEST, SP, FDREG, FSREG, FTREG }, MURES + MUOP6, UOP6 (0x2d) },
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{ "msubi", { DOTDEST, SP, FDREG, FSREG, 'i' }, MURES + UFT (~0) + MUOP6, UOP6 (0x27) },
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{ "msubq", { DOTDEST, SP, FDREG, FSREG, 'q' }, MURES + UFT (~0) + MUOP6, UOP6 (0x25) },
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{ "msub", { BC, DOTDEST, SP, FDREG, FSREG, FTREGBC }, MURES + MUOP4, UOP4 (0x3) },
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{ "msuba", { DOTDEST, SP, ACCDEST, FSREG, FTREG }, MURES + MUOP11, UOP11 (0x2fd) },
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{ "msubai", { DOTDEST, SP, ACCDEST, FSREG, 'i' }, MURES + UFT (~0) + MUOP11, UOP11 (0x27f) },
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{ "msubaq", { DOTDEST, SP, ACCDEST, FSREG, 'q' }, MURES + UFT (~0) + MUOP11, UOP11 (0x27d) },
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{ "msuba", { BC, DOTDEST, SP, ACCDEST, FSREG, FTREGBC }, MURES + MUOP9, UOP9 (0x3f) },
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{ "mul", { DOTDEST, SP, FDREG, FSREG, FTREG }, MURES + MUOP6, UOP6 (0x2a) },
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{ "muli", { DOTDEST, SP, FDREG, FSREG, 'i' }, MURES + UFT (~0) + MUOP6, UOP6 (0x1e) },
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{ "mulq", { DOTDEST, SP, FDREG, FSREG, 'q' }, MURES + UFT (~0) + MUOP6, UOP6 (0x1c) },
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{ "mul", { BC, DOTDEST, SP, FDREG, FSREG, FTREGBC }, MURES + UOP4 (~0), UOP4 (6) },
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{ "mula", { DOTDEST, SP, ACCDEST, FSREG, FTREG }, MURES + MUOP11, UOP11 (0x2be) },
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{ "mulai", { DOTDEST, SP, ACCDEST, FSREG, 'i' }, MURES + UFT (~0) + MUOP11, UOP11 (0x1fe) },
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{ "mulaq", { DOTDEST, SP, ACCDEST, FSREG, 'q' }, MURES + UFT (~0) + MUOP11, UOP11 (0x1fc) },
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{ "mula", { BC, DOTDEST, SP, ACCDEST, FSREG, FTREGBC }, MURES + MUOP9, UOP9 (0x6f) },
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{ "nop", { 0 }, MURES + UDEST (~0) + UFT (~0) + UFS (~0) + MUOP11, UOP11 (0x2ff) },
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{ "opmula", { DOTDEST, SP, ACCDEST, FSREG, FTREG, XYZ }, MURES + MUOP11, UOP11 (0x2fe) },
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{ "opmsub", { DOTDEST, SP, FDREG, FSREG, FTREG, XYZ }, MURES + MUOP6, UOP6 (0x2e) },
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{ "sub", { DOTDEST, SP, FDREG, FSREG, FTREG }, MURES + MUOP6, UOP6 (0x2c) },
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{ "subi", { DOTDEST, SP, FDREG, FSREG, 'i' }, MURES + UFT (~0) + MUOP6, UOP6 (0x26) },
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{ "subq", { DOTDEST, SP, FDREG, FSREG, 'q' }, MURES + UFT (~0) + MUOP6, UOP6 (0x24) },
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{ "sub", { BC, DOTDEST, SP, FDREG, FSREG, FTREGBC }, MURES + UOP4 (~0), UOP4 (1) },
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{ "suba", { DOTDEST, SP, ACCDEST, FSREG, FTREG }, MURES + MUOP11, UOP11 (0x2fc) },
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{ "subai", { DOTDEST, SP, ACCDEST, FSREG, 'i' }, MURES + UFT (~0) + MUOP11, UOP11 (0x27e) },
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{ "subaq", { DOTDEST, SP, ACCDEST, FSREG, 'q' }, MURES + UFT (~0) + MUOP11, UOP11 (0x27c) },
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{ "suba", { BC, DOTDEST, SP, ACCDEST, FSREG, FTREGBC }, MURES + MUOP9, UOP9 (0x1f) }
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};
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const int txvu_upper_opcodes_count = sizeof (txvu_upper_opcodes) / sizeof (txvu_opcodes[0]);
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struct txvu_opcode txvu_lower_opcodes[] = {
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/* Macros appear first. */
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/* ??? Any aliases? */
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/* The rest of these needn't be sorted, but it helps to find them if they
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are. */
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{ "waitp", { 0 }, 0xffffffff, 0x800007bf, 0 },
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{ "waitq", { 0 }, 0xffffffff, 0x800003bf, 0 },
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};
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const int txvu_lower_opcodes_count = sizeof (txvu_lower_opcodes) / sizeof (txvu_opcodes[0]);
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/* Indexed by first letter of opcode. Points to chain of opcodes with same
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first letter. */
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/* ??? One can certainly use a better hash. Later. */
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static struct txvu_opcode *upper_opcode_map[26 + 1];
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static struct txvu_opcode *lower_opcode_map[26 + 1];
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/* Indexed by insn code. Points to chain of opcodes with same insn code. */
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static struct txvu_opcode *upper_icode_map[64];
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static struct txvu_opcode *lower_icode_map[64];
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/* Initialize any tables that need it.
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Must be called once at start up (or when first needed).
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FLAGS is currently unused but is intended to control initialization. */
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void
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txvu_opcode_init_tables (flags)
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int flags;
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{
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static int init_p = 0;
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/* We may be intentionally called more than once (for example gdb will call
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us each time the user switches cpu). These tables only need to be init'd
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once though. */
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/* ??? We can remove the need for txvu_opcode_supported by taking it into
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account here, but I'm not sure I want to do that yet (if ever). */
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if (!init_p)
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{
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int i,n;
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memset (upper_opcode_map, 0, sizeof (upper_opcode_map));
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memset (upper_icode_map, 0, sizeof (upper_icode_map));
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/* Scan the table backwards so macros appear at the front. */
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for (i = txvu_upper_opcodes_count - 1; i >= 0; --i)
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{
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int opcode_hash = TXVU_HASH_UPPER_OPCODE (txvu_upper_opcodes[i].mnemonic);
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int icode_hash = TXVU_HASH_UPPER_ICODE (txvu_upper_opcodes[i].value);
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txvu_upper_opcodes[i].next_asm = upper_opcode_map[opcode_hash];
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upper_opcode_map[opcode_hash] = &txvu_upper_opcodes[i];
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txvu_upper_opcodes[i].next_dis = upper_icode_map[icode_hash];
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upper_icode_map[icode_hash] = &txvu_upper_opcodes[i];
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}
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memset (lower_opcode_map, 0, sizeof (lower_opcode_map));
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memset (lower_icode_map, 0, sizeof (lower_icode_map));
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/* Scan the table backwards so macros appear at the front. */
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for (i = txvu_lower_opcodes_count - 1; i >= 0; --i)
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{
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int opcode_hash = TXVU_HASH_LOWER_OPCODE (txvu_lower_opcodes[i].mnemonic);
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int icode_hash = TXVU_HASH_LOWER_ICODE (txvu_lower_opcodes[i].value);
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txvu_lower_opcodes[i].next_asm = lower_opcode_map[opcode_hash];
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lower_opcode_map[opcode_hash] = &txvu_lower_opcodes[i];
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txvu_lower_opcodes[i].next_dis = lower_icode_map[icode_hash];
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lower_icode_map[icode_hash] = &txvu_lower_opcodes[i];
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}
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init_p = 1;
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}
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}
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/* Return the first insn in the chain for assembling upper INSN. */
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const struct txvu_opcode *
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txvu_upper_opcode_lookup_asm (insn)
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const char *insn;
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{
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return upper_opcode_map[TXVU_HASH_UPPER_OPCODE (insn)];
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}
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/* Return the first insn in the chain for assembling lower INSN. */
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const struct txvu_opcode *
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txvu_lower_opcode_lookup_asm (insn)
|
||
const char *insn;
|
||
{
|
||
return lower_opcode_map[TXVU_HASH_LOWER_OPCODE (insn)];
|
||
}
|
||
|
||
/* Return the first insn in the chain for disassembling upper INSN. */
|
||
|
||
const struct txvu_opcode *
|
||
txvu_upper_opcode_lookup_dis (insn)
|
||
TXVU_INSN insn;
|
||
{
|
||
return upper_icode_map[TXVU_HASH_UPPER_ICODE (insn)];
|
||
}
|
||
|
||
/* Return the first insn in the chain for disassembling lower INSN. */
|
||
|
||
const struct txvu_opcode *
|
||
txvu_lower_opcode_lookup_dis (insn)
|
||
TXVU_INSN insn;
|
||
{
|
||
return lower_icode_map[TXVU_HASH_LOWER_ICODE (insn)];
|
||
}
|
||
|
||
/* Value of DEST in use.
|
||
Each of the registers must specify the same value as the opcode.
|
||
??? Perhaps remove the duplication? */
|
||
static int dest;
|
||
|
||
/* Value of BC to use.
|
||
The register specified for the ftreg must match the broadcast register
|
||
specified in the opcode. */
|
||
static int bc;
|
||
|
||
/* Init fns.
|
||
These are called before doing each of the respective activities. */
|
||
|
||
/* Called by the assembler before parsing an instruction. */
|
||
|
||
void
|
||
txvu_opcode_init_parse ()
|
||
{
|
||
dest = -1;
|
||
bc = -1;
|
||
}
|
||
|
||
/* Called by the disassembler before printing an instruction. */
|
||
|
||
void
|
||
txvu_opcode_init_print ()
|
||
{
|
||
dest = -1;
|
||
bc = -1;
|
||
}
|
||
|
||
/* Destination choice support.
|
||
The "dest" string selects any combination of x,y,z,w.
|
||
[The letters are ordered that way to follow the manual's style.] */
|
||
|
||
/* Parse a `dest' spec.
|
||
Return the found value.
|
||
*PSTR is set to the character that terminated the parsing.
|
||
It is up to the caller to do any error checking. */
|
||
|
||
static long
|
||
parse_dest (pstr)
|
||
char **pstr;
|
||
{
|
||
long dest = 0;
|
||
|
||
while (**pstr)
|
||
{
|
||
switch (**pstr)
|
||
{
|
||
case 'x' : case 'X' : dest |= TXVU_DEST_X; break;
|
||
case 'y' : case 'Y' : dest |= TXVU_DEST_Y; break;
|
||
case 'z' : case 'Z' : dest |= TXVU_DEST_Z; break;
|
||
case 'w' : case 'W' : dest |= TXVU_DEST_W; break;
|
||
default : return dest;
|
||
}
|
||
++*pstr;
|
||
}
|
||
|
||
return dest;
|
||
}
|
||
|
||
static long
|
||
parse_dotdest (pstr, errmsg)
|
||
char **pstr;
|
||
const char **errmsg;
|
||
{
|
||
long dest;
|
||
|
||
if (**pstr != '.')
|
||
{
|
||
*errmsg = "missing `.'";
|
||
return 0;
|
||
}
|
||
|
||
++*pstr;
|
||
dest = parse_dest (pstr);
|
||
if (dest == 0 || isalnum (**pstr))
|
||
{
|
||
*errmsg = "invalid `dest'";
|
||
return 0;
|
||
}
|
||
*errmsg = NULL;
|
||
return dest;
|
||
}
|
||
|
||
static TXVU_INSN
|
||
insert_dotdest (insn, operand, mods, value, errmsg)
|
||
TXVU_INSN insn;
|
||
const struct txvu_operand *operand;
|
||
int mods;
|
||
long value;
|
||
const char **errmsg;
|
||
{
|
||
/* Record the DEST value in use so the register parser can use it. */
|
||
dest = value;
|
||
if (errmsg)
|
||
*errmsg = NULL;
|
||
return insn |= value << operand->shift;
|
||
}
|
||
|
||
static long
|
||
extract_dotdest (insn, operand, mods, pinvalid)
|
||
TXVU_INSN insn;
|
||
const struct txvu_operand *operand;
|
||
int mods;
|
||
int *pinvalid;
|
||
{
|
||
/* Record the DEST value in use so the register printer can use it. */
|
||
dest = (insn >> operand->shift) & ((1 << operand->bits) - 1);
|
||
return dest;
|
||
}
|
||
|
||
static void
|
||
print_dest (info, insn, value)
|
||
disassemble_info *info;
|
||
TXVU_INSN insn;
|
||
long value;
|
||
{
|
||
if (value & TXVU_DEST_X)
|
||
(*info->fprintf_func) (info->stream, "x");
|
||
if (value & TXVU_DEST_Y)
|
||
(*info->fprintf_func) (info->stream, "y");
|
||
if (value & TXVU_DEST_Z)
|
||
(*info->fprintf_func) (info->stream, "z");
|
||
if (value & TXVU_DEST_W)
|
||
(*info->fprintf_func) (info->stream, "w");
|
||
}
|
||
|
||
static void
|
||
print_dotdest (info, insn, value)
|
||
disassemble_info *info;
|
||
TXVU_INSN insn;
|
||
long value;
|
||
{
|
||
(*info->fprintf_func) (info->stream, ".");
|
||
print_dest (info, insn, value);
|
||
}
|
||
|
||
static long
|
||
parse_vfreg (pstr, errmsg)
|
||
char **pstr;
|
||
const char **errmsg;
|
||
{
|
||
char *str = *pstr;
|
||
char *start;
|
||
long reg;
|
||
int reg_dest;
|
||
|
||
if (tolower (str[0]) != 'v'
|
||
|| tolower (str[1]) != 'f')
|
||
{
|
||
*errmsg = "unknown register";
|
||
return 0;
|
||
}
|
||
|
||
/* FIXME: quick hack until the framework works. */
|
||
start = str = str + 2;
|
||
while (*str && isdigit (*str))
|
||
++str;
|
||
reg = atoi (start);
|
||
reg_dest = parse_dest (&str);
|
||
if (reg_dest == 0 || isalnum (*str))
|
||
{
|
||
*errmsg = "invalid `dest'";
|
||
return 0;
|
||
}
|
||
if (reg_dest != dest)
|
||
{
|
||
*errmsg = "register `dest' does not match instruction `dest'";
|
||
return 0;
|
||
}
|
||
*pstr = str;
|
||
*errmsg = NULL;
|
||
return reg;
|
||
}
|
||
|
||
static void
|
||
print_vfreg (info, insn, value)
|
||
disassemble_info *info;
|
||
TXVU_INSN insn;
|
||
long value;
|
||
{
|
||
(*info->fprintf_func) (info->stream, "vf%ld", value);
|
||
print_dest (info, insn, dest);
|
||
}
|
||
|
||
/* Broadcast handling. */
|
||
|
||
static long
|
||
parse_bc (pstr, errmsg)
|
||
char **pstr;
|
||
const char **errmsg;
|
||
{
|
||
long dest = 0;
|
||
|
||
switch (**pstr)
|
||
{
|
||
case 'x' : case 'X' : dest = TXVU_BC_X; break;
|
||
case 'y' : case 'Y' : dest = TXVU_BC_Y; break;
|
||
case 'z' : case 'Z' : dest = TXVU_BC_Z; break;
|
||
case 'w' : case 'W' : dest = TXVU_BC_W; break;
|
||
default : *errmsg = "invalid `bc'"; return 0;
|
||
}
|
||
++*pstr;
|
||
|
||
*errmsg = NULL;
|
||
return dest;
|
||
}
|
||
|
||
static void
|
||
print_bc (info, insn, value)
|
||
disassemble_info *info;
|
||
TXVU_INSN insn;
|
||
long value;
|
||
{
|
||
char c;
|
||
|
||
switch (value)
|
||
{
|
||
case TXVU_BC_X : c = 'x' ; break;
|
||
case TXVU_BC_Y : c = 'y' ; break;
|
||
case TXVU_BC_Z : c = 'z' ; break;
|
||
case TXVU_BC_W : c = 'w' ; break;
|
||
}
|
||
|
||
(*info->fprintf_func) (info->stream, "%c", c);
|
||
}
|
||
|
||
/* FT register in broadcast case. */
|
||
|
||
static long
|
||
parse_ftregbc (pstr, errmsg)
|
||
char **pstr;
|
||
const char **errmsg;
|
||
{
|
||
char *str = *pstr;
|
||
char *start;
|
||
long reg;
|
||
int reg_bc;
|
||
|
||
if (tolower (str[0]) != 'v'
|
||
|| tolower (str[1]) != 'f')
|
||
{
|
||
*errmsg = "unknown register";
|
||
return 0;
|
||
}
|
||
|
||
/* FIXME: quick hack until the framework works. */
|
||
start = str = str + 2;
|
||
while (*str && isdigit (*str))
|
||
++str;
|
||
reg = atoi (start);
|
||
reg_bc = parse_bc (&str, errmsg);
|
||
if (*errmsg)
|
||
return 0;
|
||
if (reg_bc != bc)
|
||
{
|
||
*errmsg = "register `bc' does not match instruction `bc'";
|
||
return 0;
|
||
}
|
||
*pstr = str;
|
||
*errmsg = NULL;
|
||
return reg;
|
||
}
|
||
|
||
static void
|
||
print_ftregbc (info, insn, value)
|
||
disassemble_info *info;
|
||
TXVU_INSN insn;
|
||
long value;
|
||
{
|
||
(*info->fprintf_func) (info->stream, "vf%ld", value);
|
||
print_bc (info, insn, bc);
|
||
}
|
||
|
||
/* ACC handling. */
|
||
|
||
static long
|
||
parse_accdest (pstr, errmsg)
|
||
char **pstr;
|
||
const char **errmsg;
|
||
{
|
||
char *str = *pstr;
|
||
long acc_dest = 0;
|
||
|
||
if (strncasecmp (str, "acc", 3) != 0)
|
||
{
|
||
*errmsg = "expecting `acc'";
|
||
return 0;
|
||
}
|
||
str += 3;
|
||
acc_dest = parse_dest (&str);
|
||
if (acc_dest == 0 || isalnum (*str))
|
||
{
|
||
*errmsg = "invalid `dest'";
|
||
return 0;
|
||
}
|
||
if (acc_dest != dest)
|
||
{
|
||
*errmsg = "acc `dest' does not match instruction `dest'";
|
||
return 0;
|
||
}
|
||
*pstr = str;
|
||
*errmsg = NULL;
|
||
/* Value isn't used, but we must return something. */
|
||
return 0;
|
||
}
|
||
|
||
static void
|
||
print_accdest (info, insn, value)
|
||
disassemble_info *info;
|
||
TXVU_INSN insn;
|
||
long value;
|
||
{
|
||
(*info->fprintf_func) (info->stream, "acc");
|
||
print_dest (info, insn, value);
|
||
}
|
||
|
||
/* XYZ operand handling.
|
||
This simplifies the opmula,opmsub entries by keeping them equivalent to
|
||
the others. */
|
||
|
||
static long
|
||
parse_xyz (pstr, errmsg)
|
||
char **pstr;
|
||
const char **errmsg;
|
||
{
|
||
if (dest != (TXVU_DEST_X | TXVU_DEST_Y | TXVU_DEST_Z))
|
||
{
|
||
*errmsg = "expecting `xyz' for `dest' value";
|
||
return 0;
|
||
}
|
||
return 0;
|
||
}
|