639 lines
21 KiB
C
639 lines
21 KiB
C
/* Disassembler interface for targets using CGEN. -*- C -*-
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CGEN: Cpu tools GENerator
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This file is used to generate m32r-dis.c.
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Copyright (C) 1996, 1997 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "ansidecl.h"
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#include "dis-asm.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "m32r-opc.h"
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/* ??? The layout of this stuff is still work in progress.
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For speed in assembly/disassembly, we use inline functions. That of course
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will only work for GCC. When this stuff is finished, we can decide whether
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to keep the inline functions (and only get the performance increase when
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compiled with GCC), or switch to macros, or use something else.
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*/
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/* Default text to print if an instruction isn't recognized. */
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#define UNKNOWN_INSN_MSG "*unknown*"
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/* FIXME: Machine generate. */
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#ifndef CGEN_PCREL_OFFSET
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#define CGEN_PCREL_OFFSET 0
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#endif
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static int print_insn PARAMS ((bfd_vma, disassemble_info *, char *, int));
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static int extract_insn_normal
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PARAMS ((const CGEN_INSN *, void *, cgen_insn_t, CGEN_FIELDS *));
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static void print_insn_normal
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PARAMS ((void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int));
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/* Default extraction routine.
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ATTRS is a mask of the boolean attributes. We only need `unsigned',
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but for generality we take a bitmask of all of them. */
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static int
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extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length, valuep)
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PTR buf_ctrl;
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cgen_insn_t insn_value;
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unsigned int attrs;
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int start, length, shift, total_length;
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long *valuep;
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{
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long value;
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#ifdef CGEN_INT_INSN
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#if 0
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value = ((insn_value >> (CGEN_BASE_INSN_BITSIZE - (start + length)))
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& ((1 << length) - 1));
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#else
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value = ((insn_value >> (total_length - (start + length)))
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& ((1 << length) - 1));
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#endif
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if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
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&& (value & (1 << (length - 1))))
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value -= 1 << length;
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#else
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/* FIXME: unfinished */
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#endif
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/* This is backwards as we undo the effects of insert_normal. */
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if (shift < 0)
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value >>= -shift;
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else
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value <<= shift;
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*valuep = value;
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/* FIXME: for now */
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return 1;
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}
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/* Default print handler. */
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static void
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print_normal (dis_info, value, attrs, pc, length)
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PTR dis_info;
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long value;
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unsigned int attrs;
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unsigned long pc; /* FIXME: should be bfd_vma */
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int length;
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{
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disassemble_info *info = dis_info;
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/* Print the operand as directed by the attributes. */
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if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_FAKE))
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; /* nothing to do (??? at least not yet) */
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else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_PCREL_ADDR))
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(*info->print_address_func) (pc + CGEN_PCREL_OFFSET + value, info);
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/* ??? Not all cases of this are currently caught. */
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else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_ABS_ADDR))
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/* FIXME: Why & 0xffffffff? */
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(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
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else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
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(*info->fprintf_func) (info->stream, "0x%lx", value);
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else
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(*info->fprintf_func) (info->stream, "%ld", value);
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}
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/* Keyword print handler. */
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static void
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print_keyword (dis_info, keyword_table, value, attrs)
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PTR dis_info;
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CGEN_KEYWORD *keyword_table;
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long value;
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CGEN_ATTR *attrs;
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{
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disassemble_info *info = dis_info;
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const CGEN_KEYWORD_ENTRY *ke;
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ke = cgen_keyword_lookup_value (keyword_table, value);
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if (ke != NULL)
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(*info->fprintf_func) (info->stream, "%s", ke->name);
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else
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(*info->fprintf_func) (info->stream, "???");
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}
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/* -- disassembler routines inserted here */
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/* -- dis.c */
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#undef CGEN_PRINT_INSN
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#define CGEN_PRINT_INSN my_print_insn
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static int
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my_print_insn (pc, info, buf, buflen)
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bfd_vma pc;
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disassemble_info *info;
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char *buf;
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int buflen;
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{
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/* 32 bit insn? */
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if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
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return print_insn (pc, info, buf, buflen);
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/* Print the first insn. */
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if ((pc & 3) == 0)
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{
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if (print_insn (pc, info, buf, 16) == 0)
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(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
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buf += 2;
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}
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if (buf[0] & 0x80)
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{
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/* Parallel. */
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(*info->fprintf_func) (info->stream, " || ");
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buf[0] &= 0x7f;
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}
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else
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(*info->fprintf_func) (info->stream, " -> ");
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/* The "& 3" is to ensure the branch address is computed correctly
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[if it is a branch]. */
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if (print_insn (pc & ~ (bfd_vma) 3, info, buf, 16) == 0)
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(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
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return (pc & 3) ? 2 : 4;
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}
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/* -- */
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/* Main entry point for operand extraction.
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This function is basically just a big switch statement. Earlier versions
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used tables to look up the function to use, but
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- if the table contains both assembler and disassembler functions then
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the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
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- using a switch statement avoids the function call overhead.
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This function could be moved into `print_insn_normal', but keeping it
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separate makes clear the interface between `print_insn_normal' and each of
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the handlers.
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*/
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int
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m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields)
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int opindex;
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PTR buf_ctrl;
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cgen_insn_t insn_value;
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CGEN_FIELDS * fields;
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{
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int length;
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switch (opindex)
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{
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case M32R_OPERAND_SR :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
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break;
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case M32R_OPERAND_DR :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
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break;
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case M32R_OPERAND_SRC1 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
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break;
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case M32R_OPERAND_SRC2 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
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break;
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case M32R_OPERAND_SCR :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
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break;
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case M32R_OPERAND_DCR :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
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break;
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case M32R_OPERAND_SIMM8 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm8);
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break;
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case M32R_OPERAND_SIMM16 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm16);
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break;
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case M32R_OPERAND_UIMM4 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm4);
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break;
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case M32R_OPERAND_UIMM5 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm5);
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break;
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case M32R_OPERAND_UIMM16 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm16);
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break;
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/* start-sanitize-m32rx */
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case M32R_OPERAND_IMM1 :
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{
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long value;
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 15, 1, 0, CGEN_FIELDS_BITSIZE (fields), & value);
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fields->f_imm1 = ((value) + (1));
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}
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break;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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case M32R_OPERAND_ACCD :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 2, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_accd);
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break;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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case M32R_OPERAND_ACCS :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_accs);
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break;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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case M32R_OPERAND_ACC :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_acc);
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break;
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/* end-sanitize-m32rx */
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case M32R_OPERAND_HI16 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_hi16);
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break;
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case M32R_OPERAND_SLO16 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm16);
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break;
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case M32R_OPERAND_ULO16 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm16);
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break;
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case M32R_OPERAND_UIMM24 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm24);
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break;
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case M32R_OPERAND_DISP8 :
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{
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long value;
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), & value);
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fields->f_disp8 = ((value) << (2));
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}
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break;
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case M32R_OPERAND_DISP16 :
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{
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long value;
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & value);
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fields->f_disp16 = ((value) << (2));
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}
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break;
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case M32R_OPERAND_DISP24 :
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{
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long value;
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), & value);
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fields->f_disp24 = ((value) << (2));
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}
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break;
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default :
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fprintf (stderr, "Unrecognized field %d while decoding insn.\n",
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opindex);
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abort ();
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}
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return length;
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}
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/* Main entry point for printing operands.
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This function is basically just a big switch statement. Earlier versions
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used tables to look up the function to use, but
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- if the table contains both assembler and disassembler functions then
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the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
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- using a switch statement avoids the function call overhead.
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This function could be moved into `print_insn_normal', but keeping it
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separate makes clear the interface between `print_insn_normal' and each of
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the handlers.
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*/
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void
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m32r_cgen_print_operand (opindex, info, fields, attrs, pc, length)
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int opindex;
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disassemble_info * info;
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CGEN_FIELDS * fields;
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void const * attrs;
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bfd_vma pc;
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int length;
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{
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switch (opindex)
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{
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case M32R_OPERAND_SR :
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print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case M32R_OPERAND_DR :
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print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case M32R_OPERAND_SRC1 :
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print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case M32R_OPERAND_SRC2 :
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print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case M32R_OPERAND_SCR :
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print_keyword (info, & m32r_cgen_opval_h_cr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case M32R_OPERAND_DCR :
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print_keyword (info, & m32r_cgen_opval_h_cr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case M32R_OPERAND_SIMM8 :
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print_normal (info, fields->f_simm8, 0, pc, length);
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break;
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case M32R_OPERAND_SIMM16 :
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print_normal (info, fields->f_simm16, 0, pc, length);
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break;
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case M32R_OPERAND_UIMM4 :
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print_normal (info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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case M32R_OPERAND_UIMM5 :
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print_normal (info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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case M32R_OPERAND_UIMM16 :
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print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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/* start-sanitize-m32rx */
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case M32R_OPERAND_IMM1 :
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print_normal (info, fields->f_imm1, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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case M32R_OPERAND_ACCD :
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print_keyword (info, & m32r_cgen_opval_h_accums, fields->f_accd, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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case M32R_OPERAND_ACCS :
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print_keyword (info, & m32r_cgen_opval_h_accums, fields->f_accs, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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case M32R_OPERAND_ACC :
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print_keyword (info, & m32r_cgen_opval_h_accums, fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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/* end-sanitize-m32rx */
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case M32R_OPERAND_HI16 :
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print_normal (info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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case M32R_OPERAND_SLO16 :
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print_normal (info, fields->f_simm16, 0, pc, length);
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break;
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case M32R_OPERAND_ULO16 :
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print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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case M32R_OPERAND_UIMM24 :
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print_normal (info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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case M32R_OPERAND_DISP8 :
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print_normal (info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
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break;
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case M32R_OPERAND_DISP16 :
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print_normal (info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
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break;
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case M32R_OPERAND_DISP24 :
|
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print_normal (info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
|
||
break;
|
||
|
||
default :
|
||
fprintf (stderr, "Unrecognized field %d while printing insn.\n",
|
||
opindex);
|
||
abort ();
|
||
}
|
||
}
|
||
|
||
cgen_extract_fn * m32r_cgen_extract_handlers[] =
|
||
{
|
||
0, /* default */
|
||
extract_insn_normal,
|
||
};
|
||
|
||
cgen_print_fn * m32r_cgen_print_handlers[] =
|
||
{
|
||
0, /* default */
|
||
print_insn_normal,
|
||
};
|
||
|
||
|
||
void
|
||
m32r_cgen_init_dis (mach, endian)
|
||
int mach;
|
||
enum cgen_endian endian;
|
||
{
|
||
m32r_cgen_init_tables (mach);
|
||
cgen_set_cpu (& m32r_cgen_opcode_data, mach, endian);
|
||
cgen_dis_init ();
|
||
}
|
||
|
||
|
||
/* Default insn extractor.
|
||
|
||
The extracted fields are stored in DIS_FLDS.
|
||
BUF_CTRL is used to handle reading variable length insns (FIXME: not done).
|
||
Return the length of the insn in bits, or 0 if no match. */
|
||
|
||
static int
|
||
extract_insn_normal (insn, buf_ctrl, insn_value, fields)
|
||
const CGEN_INSN *insn;
|
||
PTR buf_ctrl;
|
||
cgen_insn_t insn_value;
|
||
CGEN_FIELDS *fields;
|
||
{
|
||
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
|
||
const unsigned char *syn;
|
||
|
||
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
|
||
|
||
CGEN_INIT_EXTRACT ();
|
||
|
||
for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
|
||
{
|
||
int length;
|
||
|
||
if (CGEN_SYNTAX_CHAR_P (*syn))
|
||
continue;
|
||
|
||
length = m32r_cgen_extract_operand (CGEN_SYNTAX_FIELD (*syn),
|
||
buf_ctrl, insn_value, fields);
|
||
if (length == 0)
|
||
return 0;
|
||
}
|
||
|
||
/* We recognized and successfully extracted this insn. */
|
||
return CGEN_INSN_BITSIZE (insn);
|
||
}
|
||
|
||
/* Default insn printer.
|
||
|
||
DIS_INFO is defined as `PTR' so the disassembler needn't know anything
|
||
about disassemble_info.
|
||
*/
|
||
|
||
static void
|
||
print_insn_normal (dis_info, insn, fields, pc, length)
|
||
PTR dis_info;
|
||
const CGEN_INSN *insn;
|
||
CGEN_FIELDS *fields;
|
||
bfd_vma pc;
|
||
int length;
|
||
{
|
||
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
|
||
disassemble_info *info = dis_info;
|
||
const unsigned char *syn;
|
||
|
||
CGEN_INIT_PRINT ();
|
||
|
||
for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
|
||
{
|
||
if (CGEN_SYNTAX_MNEMONIC_P (*syn))
|
||
{
|
||
(*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
|
||
continue;
|
||
}
|
||
if (CGEN_SYNTAX_CHAR_P (*syn))
|
||
{
|
||
(*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
|
||
continue;
|
||
}
|
||
|
||
/* We have an operand. */
|
||
m32r_cgen_print_operand (CGEN_SYNTAX_FIELD (*syn), info,
|
||
fields, CGEN_INSN_ATTRS (insn), pc, length);
|
||
}
|
||
}
|
||
|
||
/* Default value for CGEN_PRINT_INSN.
|
||
Given BUFLEN bits (target byte order) read into BUF, look up the
|
||
insn in the instruction table and disassemble it.
|
||
|
||
The result is the size of the insn in bytes. */
|
||
|
||
#ifndef CGEN_PRINT_INSN
|
||
#define CGEN_PRINT_INSN print_insn
|
||
#endif
|
||
|
||
static int
|
||
print_insn (pc, info, buf, buflen)
|
||
bfd_vma pc;
|
||
disassemble_info *info;
|
||
char *buf;
|
||
int buflen;
|
||
{
|
||
unsigned long insn_value;
|
||
const CGEN_INSN_LIST *insn_list;
|
||
|
||
switch (buflen)
|
||
{
|
||
case 8:
|
||
insn_value = buf[0];
|
||
break;
|
||
case 16:
|
||
insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf);
|
||
break;
|
||
case 32:
|
||
insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf);
|
||
break;
|
||
default:
|
||
abort ();
|
||
}
|
||
|
||
/* The instructions are stored in hash lists.
|
||
Pick the first one and keep trying until we find the right one. */
|
||
|
||
insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
|
||
while (insn_list != NULL)
|
||
{
|
||
const CGEN_INSN *insn = insn_list->insn;
|
||
CGEN_FIELDS fields;
|
||
int length;
|
||
|
||
#if 0 /* not needed as insn shouldn't be in hash lists if not supported */
|
||
/* Supported by this cpu? */
|
||
if (! m32r_cgen_insn_supported (insn))
|
||
continue;
|
||
#endif
|
||
|
||
/* Basic bit mask must be correct. */
|
||
/* ??? May wish to allow target to defer this check until the extract
|
||
handler. */
|
||
if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
|
||
{
|
||
/* Printing is handled in two passes. The first pass parses the
|
||
machine insn and extracts the fields. The second pass prints
|
||
them. */
|
||
|
||
length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, &fields);
|
||
if (length > 0)
|
||
{
|
||
(*CGEN_PRINT_FN (insn)) (info, insn, &fields, pc, length);
|
||
/* length is in bits, result is in bytes */
|
||
return length / 8;
|
||
}
|
||
}
|
||
|
||
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
|
||
}
|
||
|
||
return 0;
|
||
}
|
||
|
||
/* Main entry point.
|
||
Print one instruction from PC on INFO->STREAM.
|
||
Return the size of the instruction (in bytes). */
|
||
|
||
int
|
||
print_insn_m32r (pc, info)
|
||
bfd_vma pc;
|
||
disassemble_info *info;
|
||
{
|
||
char buffer[CGEN_MAX_INSN_SIZE];
|
||
int status, length;
|
||
static int initialized = 0;
|
||
static int current_mach = 0;
|
||
static int current_big_p = 0;
|
||
int mach = info->mach;
|
||
int big_p = info->endian == BFD_ENDIAN_BIG;
|
||
|
||
/* If we haven't initialized yet, or if we've switched cpu's, initialize. */
|
||
if (!initialized || mach != current_mach || big_p != current_big_p)
|
||
{
|
||
initialized = 1;
|
||
current_mach = mach;
|
||
current_big_p = big_p;
|
||
m32r_cgen_init_dis (mach, big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
|
||
}
|
||
|
||
/* Read enough of the insn so we can look it up in the hash lists. */
|
||
|
||
status = (*info->read_memory_func) (pc, buffer, CGEN_BASE_INSN_SIZE, info);
|
||
if (status != 0)
|
||
{
|
||
(*info->memory_error_func) (status, pc, info);
|
||
return -1;
|
||
}
|
||
|
||
/* We try to have as much common code as possible.
|
||
But at this point some targets need to take over. */
|
||
/* ??? Some targets may need a hook elsewhere. Try to avoid this,
|
||
but if not possible try to move this hook elsewhere rather than
|
||
have two hooks. */
|
||
length = CGEN_PRINT_INSN (pc, info, buffer, CGEN_BASE_INSN_BITSIZE);
|
||
if (length)
|
||
return length;
|
||
|
||
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
|
||
return CGEN_DEFAULT_INSN_SIZE;
|
||
}
|