Andrew Cagney 37a684b84d o Make tic80 insn file more `cache ready' ... o Have igen always zero r0 instead of constantly checking if the designated register is r0.		1997-05-16 03:27:40 +00:00
..
.Sanitize	o Clean-up tic80 fp tracing	1997-05-07 13:58:52 +00:00
alu.h	Remove ANNULed cycle - was confusing gdb.	1997-05-13 13:57:49 +00:00
ChangeLog	o Make tic80 insn file more `cache ready'	1997-05-16 03:27:40 +00:00
config.in	TIc80 simulator checkpoint - runs 3 instructions - trap, addu, br.a.	1997-04-22 17:46:07 +00:00
configure	* configure: Regenerated to track ../common/aclocal.m4 changes.	1997-04-24 07:58:17 +00:00
configure.in	Start of implementation of a distributed (between processors)	1997-05-05 13:21:04 +00:00
cpu.h	o Make tic80 insn file more `cache ready'	1997-05-16 03:27:40 +00:00
dc	Enable more instructions.	1997-04-24 12:06:27 +00:00
ic	o Make tic80 insn file more `cache ready'	1997-05-16 03:27:40 +00:00
insns	o Make tic80 insn file more `cache ready'	1997-05-16 03:27:40 +00:00
interp.c	o Make tic80 insn file more `cache ready'	1997-05-16 03:27:40 +00:00
Makefile.in	o Make tic80 insn file more `cache ready'	1997-05-16 03:27:40 +00:00
misc.c	Fix double conversion problem.	1997-05-15 02:21:11 +00:00
sim-calls.c	o Make tic80 insn file more `cache ready'	1997-05-16 03:27:40 +00:00
sim-main.h	c80 simulator fixes.	1997-05-12 04:57:49 +00:00