old-cross-binutils/ld/testsuite/ld-aarch64/farcall-bl-section.d
Jiong Wang 2f340668a9 [AArch64] Relax long branch veneer insertion for non STT_FUNC symbol
As defined at AArch64 ELF Specification (4.6.7 Call and Jump
  relocations), symbol with type of non STT_FUNC but in different input
  section with relocation place should insert long branch veneer also.

  Meanwhile the current long branch veneer infrastructure havn't considered
  the situation where the branch destination is "sym_value + rela->addend".

  This was OK because we only insert veneer for long call destination is
  STT_FUNC symbol for which the addend is always zero. But as we relax the
  support to other situations by this patch, we need to handle addend be
  non-zero value. For example, for static function, relocation against
  "local symbol" are turned into relocation against "section symbol + offset"
  where there is a valid addend.

  bfd/
	* elfnn-aarch64.c (aarch64_type_of_stub): Allow insert long branch
	veneer for sym_sec != input_sec.
	(elfNN_aarch64_size_stub): Support STT_SECTION symbol.
	(elfNN_aarch64_final_link_relocate): Take rela addend into account when
	calculation destination.

  ld/
	* testsuite/ld-aarch64/farcall-section.d: Delete.
	* testsuite/ld-aarch64/farcall-section.s: Delete.
	* testsuite/ld-aarch64/farcall-b-section.d: New expectation file.
	* testsuite/ld-aarch64/farcall-bl-section.d: Likewise.
	* testsuite/ld-aarch64/farcall-b-section.s: New testcase.
	* testsuite/ld-aarch64/farcall-bl-section.s: Likewise.
	* testsuite/ld-aarch64/aarch64-elf.exp: Likewise.
2016-01-21 09:57:09 +00:00

34 lines
741 B
Makefile

#name: aarch64-farcall-bl-section
#source: farcall-bl-section.s
#as:
#ld: -Ttext 0x1000 --section-start .foo=0x8001000
#objdump: -dr
#...
Disassembly of section .text:
.* <_start>:
1000: 94000008 bl 1020 <___veneer>
1004: 94000003 bl 1010 <___veneer>
1008: d65f03c0 ret
100c: 1400000d b 1040 <___veneer\+0x20>
.* <___veneer>:
1010: 90040010 adrp x16, 8001000 <bar>
1014: 91001210 add x16, x16, #0x4
1018: d61f0200 br x16
101c: 00000000 .inst 0x00000000 ; undefined
.* <___veneer>:
1020: 90040010 adrp x16, 8001000 <bar>
1024: 91000210 add x16, x16, #0x0
1028: d61f0200 br x16
...
Disassembly of section .foo:
.* <bar>:
8001000: d65f03c0 ret
.* <bar2>:
8001004: d65f03c0 ret