421 lines
12 KiB
C
421 lines
12 KiB
C
/* armcopro.c -- co-processor interface: ARM6 Instruction Emulator.
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Copyright (C) 1994, 2000 Advanced RISC Machines Ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "armdefs.h"
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#include "ansidecl.h"
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extern unsigned ARMul_CoProInit (ARMul_State * state);
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extern void ARMul_CoProExit (ARMul_State * state);
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extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
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ARMul_CPInits * init, ARMul_CPExits * exit,
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ARMul_LDCs * ldc, ARMul_STCs * stc,
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ARMul_MRCs * mrc, ARMul_MCRs * mcr,
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ARMul_CDPs * cdp,
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ARMul_CPReads * read, ARMul_CPWrites * write);
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extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
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/***************************************************************************\
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* Dummy Co-processors *
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\***************************************************************************/
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static unsigned NoCoPro3R (ARMul_State * state, unsigned, ARMword);
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static unsigned NoCoPro4R (ARMul_State * state, unsigned, ARMword, ARMword);
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static unsigned NoCoPro4W (ARMul_State * state, unsigned, ARMword, ARMword *);
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/***************************************************************************\
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* Define Co-Processor instruction handlers here *
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\***************************************************************************/
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/* Here's ARMulator's MMU definition. A few things to note:
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1) it has eight registers, but only two are defined.
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2) you can only access its registers with MCR and MRC.
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3) MMU Register 0 (ID) returns 0x41440110
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4) Register 1 only has 4 bits defined. Bits 0 to 3 are unused, bit 4
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controls 32/26 bit program space, bit 5 controls 32/26 bit data space,
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bit 6 controls late abort timimg and bit 7 controls big/little endian.
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*/
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static ARMword MMUReg[8];
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static unsigned
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MMUInit (ARMul_State * state)
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{
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MMUReg[1] = state->prog32Sig << 4 |
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state->data32Sig << 5 | state->lateabtSig << 6 | state->bigendSig << 7;
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ARMul_ConsolePrint (state, ", MMU present");
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return (TRUE);
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}
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static unsigned
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MMUMRC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword * value)
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{
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int reg = BITS (16, 19) & 7;
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if (reg == 0)
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*value = 0x41440110;
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else
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*value = MMUReg[reg];
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return (ARMul_DONE);
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}
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static unsigned
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MMUMCR (ARMul_State * state, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword value)
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{
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int reg = BITS (16, 19) & 7;
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MMUReg[reg] = value;
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if (reg == 1)
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{
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state->prog32Sig = value >> 4 & 1;
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state->data32Sig = value >> 5 & 1;
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state->lateabtSig = value >> 6 & 1;
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state->bigendSig = value >> 7 & 1;
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state->Emulate = TRUE; /* force ARMulator to notice these now ! */
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}
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return (ARMul_DONE);
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}
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static unsigned
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MMURead (ARMul_State * state ATTRIBUTE_UNUSED, unsigned reg, ARMword * value)
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{
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if (reg == 0)
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*value = 0x41440110;
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else if (reg < 8)
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*value = MMUReg[reg];
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return (TRUE);
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}
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static unsigned
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MMUWrite (ARMul_State * state, unsigned reg, ARMword value)
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{
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if (reg < 8)
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MMUReg[reg] = value;
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if (reg == 1)
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{
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state->prog32Sig = value >> 4 & 1;
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state->data32Sig = value >> 5 & 1;
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state->lateabtSig = value >> 6 & 1;
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state->bigendSig = value >> 7 & 1;
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state->Emulate = TRUE; /* force ARMulator to notice these now ! */
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}
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return (TRUE);
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}
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/* What follows is the Validation Suite Coprocessor. It uses two
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co-processor numbers (4 and 5) and has the follwing functionality.
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Sixteen registers. Both co-processor nuimbers can be used in an MCR and
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MRC to access these registers. CP 4 can LDC and STC to and from the
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registers. CP 4 and CP 5 CDP 0 will busy wait for the number of cycles
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specified by a CP register. CP 5 CDP 1 issues a FIQ after a number of
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cycles (specified in a CP register), CDP 2 issues an IRQW in the same
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way, CDP 3 and 4 turn of the FIQ and IRQ source, and CDP 5 stores a 32
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bit time value in a CP register (actually it's the total number of N, S,
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I, C and F cyles) */
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static ARMword ValReg[16];
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static unsigned
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ValLDC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type, ARMword instr, ARMword data)
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{
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static unsigned words;
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if (type != ARMul_DATA)
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{
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words = 0;
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return (ARMul_DONE);
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}
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if (BIT (22))
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{ /* it's a long access, get two words */
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ValReg[BITS (12, 15)] = data;
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if (words++ == 4)
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return (ARMul_DONE);
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else
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return (ARMul_INC);
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}
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else
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{ /* get just one word */
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ValReg[BITS (12, 15)] = data;
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return (ARMul_DONE);
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}
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}
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static unsigned
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ValSTC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type, ARMword instr, ARMword * data)
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{
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static unsigned words;
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if (type != ARMul_DATA)
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{
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words = 0;
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return (ARMul_DONE);
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}
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if (BIT (22))
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{ /* it's a long access, get two words */
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*data = ValReg[BITS (12, 15)];
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if (words++ == 4)
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return (ARMul_DONE);
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else
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return (ARMul_INC);
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}
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else
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{ /* get just one word */
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*data = ValReg[BITS (12, 15)];
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return (ARMul_DONE);
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}
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}
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static unsigned
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ValMRC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword * value)
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{
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*value = ValReg[BITS (16, 19)];
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return (ARMul_DONE);
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}
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static unsigned
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ValMCR (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword value)
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{
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ValReg[BITS (16, 19)] = value;
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return (ARMul_DONE);
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}
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static unsigned
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ValCDP (ARMul_State * state, unsigned type, ARMword instr)
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{
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static unsigned long finish = 0;
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ARMword howlong;
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howlong = ValReg[BITS (0, 3)];
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if (BITS (20, 23) == 0)
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{
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if (type == ARMul_FIRST)
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{ /* First cycle of a busy wait */
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finish = ARMul_Time (state) + howlong;
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if (howlong == 0)
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return (ARMul_DONE);
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else
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return (ARMul_BUSY);
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}
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else if (type == ARMul_BUSY)
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{
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if (ARMul_Time (state) >= finish)
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return (ARMul_DONE);
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else
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return (ARMul_BUSY);
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}
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}
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return (ARMul_CANT);
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}
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static unsigned
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DoAFIQ (ARMul_State * state)
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{
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state->NfiqSig = LOW;
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state->Exception++;
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return (0);
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}
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static unsigned
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DoAIRQ (ARMul_State * state)
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{
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state->NirqSig = LOW;
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state->Exception++;
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return (0);
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}
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static unsigned
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IntCDP (ARMul_State * state, unsigned type, ARMword instr)
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{
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static unsigned long finish;
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ARMword howlong;
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howlong = ValReg[BITS (0, 3)];
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switch ((int) BITS (20, 23))
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{
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case 0:
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if (type == ARMul_FIRST)
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{ /* First cycle of a busy wait */
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finish = ARMul_Time (state) + howlong;
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if (howlong == 0)
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return (ARMul_DONE);
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else
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return (ARMul_BUSY);
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}
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else if (type == ARMul_BUSY)
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{
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if (ARMul_Time (state) >= finish)
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return (ARMul_DONE);
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else
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return (ARMul_BUSY);
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}
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return (ARMul_DONE);
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case 1:
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if (howlong == 0)
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ARMul_Abort (state, ARMul_FIQV);
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else
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ARMul_ScheduleEvent (state, howlong, DoAFIQ);
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return (ARMul_DONE);
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case 2:
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if (howlong == 0)
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ARMul_Abort (state, ARMul_IRQV);
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else
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ARMul_ScheduleEvent (state, howlong, DoAIRQ);
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return (ARMul_DONE);
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case 3:
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state->NfiqSig = HIGH;
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state->Exception--;
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return (ARMul_DONE);
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case 4:
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state->NirqSig = HIGH;
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state->Exception--;
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return (ARMul_DONE);
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case 5:
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ValReg[BITS (0, 3)] = ARMul_Time (state);
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return (ARMul_DONE);
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}
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return (ARMul_CANT);
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}
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/***************************************************************************\
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* Install co-processor instruction handlers in this routine *
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\***************************************************************************/
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unsigned
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ARMul_CoProInit (ARMul_State * state)
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{
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register unsigned i;
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for (i = 0; i < 16; i++) /* initialise tham all first */
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ARMul_CoProDetach (state, i);
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/* Install CoPro Instruction handlers here
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The format is
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ARMul_CoProAttach(state, CP Number, Init routine, Exit routine
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LDC routine, STC routine, MRC routine, MCR routine,
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CDP routine, Read Reg routine, Write Reg routine) ;
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*/
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ARMul_CoProAttach (state, 4, NULL, NULL,
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ValLDC, ValSTC, ValMRC, ValMCR, ValCDP, NULL, NULL);
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ARMul_CoProAttach (state, 5, NULL, NULL,
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NULL, NULL, ValMRC, ValMCR, IntCDP, NULL, NULL);
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ARMul_CoProAttach (state, 15, MMUInit, NULL,
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NULL, NULL, MMUMRC, MMUMCR, NULL, MMURead, MMUWrite);
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/* No handlers below here */
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for (i = 0; i < 16; i++) /* Call all the initialisation routines */
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if (state->CPInit[i])
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(state->CPInit[i]) (state);
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return (TRUE);
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}
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/***************************************************************************\
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* Install co-processor finalisation routines in this routine *
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\***************************************************************************/
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void
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ARMul_CoProExit (ARMul_State * state)
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{
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register unsigned i;
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for (i = 0; i < 16; i++)
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if (state->CPExit[i])
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(state->CPExit[i]) (state);
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for (i = 0; i < 16; i++) /* Detach all handlers */
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ARMul_CoProDetach (state, i);
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}
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/***************************************************************************\
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* Routines to hook Co-processors into ARMulator *
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\***************************************************************************/
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void
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ARMul_CoProAttach (ARMul_State * state, unsigned number,
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ARMul_CPInits * init, ARMul_CPExits * exit,
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ARMul_LDCs * ldc, ARMul_STCs * stc,
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ARMul_MRCs * mrc, ARMul_MCRs * mcr, ARMul_CDPs * cdp,
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ARMul_CPReads * read, ARMul_CPWrites * write)
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{
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if (init != NULL)
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state->CPInit[number] = init;
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if (exit != NULL)
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state->CPExit[number] = exit;
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if (ldc != NULL)
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state->LDC[number] = ldc;
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if (stc != NULL)
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state->STC[number] = stc;
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if (mrc != NULL)
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state->MRC[number] = mrc;
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if (mcr != NULL)
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state->MCR[number] = mcr;
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if (cdp != NULL)
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state->CDP[number] = cdp;
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if (read != NULL)
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state->CPRead[number] = read;
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if (write != NULL)
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state->CPWrite[number] = write;
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}
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void
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ARMul_CoProDetach (ARMul_State * state, unsigned number)
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{
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ARMul_CoProAttach (state, number, NULL, NULL,
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NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R,
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NoCoPro3R, NULL, NULL);
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state->CPInit[number] = NULL;
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state->CPExit[number] = NULL;
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state->CPRead[number] = NULL;
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state->CPWrite[number] = NULL;
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}
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/***************************************************************************\
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* There is no CoPro around, so Undefined Instruction trap *
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\***************************************************************************/
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static unsigned
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NoCoPro3R (ARMul_State * state ATTRIBUTE_UNUSED,
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unsigned a ATTRIBUTE_UNUSED,
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ARMword b ATTRIBUTE_UNUSED)
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{
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return (ARMul_CANT);
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}
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static unsigned
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NoCoPro4R (
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ARMul_State * state ATTRIBUTE_UNUSED,
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unsigned a ATTRIBUTE_UNUSED,
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ARMword b ATTRIBUTE_UNUSED,
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ARMword c ATTRIBUTE_UNUSED)
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{
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return (ARMul_CANT);
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}
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static unsigned
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NoCoPro4W (
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ARMul_State * state ATTRIBUTE_UNUSED,
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unsigned a ATTRIBUTE_UNUSED,
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ARMword b ATTRIBUTE_UNUSED,
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ARMword * c ATTRIBUTE_UNUSED)
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{
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return (ARMul_CANT);
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}
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