f2db709f4f
Pull the model data (register addresses/sizes) out of the different model files and into the machs.h header. The models themselves don't care about where they're mapped, only the mach code does. This allows us to keep the model headers from being included in the mach code which can cause issues with model-specific names colliding. Such as when a newer device model is created, but with incompatible register names/layouts. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
103 lines
3.2 KiB
C
103 lines
3.2 KiB
C
/* Simulator for Analog Devices Blackfin processors.
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Copyright (C) 2005-2011 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef _BFIN_MACHS_H_
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#define _BFIN_MACHS_H_
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typedef enum model_type {
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#define P(n) MODEL_BF##n,
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#include "proc_list.def"
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#undef P
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MODEL_MAX
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} MODEL_TYPE;
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typedef enum mach_attr {
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MACH_BASE,
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MACH_BFIN,
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MACH_MAX
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} MACH_ATTR;
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#define CPU_MODEL_NUM(cpu) MODEL_NUM (CPU_MODEL (cpu))
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/* XXX: Some of this probably belongs in CPU_MODEL. */
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struct bfin_board_data {
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unsigned int sirev, sirev_valid;
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const char *hw_file;
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};
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void bfin_model_cpu_init (SIM_DESC, SIM_CPU *);
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bu32 bfin_model_get_chipid (SIM_DESC);
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bu32 bfin_model_get_dspid (SIM_DESC);
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enum {
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#define I(insn) BFIN_INSN_##insn,
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#include "insn_list.def"
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#undef I
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BFIN_INSN_MAX
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};
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#define BFIN_COREMMR_CEC_BASE 0xFFE02100
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#define BFIN_COREMMR_CEC_SIZE (4 * 5)
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#define BFIN_COREMMR_CTIMER_BASE 0xFFE03000
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#define BFIN_COREMMR_CTIMER_SIZE (4 * 4)
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#define BFIN_COREMMR_EVT_BASE 0xFFE02000
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#define BFIN_COREMMR_EVT_SIZE (4 * 16)
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#define BFIN_COREMMR_JTAG_BASE 0xFFE05000
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#define BFIN_COREMMR_JTAG_SIZE (4 * 3)
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#define BFIN_COREMMR_MMU_BASE 0xFFE00000
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#define BFIN_COREMMR_MMU_SIZE 0x2000
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#define BFIN_COREMMR_PFMON_BASE 0xFFE08000
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#define BFIN_COREMMR_PFMON_SIZE 0x108
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#define BFIN_COREMMR_TRACE_BASE 0xFFE06000
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#define BFIN_COREMMR_TRACE_SIZE (4 * 65)
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#define BFIN_COREMMR_WP_BASE 0xFFE07000
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#define BFIN_COREMMR_WP_SIZE 0x204
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#define BFIN_MMR_DMA_SIZE (4 * 16)
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#define BFIN_MMR_DMAC0_BASE 0xFFC00C00
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#define BFIN_MMR_DMAC1_BASE 0xFFC01C00
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#define BFIN_MMR_EBIU_AMC_SIZE (4 * 3)
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#define BF50X_MMR_EBIU_AMC_SIZE 0x28
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#define BF54X_MMR_EBIU_AMC_SIZE (4 * 7)
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#define BFIN_MMR_EBIU_DDRC_SIZE 0xb0
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#define BFIN_MMR_EBIU_SDC_SIZE (4 * 4)
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#define BFIN_MMR_EMAC_BASE 0xFFC03000
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#define BFIN_MMR_EMAC_SIZE 0x200
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#define BFIN_MMR_EPPI_SIZE 0x40
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#define BFIN_MMR_GPIO_SIZE (17 * 4)
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#define BFIN_MMR_GPTIMER_SIZE (4 * 4)
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#define BFIN_MMR_NFC_SIZE 0x50
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/* XXX: Not exactly true; it's two sets of 4 regs near each other:
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0xFFC03600 0x10 - Control
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0xFFC03680 0x10 - Data */
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#define BFIN_MMR_OTP_SIZE 0xa0
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#define BFIN_MMR_PLL_BASE 0xFFC00000
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#define BFIN_MMR_PLL_SIZE (4 * 6)
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#define BFIN_MMR_PPI_SIZE (4 * 5)
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#define BFIN_MMR_RTC_SIZE (4 * 6)
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#define BFIN_MMR_SIC_BASE 0xFFC00100
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#define BFIN_MMR_SIC_SIZE 0x100
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#define BFIN_MMR_SPI_SIZE (4 * 7)
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#define BFIN_MMR_TWI_SIZE 0x90
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#define BFIN_MMR_WDOG_SIZE (4 * 3)
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#define BFIN_MMR_UART_SIZE 0x30
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#define BFIN_MMR_UART2_SIZE 0x30
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#endif
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