136 lines
4.4 KiB
C
136 lines
4.4 KiB
C
/* TIc80 Simulator.
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Copyright (C) 1997 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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struct _sim_cpu {
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unsigned32 reg[32];
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unsigned64 acc[4];
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sim_cia cia;
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sim_cpu_base base;
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};
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#define GPR(N) ((CPU)->reg[N])
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#define ACC(N) ((CPU)->acc[N])
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#if defined(WITH_TRACE)
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extern char *tic80_trace_alu3 PARAMS ((int, unsigned32, unsigned32, unsigned32));
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extern char *tic80_trace_alu2 PARAMS ((int, unsigned32, unsigned32));
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extern char *tic80_trace_nop PARAMS ((int));
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extern char *tic80_trace_sink1 PARAMS ((int, unsigned32));
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extern char *tic80_trace_sink2 PARAMS ((int, unsigned32, unsigned32));
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extern char *tic80_trace_cond_br PARAMS ((int, int, unsigned32, unsigned32));
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extern char *tic80_trace_ucond_br PARAMS ((int, unsigned32));
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extern char *tic80_trace_ldst PARAMS ((int, int, int, int, unsigned32, unsigned32, unsigned32));
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#define TRACE_ALU3(indx, result, input1, input2) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "alu", \
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tic80_trace_alu3 (indx, result, input1, input2)); \
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} \
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} while (0)
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#define TRACE_ALU2(indx, result, input) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "alu", \
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tic80_trace_alu2 (indx, result, input)); \
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} \
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} while (0)
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#define TRACE_NOP(indx) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "nop", \
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tic80_trace_nop (indx)); \
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} \
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} while (0)
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#define TRACE_SINK1(indx, input) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "nop", \
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tic80_trace_sink1 (indx, input)); \
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} \
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} while (0)
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#define TRACE_SINK2(indx, input1, input2) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "nop", \
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tic80_trace_sink2 (indx, input1, input2)); \
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} \
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} while (0)
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#define TRACE_COND_BR(indx, jump_p, cond, target) \
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do { \
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if (TRACE_BRANCH_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "branch", \
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tic80_trace_cond_br (indx, jump_p, cond, target)); \
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} \
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} while (0)
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#define TRACE_UCOND_BR(indx, target) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "branch", \
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tic80_trace_ucond_br (indx, target)); \
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} \
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} while (0)
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#define TRACE_LD(indx, result, m, s, addr1, addr2) \
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do { \
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if (TRACE_MEMORY_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "memory", \
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tic80_trace_ldst (indx, 0, m, s, result, \
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addr1, addr2)); \
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} \
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} while (0)
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#define TRACE_ST(indx, value, m, s, addr1, addr2) \
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do { \
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if (TRACE_MEMORY_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "memory", \
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tic80_trace_ldst (indx, 1, m, s, value, \
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addr1, addr2)); \
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} \
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} while (0)
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#else
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#define TRACE_ALU3(indx, result, input1, input2)
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#define TRACE_ALU2(indx, result, input)
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#define TRACE_NOP(indx)
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#define TRACE_SINK1(indx, input)
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#define TRACE_SINK2(indx, input1, input2)
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#define TRACE_COND_BR(indx, jump_p, cond, target)
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#define TRACE_UCOND_BR(indx, target)
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#define TRACE_LD(indx, m, s, result, addr1, addr2)
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#define TRACE_ST(indx, m, s, value, addr1, addr2)
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#endif
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