7e8b059be6
gas/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386.c (BND_PREFIX): New. (struct _i386_insn): Add new field bnd_prefix. (add_bnd_prefix): New. (cpu_arch): Add MPX. (i386_operand_type): Add regbnd. (md_assemble): Handle BND prefixes. (parse_insn): Likewise. (output_branch): Likewise. (output_jump): Likewise. (build_modrm_byte): Handle regbnd. (OPTION_MADD_BND_PREFIX): New. (md_longopts): Add entry for 'madd-bnd-prefix'. (md_parse_option): Handle madd-bnd-prefix option. (md_show_usage): Add description for madd-bnd-prefix option. * doc/c-i386.texi: Document mpx/.mpx and -madd-bnd-prefix. gas/testsuite/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/i386/mpx-add-bnd-prefix.s: New. * gas/i386/mpx-add-bnd-prefix.d: New. * gas/i386/mpx-inval-1.l: New. * gas/i386/mpx-inval-1.s: New. * gas/i386/mpx.d: New. * gas/i386/mpx.s: New. * gas/i386/x86-64-mpx-add-bnd-prefix.d: New. * gas/i386/x86-64-mpx-add-bnd-prefix.s: New. * gas/i386/x86-64-mpx-addr32.d: New. * gas/i386/x86-64-mpx-addr32.s: New. * gas/i386/x86-64-mpx-inval-1.l: New. * gas/i386/x86-64-mpx-inval-1.s: New. * gas/i386/x86-64-mpx-inval-2.l: New. * gas/i386/x86-64-mpx-inval-2.s: New. * gas/i386/x86-64-mpx.d: New. * gas/i386/x86-64-mpx.s: New. * gas/i386/nops.d: Adjust to MPX changes. * gas/i386/nops.s: Likewise. * gas/i386/x86-64-nops.d: Likewise. * gas/i386/x86-64-nops.s: Likewise. * gas/i386/ilp32/x86-64-nops.d: Likewise. * gas/i386/i386.exp: Run new MPX tests. include/opcode/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386.h (BND_PREFIX_OPCODE): New. opcodes/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis.c (BND_Fixup): New. (Ebnd): New. (Ev_bnd): New. (Gbnd): New. (BND): New. (v_bnd_mode): New. (bnd_mode): New. (MOD enum): Add new entries. (PREFIX enum): Likewise. (dis tables): Replace XX with BND for near branch and call instructions. (prefix_table): Add new entries. (mod_table): Likewise. (names_bnd): New. (intel_names_bnd): New. (att_names_bnd): New. (BND_PREFIX): New. (prefix_name): Handle BND_PREFIX. (print_insn): Initialize names_bnd. (intel_operand_size): Handle new modes. (OP_E_register): Likewise. (OP_E_memory): Likewise. (OP_G): Likewise. * i386-gen.c (cpu_flag_init): Add CpuMPX. (cpu_flags): Add CpuMPX. (operand_type_init): Add RegBND. (opcode_modifiers): Add BNDPrefixOk. (operand_types): Add RegBND. * i386-init.h: Regenerate. * i386-opc.h (CpuMPX): New. (CpuUnused): Comment out. (i386_cpu_flags): Add cpumpx. (BNDPrefixOk): New. (i386_opcode_modifier): Add bndprefixok. (RegBND): New. (i386_operand_type): Add regbnd. * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets. Add MPX instructions and bnd prefix. * i386-reg.tbl: Add bnd0-bnd3 registers. * i386-tbl.h: Regenerate.
148 lines
5 KiB
C
148 lines
5 KiB
C
/* opcode/i386.h -- Intel 80386 opcode macros
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Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
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Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
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ix86 Unix assemblers, generate floating point instructions with
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reversed source and destination registers in certain cases.
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Unfortunately, gcc and possibly many other programs use this
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reversed syntax, so we're stuck with it.
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eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
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`fsub %st,%st(3)' results in st(3) = st - st(3), rather than
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the expected st(3) = st(3) - st
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This happens with all the non-commutative arithmetic floating point
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operations with two register operands, where the source register is
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%st, and destination register is %st(i).
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The affected opcode map is dceX, dcfX, deeX, defX. */
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#ifndef OPCODE_I386_H
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#define OPCODE_I386_H
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#ifndef SYSV386_COMPAT
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/* Set non-zero for broken, compatible instructions. Set to zero for
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non-broken opcodes at your peril. gcc generates SystemV/386
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compatible instructions. */
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#define SYSV386_COMPAT 1
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#endif
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#ifndef OLDGCC_COMPAT
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/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
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generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
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reversed. */
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#define OLDGCC_COMPAT SYSV386_COMPAT
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#endif
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#define MOV_AX_DISP32 0xa0
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#define POP_SEG_SHORT 0x07
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#define JUMP_PC_RELATIVE 0xeb
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#define INT_OPCODE 0xcd
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#define INT3_OPCODE 0xcc
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/* The opcode for the fwait instruction, which disassembler treats as a
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prefix when it can. */
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#define FWAIT_OPCODE 0x9b
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/* Instruction prefixes.
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NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as
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part of the opcode. Other prefixes may still appear between them
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and the 0x0f part of the opcode. */
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#define ADDR_PREFIX_OPCODE 0x67
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#define DATA_PREFIX_OPCODE 0x66
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#define LOCK_PREFIX_OPCODE 0xf0
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#define CS_PREFIX_OPCODE 0x2e
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#define DS_PREFIX_OPCODE 0x3e
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#define ES_PREFIX_OPCODE 0x26
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#define FS_PREFIX_OPCODE 0x64
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#define GS_PREFIX_OPCODE 0x65
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#define SS_PREFIX_OPCODE 0x36
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#define REPNE_PREFIX_OPCODE 0xf2
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#define REPE_PREFIX_OPCODE 0xf3
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#define XACQUIRE_PREFIX_OPCODE 0xf2
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#define XRELEASE_PREFIX_OPCODE 0xf3
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#define BND_PREFIX_OPCODE 0xf2
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#define TWO_BYTE_OPCODE_ESCAPE 0x0f
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#define NOP_OPCODE (char) 0x90
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/* register numbers */
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#define EAX_REG_NUM 0
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#define ECX_REG_NUM 1
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#define EDX_REG_NUM 2
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#define EBX_REG_NUM 3
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#define ESP_REG_NUM 4
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#define EBP_REG_NUM 5
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#define ESI_REG_NUM 6
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#define EDI_REG_NUM 7
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/* modrm_byte.regmem for twobyte escape */
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#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
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/* index_base_byte.index for no index register addressing */
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#define NO_INDEX_REGISTER ESP_REG_NUM
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/* index_base_byte.base for no base register addressing */
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#define NO_BASE_REGISTER EBP_REG_NUM
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#define NO_BASE_REGISTER_16 6
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/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
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#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
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#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
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/* Extract fields from the mod/rm byte. */
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#define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3)
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#define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7)
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#define MODRM_RM_FIELD(modrm) (((modrm) >> 0) & 7)
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/* Extract fields from the sib byte. */
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#define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3)
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#define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7)
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#define SIB_BASE_FIELD(sib) (((sib) >> 0) & 7)
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/* x86-64 extension prefix. */
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#define REX_OPCODE 0x40
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/* Non-zero if OPCODE is the rex prefix. */
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#define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE)
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/* Indicates 64 bit operand size. */
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#define REX_W 8
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/* High extension to reg field of modrm byte. */
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#define REX_R 4
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/* High extension to SIB index field. */
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#define REX_X 2
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/* High extension to base field of modrm or SIB, or reg field of opcode. */
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#define REX_B 1
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/* max operands per insn */
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#define MAX_OPERANDS 5
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/* max immediates per insn (lcall, ljmp, insertq, extrq) */
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#define MAX_IMMEDIATE_OPERANDS 2
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/* max memory refs per insn (string ops) */
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#define MAX_MEMORY_OPERANDS 2
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/* max size of insn mnemonics. */
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#define MAX_MNEM_SIZE 20
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/* max size of register name in insn mnemonics. */
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#define MAX_REG_NAME_SIZE 8
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#endif /* OPCODE_I386_H */
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