e3659cbf49
Wed Jul 17 14:39:05 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* configure: (bfd_d10v_arch) Add new case.
* configure.in: (bfd_d10v_arch) Add new case.
* d10v-dis.c: New file.
* d10v-opc.c: New file.
* disassemble.c (disassembler) Add entry for d10v.
end-sanitize-d10v
241 lines
14 KiB
C
241 lines
14 KiB
C
/* d10v-opc.c -- D10V opcode list
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Copyright 1996 Free Software Foundation, Inc.
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Written by Martin Hunt, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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2, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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#include "ansidecl.h"
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#include "opcode/d10v.h"
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const struct d10v_operand d10v_operands[] =
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{
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#define UNUSED (0)
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{ 0, 0, 0 },
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#define RSRC (UNUSED + 1)
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{ 4, 1, OPERAND_REG },
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#define RDST (RSRC + 1)
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{ 4, 5, OPERAND_DEST|OPERAND_REG },
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#define ASRC (RDST + 1)
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{ 1, 4, OPERAND_ACC|OPERAND_REG },
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#define ADST (ASRC + 1)
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{ 1, 8, OPERAND_DEST|OPERAND_ACC|OPERAND_REG },
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#define RSRCE (ADST + 1)
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{ 4, 1, OPERAND_EVEN|OPERAND_REG },
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#define RDSTE (RSRCE + 1)
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{ 4, 5, OPERAND_EVEN|OPERAND_DEST|OPERAND_REG },
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#define NUM16 (RDSTE + 1)
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{ 16, 0, OPERAND_NUM },
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#define NUM3 (NUM16 + 1)
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{ 3, 1, OPERAND_NUM },
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#define NUM4 (NUM3 + 1)
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{ 4, 1, OPERAND_NUM },
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#define NUM8 (NUM4 + 1) /* only used in REPI */
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{ 8, 16, OPERAND_NUM },
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#define ANUM16 (NUM8 + 1)
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{ 16, 0, OPERAND_ADDR },
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#define ANUM8 (ANUM16 + 1)
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{ 8, 0, OPERAND_ADDR },
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#define ASRC2 (ANUM8 + 1)
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{ 1, 8, OPERAND_ACC|OPERAND_REG },
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#define RSRC2 (ASRC2 + 1)
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{ 4, 5, OPERAND_REG },
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#define RSRC2E (RSRC2 + 1)
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{ 4, 5, OPERAND_REG|OPERAND_EVEN },
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#define ASRC0 (RSRC2E + 1)
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{ 1, 0, OPERAND_ACC|OPERAND_REG },
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#define ADST0 (ASRC0 + 1)
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{ 1, 0, OPERAND_ACC|OPERAND_REG|OPERAND_DEST },
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#define FSRC (ADST0 + 1)
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{ 2, 1, OPERAND_REG | OPERAND_FLAG },
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#define FDST (FSRC + 1)
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{ 1, 5, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST},
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#define ATSIGN (FDST + 1)
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{ 0, 0, OPERAND_ATSIGN},
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#define ATPAR (ATSIGN + 1) /* "@(" */
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{ 0, 0, OPERAND_ATPAR},
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#define PLUS (ATPAR + 1) /* postincrement */
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{ 0, 0, OPERAND_PLUS},
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#define MINUS (PLUS + 1) /* postdecrement */
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{ 0, 0, OPERAND_MINUS},
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#define ATMINUS (MINUS + 1) /* predecrement */
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{ 0, 0, OPERAND_ATMINUS},
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#define CSRC (ATMINUS + 1) /* control register */
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{ 4, 1, OPERAND_REG|OPERAND_CONTROL},
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#define CDST (CSRC + 1) /* control register */
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{ 4, 5, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST},
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};
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const struct d10v_opcode d10v_opcodes[] = {
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{ "abs", SHORT_2, 1, EITHER, PAR, 0x4607, 0x7e1f, { RDST } },
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{ "abs", SHORT_2, 1, IU, PAR, 0x5607, 0x7eff, { ADST } },
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{ "add", SHORT_2, 1, EITHER, PAR, 0x0200, 0x7e01, { RDST, RSRC } },
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{ "add", SHORT_2, 1, IU, PAR, 0x1201, 0x7ee3, { ADST, RSRCE } },
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{ "add", SHORT_2, 1, IU, PAR, 0x1203, 0x7eef, { ADST, ASRC } },
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{ "add2w", SHORT_2, 2, IU, PAR, 0x1200, 0x7e23, { RDSTE, RSRCE } },
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{ "add3", LONG_L, 1, MU, SEQ, 0x1000000, 0x3f000000, { RDST, RSRC, NUM16 } },
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{ "addac3", LONG_R, 1, IU, SEQ, 0x17000200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
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{ "addac3", LONG_R, 1, IU, SEQ, 0x17000202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
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{ "addac3s", LONG_R, 1, IU, SEQ, 0x17001200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
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{ "addac3s", LONG_R, 1, IU, SEQ, 0x17001202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
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{ "addi", SHORT_2, 1, EITHER, PAR, 0x201, 0x7e01, { RDST, NUM4 } },
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{ "and", SHORT_2, 1, EITHER, PAR, 0xc00, 0x7e01, { RDST, RSRC } },
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{ "and3", LONG_L, 1, MU, SEQ, 0x6000000, 0x3f000000, { RDST, RSRC, NUM16 } },
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{ "bclri", SHORT_2, 1, IU, PAR, 0xc01, 0x7e01, { RDST, NUM4 } },
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{ "bl", LONG_B, 3, MU, BRANCH_LINK, 0x24800000, 0x3fff8000, { ANUM16 } },
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{ "bl.s", SHORT_B, 3, MU, BRANCH_LINK, 0x4900, 0x7f00, { ANUM8 } },
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{ "bnoti", SHORT_2, 1, IU, PAR, 0xa01, 0x7e01, { RDST, NUM4 } },
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{ "bra", LONG_B, 3, MU, SEQ, 0x24000000, 0x3fff0000, { ANUM16 } },
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{ "bra.s", SHORT_B, 3, MU, PAR, 0x4800, 0x7f00, { ANUM8 } },
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{ "brf0f", LONG_B, 3, MU, SEQ, 0x25000000, 0x3fff0000, { ANUM16 } },
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{ "brf0f.s", SHORT_B, 3, MU, PAR, 0x4a00, 0x7f00, { ANUM8 } },
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{ "brf0t", LONG_B, 3, MU, SEQ, 0x25800000, 0x3fff0000, { ANUM16 } },
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{ "brf0t.s", SHORT_B, 3, MU, PAR, 0x4b00, 0x7f00, { ANUM8 } },
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{ "bseti", SHORT_2, 1, IU, PAR, 0x801, 0x7e01, { RDST, NUM4 } },
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{ "btsti", SHORT_2, 1, IU, PAR, 0xe01, 0x7e01, { RDST, NUM4 } },
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{ "clrac", SHORT_2, 1, IU, PAR, 0x5601, 0x7eff, { ADST } },
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{ "cmp", SHORT_2, 1, EITHER, PAR, 0x600, 0x7e01, { RSRC2, RSRC } },
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{ "cmp", SHORT_2, 1, IU, PAR, 0x1603, 0x7eef, { ASRC2, ASRC } },
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{ "cmpeq", SHORT_2, 1, EITHER, PAR, 0x400, 0x7e01, { RSRC2, RSRC } },
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{ "cmpeq", SHORT_2, 1, IU, PAR, 0x1403, 0x7eef, { ASRC2, ASRC } },
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{ "cmpeqi", SHORT_2, 1, EITHER, PAR, 0x401, 0x7e01, { RSRC2, NUM4 } },
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{ "cmpeqi", LONG_L, 1, MU, SEQ, 0x2000000, 0x3f0f0000, { RSRC2, NUM16 } },
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{ "cmpi", SHORT_2, 1, EITHER, PAR, 0x601, 0x7e01, { RSRC2, NUM4 } },
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{ "cmpi", LONG_L, 1, MU, SEQ, 0x3000000, 0x3f0f0000, { RSRC2, NUM16 } },
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{ "cmpu", SHORT_2, 1, EITHER, PAR, 0x4600, 0x7e01, { RSRC2, RSRC } },
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{ "cmpui", LONG_L, 1, MU, SEQ, 0x23000000, 0x3f0f0000, { RSRC2, NUM16 } },
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{ "cpfg", SHORT_2, 1, MU, PAR, 0x4e09, 0x7fd9, { FDST, FSRC } },
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{ "dbt", SHORT_2, 5, MU, PAR, 0x5f20, 0x7fff, { 0 } },
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{ "exef0f", SHORT_2, 1, EITHER, PAR, 0x4e04, 0x7fff, { 0 } },
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{ "exef0t", SHORT_2, 1, EITHER, PAR, 0x4e24, 0x7fff, { 0 } },
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{ "exef1f", SHORT_2, 1, EITHER, PAR, 0x4e40, 0x7fff, { 0 } },
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{ "exef1t", SHORT_2, 1, EITHER, PAR, 0x4e42, 0x7fff, { 0 } },
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{ "exefaf", SHORT_2, 1, EITHER, PAR, 0x4e00, 0x7fff, { 0 } },
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{ "exefat", SHORT_2, 1, EITHER, PAR, 0x4e02, 0x7fff, { 0 } },
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{ "exetaf", SHORT_2, 1, EITHER, PAR, 0x4e20, 0x7fff, { 0 } },
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{ "exetat", SHORT_2, 1, EITHER, PAR, 0x4e22, 0x7fff, { 0 } },
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{ "exp", LONG_R, 1, IU, SEQ, 0x15002a00, 0x3ffffe03, { RDST, RSRCE } },
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{ "exp", LONG_R, 1, IU, SEQ, 0x15002a02, 0x3ffffe0f, { RDST, ASRC } },
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{ "jl", SHORT_2, 3, MU, BRANCH_LINK, 0x4d00, 0x7fe1, { RSRC } },
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{ "jmp", SHORT_2, 3, MU, PAR, 0x4c00, 0x7fe1, { RSRC } },
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{ "ld", LONG_L, 1, MU, SEQ, 0x30000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } },
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{ "ld", SHORT_2, 1, MU, PAR, 0x6401, 0x7e01, { RDST, ATSIGN, RSRC, MINUS } },
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{ "ld", SHORT_2, 1, MU, PAR, 0x6001, 0x7e01, { RDST, ATSIGN, RSRC, PLUS } },
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{ "ld", SHORT_2, 1, MU, PAR, 0x6000, 0x7e01, { RDST, ATSIGN, RSRC } },
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{ "ld2w", LONG_L, 1, MU, SEQ, 0x31000000, 0x3f100000, { RDSTE, ATPAR, NUM16, RSRC } },
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{ "ld2w", SHORT_2, 1, MU, PAR, 0x6601, 0x7e21, { RDSTE, ATSIGN, RSRC, MINUS } },
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{ "ld2w", SHORT_2, 1, MU, PAR, 0x6201, 0x7e21, { RDSTE, ATSIGN, RSRC, PLUS } },
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{ "ld2w", SHORT_2, 1, MU, PAR, 0x6200, 0x7e21, { RDSTE, ATSIGN, RSRC } },
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{ "ldb", LONG_L, 1, MU, SEQ, 0x38000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } },
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{ "ldb", SHORT_2, 1, MU, PAR, 0x7000, 0x7e01, { RDST, ATSIGN, RSRC } },
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{ "ldi", LONG_L, 1, MU, SEQ, 0x20000000, 0x3f0f0000, { RDST, NUM16 } },
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{ "ldi", SHORT_2, 1, EITHER, PAR,0x4001, 0x7e01 , { RDST, NUM4 } },
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{ "ldub", LONG_L, 1, MU, SEQ, 0x39000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } },
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{ "ldub", SHORT_2, 1, MU, PAR, 0x7200, 0x7e01, { RDST, ATSIGN, RSRC } },
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{ "mac", SHORT_2, 1, IU, PAR, 0x2a00, 0x7e00, { ADST0, RSRC2, RSRC } },
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{ "macsu", SHORT_2, 1, IU, PAR, 0x1a00, 0x7e00, { ADST0, RSRC2, RSRC } },
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{ "macu", SHORT_2, 1, IU, PAR, 0x3a00, 0x7e00, { ADST0, RSRC2, RSRC } },
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{ "max", SHORT_2, 1, IU, PAR, 0x2600, 0x7e01, { RDST, RSRC } },
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{ "max", SHORT_2, 1, IU, PAR, 0x3600, 0x7ee3, { ADST, RSRCE } },
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{ "max", SHORT_2, 1, IU, PAR, 0x3602, 0x7eef, { ADST, ASRC } },
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{ "min", SHORT_2, 1, IU, PAR, 0x2601, 0x7e01 , { RDST, RSRC } },
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{ "min", SHORT_2, 1, IU, PAR, 0x3601, 0x7ee3 , { ADST, RSRCE } },
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{ "min", SHORT_2, 1, IU, PAR, 0x3603, 0x7eef, { ADST, ASRC } },
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{ "msb", SHORT_2, 1, IU, PAR, 0x2800, 0x7e00, { ADST0, RSRC2, RSRC } },
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{ "msbsu", SHORT_2, 1, IU, PAR, 0x1800, 0x7e00, { ADST0, RSRC2, RSRC } },
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{ "msbu", SHORT_2, 1, IU, PAR, 0x3800, 0x7e00, { ADST0, RSRC2, RSRC } },
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{ "mul", SHORT_2, 1, IU, PAR, 0x2e00, 0x7e01 , { RDST, RSRC } },
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{ "mulx", SHORT_2, 1, IU, PAR, 0x2c00, 0x7e00, { ADST0, RSRC2, RSRC } },
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{ "mulxsu", SHORT_2, 1, IU, PAR, 0x1c00, 0x7e00, { ADST0, RSRC2, RSRC } },
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{ "mulxu", SHORT_2, 1, IU, PAR, 0x3c00, 0x7e00, { ADST0, RSRC2, RSRC } },
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{ "mv", SHORT_2, 1, IU, PAR, 0x4000, 0x7e01, { RDST, RSRC } },
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{ "mv2w", SHORT_2, 1, IU, PAR, 0x5000, 0x7e23, { RDSTE, RSRCE } },
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{ "mv2wfac", SHORT_2, 1, IU, PAR, 0x3e00, 0x7e2f, { RDSTE, ASRC } },
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{ "mv2wtac", SHORT_2, 1, IU, PAR, 0x3e01, 0x7ee3, { RSRCE, ADST } },
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{ "mvac", SHORT_2, 1, IU, PAR, 0x3e03, 0x7eef, { ADST, ASRC } },
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{ "mvb", SHORT_2, 1, IU, PAR, 0x5400, 0x7e01, { RDST, RSRC } },
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{ "mvf0f", SHORT_2, 1, EITHER, PAR, 0x4400, 0x7e01, { RDST, RSRC } },
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{ "mvf0t", SHORT_2, 1, EITHER, PAR, 0x4401, 0x7e01, { RDST, RSRC } },
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{ "mvfacg", SHORT_2, 1, IU, PAR, 0x1e04, 0x7e0f, { RDST, ASRC } },
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{ "mvfachi", SHORT_2, 1, IU, PAR, 0x1e00, 0x7e0f, { RDST, ASRC } },
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{ "mvfaclo", SHORT_2, 1, IU, PAR, 0x1e02, 0x7e0f, { RDST, ASRC } },
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{ "mvfc", SHORT_2, 1, MU, PAR, 0x5200, 0x7e01, { RDST, CSRC } },
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{ "mvtacg", SHORT_2, 1, IU, PAR, 0x1e41, 0x7ee1, { RSRC, ADST } },
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{ "mvtachi", SHORT_2, 1, IU, PAR, 0x1e01, 0x7ee1, { RSRC, ADST } },
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{ "mvtaclo", SHORT_2, 1, IU, PAR, 0x1e21, 0x7ee1, { RSRC, ADST } },
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{ "mvtc", SHORT_2, 1, MU, PAR, 0x5600, 0x7e01, { RSRC, CDST } },
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{ "mvub", SHORT_2, 1, IU, PAR, 0x5401, 0x7e01, { RDST, RSRC } },
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{ "neg", SHORT_2, 1, EITHER, PAR, 0x4605, 0x7e1f, { RDST } },
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{ "neg", SHORT_2, 1, IU, PAR, 0x5605, 0x7eff, { ADST } },
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{ "nop", SHORT_2, 1, EITHER, PAR, 0x5e00, 0x7fff, { 0 } },
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{ "not", SHORT_2, 1, EITHER, PAR, 0x4603, 0x7e1f, { RDST } },
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{ "or", SHORT_2, 1, EITHER, PAR, 0x800, 0x7e01, { RDST, RSRC } },
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{ "or3", LONG_L, 1, MU, SEQ, 0x4000000, 0x3f000000, { RDST, RSRC, NUM16 } },
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{ "rac", SHORT_2, 1, IU, PAR, 0x5201, 0x7e21, { RDSTE, ASRC, NUM3 } },
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{ "rachi", SHORT_2, 1, IU, PAR, 0x4201, 0x7e01, { RDST, ASRC, NUM3 } },
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{ "rep", LONG_L, 2, MU, SEQ, 0x27000000, 0x3ff00000, { RSRC, ANUM16 } },
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{ "repi", LONG_L, 2, MU, SEQ, 0x2f000000, 0x3f000000, { NUM8, ANUM16 } },
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{ "rtd", SHORT_2, 3, MU, PAR, 0x5f60, 0x7fff, { 0 } },
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{ "rte", SHORT_2, 3, MU, PAR, 0x5f40, 0x7ff, { 0 } },
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{ "sadd", SHORT_2, 1, IU, PAR, 0x1223, 0x7eef, { ADST, ASRC } },
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{ "setf0f", SHORT_2, 1, MU, PAR, 0x4611, 0x7e1f, { RDST } },
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{ "setf0t", SHORT_2, 1, MU, PAR, 0x4613, 0x7e1f, { RDST } },
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{ "sleep", SHORT_2, 1, MU, PAR, 0x5fc0, 0x7fff, { 0 } },
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{ "sll", SHORT_2, 1, IU, PAR, 0x2200, 0x7e01, { RDST, RSRC } },
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{ "sll", SHORT_2, 1, IU, PAR, 0x3200, 0x7ee1, { ADST, RSRC } },
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{ "slli", SHORT_2, 1, IU, PAR, 0x2201, 0x7e01, { RDST, NUM4 } },
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{ "slli", SHORT_2, 1, IU, PAR, 0x3201, 0x7ee1, { ADST, NUM4 } },
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{ "slx", SHORT_2, 1, IU, PAR, 0x460b, 0x7e1f, { RDST } },
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{ "sra", SHORT_2, 1, IU, PAR, 0x2400, 0x7e01, { RDST, RSRC } },
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{ "sra", SHORT_2, 1, IU, PAR, 0x3400, 0x7ee1, { ADST, RSRC } },
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{ "srai", SHORT_2, 1, IU, PAR, 0x2401, 0x7e01, { RDST, NUM4 } },
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{ "srai", SHORT_2, 1, IU, PAR, 0x3401, 0x7ee1, { ADST, NUM4 } },
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{ "srl", SHORT_2, 1, IU, PAR, 0x2000, 0x7e01, { RDST, RSRC } },
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{ "srl", SHORT_2, 1, IU, PAR, 0x3000, 0x7ee1, { ADST, RSRC } },
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{ "srli", SHORT_2, 1, IU, PAR, 0x2001, 0x7e01, { RDST, NUM4 } },
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{ "srli", SHORT_2, 1, IU, PAR, 0x3001, 0x7ee1, { ADST, NUM4 } },
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{ "srx", SHORT_2, 1, IU, PAR, 0x4609, 0x7e1f, { RDST } },
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{ "st", LONG_L, 1, MU, SEQ, 0x34000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } },
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{ "st", SHORT_2, 1, MU, PAR, 0x6800, 0x7e01, { RSRC2, ATSIGN, RSRC } },
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{ "st", SHORT_2, 1, MU, PAR, 0x6c1f, 0x7e1f, { RSRC2, ATMINUS, RSRC } },
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{ "st", SHORT_2, 1, MU, PAR, 0x6801, 0x7e01, { RSRC2, ATSIGN, RSRC, PLUS } },
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{ "st", SHORT_2, 1, MU, PAR, 0x6c01, 0x7e01, { RSRC2, ATSIGN, RSRC, MINUS } },
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{ "st2w", LONG_L, 1, MU, SEQ, 0x35000000, 0x3f100000, { RSRC2E, ATPAR, NUM16, RSRC } },
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{ "st2w", SHORT_2, 1, MU, PAR, 0x6a00, 0x7e21, { RSRC2E, ATSIGN, RSRC } },
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{ "st2w", SHORT_2, 1, MU, PAR, 0x6e1f, 0x7e3f, { RSRC2E, ATMINUS, RSRC } },
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{ "st2w", SHORT_2, 1, MU, PAR, 0x6a01, 0x7e21, { RSRC2E, ATSIGN, RSRC, PLUS } },
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{ "st2w", SHORT_2, 1, MU, PAR, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC, MINUS } },
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{ "stb", LONG_L, 1, MU, SEQ, 0x3c000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } },
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{ "stb", SHORT_2, 1, MU, PAR, 0x7800, 0x7e01, { RSRC2, ATSIGN, RSRC } },
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/* { "stop", SHORT_2, 1, MU, PAR, 0x5fe0, 0x7fff, { 0 } }, */
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{ "sub", SHORT_2, 1, EITHER, PAR, 0x0, 0x7e01, { RDST, RSRC } },
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{ "sub2w", SHORT_2, 1, IU, PAR, 0x1000, 0x7e23, { RDSTE, RSRCE } },
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{ "subac3", LONG_R, 1, IU, SEQ, 0x17000000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
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{ "subac3", LONG_R, 1, IU, SEQ, 0x17000002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
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{ "subac3s", LONG_R, 1, IU, SEQ, 0x17001000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
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{ "subac3s", LONG_R, 1, IU, SEQ, 0x17001002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
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{ "subi", SHORT_2, 1, EITHER, PAR, 0x1, 0x7e01, { RDST, NUM4 } },
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{ "trap", SHORT_2, 5, MU, PAR, 0x5f00, 0x7fe1, { NUM4 } },
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{ "tst0i", LONG_L, 1, MU, SEQ, 0x7000000, 0x3f0f0000, { RSRC2, NUM16 } },
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{ "tst1i", LONG_L, 1, MU, SEQ, 0xf000000, 0x3f0f0000, { RSRC2, NUM16 } },
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{ "wait", SHORT_2, 1, MU, PAR, 0x5f80, 0x7fff, { 0 } },
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{ "xor", SHORT_2, 1, EITHER, PAR, 0xa00, 0x7e01, { RDST, RSRC } },
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{ "xor3", LONG_L, 1, MU, SEQ, 0x5000000, 0x3f000000, { RDST, RSRC, NUM16 } },
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|
{ 0, 0, 0, 0, 0, 0, 0, { 0 } },
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};
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