a27e685fa0
This change, with prerequisite 0e5fabeb, provides a toc base aligned
to 256 bytes rather than 8 bytes. This is necessary for a minor gcc
optimisation, allowing use of d-form instructions to correctly access
toc-relative items larger than 8 bytes.
bfd/
* elf64-ppc.c (TOC_BASE_ALIGN): Define.
(ppc64_elf_next_toc_section): Align multi-got toc base.
(ppc64_elf_set_toc): Likewise initial toc base and .TOC. symbol.
ld/
* emulparams/elf64ppc.sh (GOT): Align.
ld/testsuite/
* ld-powerpc/ambiguousv1b.d: Update for aligned .got.
* ld-powerpc/defsym.d: Likewise.
* ld-powerpc/elfv2-2exe.d: Likewise.
* ld-powerpc/elfv2exe.d: Likewise.
* ld-powerpc/elfv2so.d: Likewise.
* ld-powerpc/relbrlt.d: Likewise.
* ld-powerpc/tls.g: Likewise.
* ld-powerpc/tlsexe.d: Likewise.
* ld-powerpc/tlsexe.g: Likewise.
* ld-powerpc/tlsexe.r: Likewise.
* ld-powerpc/tlsexetoc.d: Likewise.
* ld-powerpc/tlsexetoc.g: Likewise.
* ld-powerpc/tlsexetoc.r: Likewise.
* ld-powerpc/tlsso.d: Likewise.
* ld-powerpc/tlsso.g: Likewise.
* ld-powerpc/tlsso.r: Likewise.
* ld-powerpc/tlstoc.g: Likewise.
* ld-powerpc/tlstocso.d: Likewise.
* ld-powerpc/tlstocso.g: Likewise.
* ld-powerpc/tlstocso.r: Likewise.
* ld-powerpc/tocopt.d: Likewise.
* ld-powerpc/tocopt2.d: Likewise.
* ld-powerpc/tocopt3.d: Likewise.
* ld-powerpc/tocopt4.d: Likewise.
* ld-powerpc/tocopt5.d: Likewise.
60 lines
1.8 KiB
Makefile
60 lines
1.8 KiB
Makefile
#source: relbrlt.s
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#as: -a64
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#ld: -melf64ppc --no-ld-generated-unwind-info --emit-relocs
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#objdump: -Dr
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.*
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Disassembly of section \.text:
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0*100000c0 <_start>:
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[0-9a-f ]*: (49 bf 00 2d|2d 00 bf 49) bl .*
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[0-9a-f ]*: R_PPC64_REL24 \.text\+0x37e003c
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[0-9a-f ]*: (60 00 00 00|00 00 00 60) nop
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[0-9a-f ]*: (49 bf 00 19|19 00 bf 49) bl .*
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[0-9a-f ]*: R_PPC64_REL24 \.text\+0x3bf0020
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[0-9a-f ]*: (60 00 00 00|00 00 00 60) nop
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[0-9a-f ]*: (49 bf 00 21|21 00 bf 49) bl .*
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[0-9a-f ]*: R_PPC64_REL24 \.text\+0x57e0024
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[0-9a-f ]*: (60 00 00 00|00 00 00 60) nop
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[0-9a-f ]*: 00 00 00 00 \.long 0x0
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[0-9a-f ]*: (4b ff ff e4|e4 ff ff 4b) b .* <_start>
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\.\.\.
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[0-9a-f ]*<.*plt_branch.*>:
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[0-9a-f ]*: (e9 82 80 e8|e8 80 82 e9) ld r12,-32536\(r2\)
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[0-9a-f ]*: R_PPC64_TOC16_DS \*ABS\*\+0x157f00e8
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[0-9a-f ]*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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[0-9a-f ]*: (4e 80 04 20|20 04 80 4e) bctr
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[0-9a-f ]*<.*long_branch.*>:
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[0-9a-f ]*: (49 bf 00 10|10 00 bf 49) b .* <far>
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[0-9a-f ]*: R_PPC64_REL24 \*ABS\*\+0x137e00fc
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[0-9a-f ]*<.*plt_branch.*>:
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[0-9a-f ]*: (e9 82 80 f0|f0 80 82 e9) ld r12,-32528\(r2\)
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[0-9a-f ]*: R_PPC64_TOC16_DS \*ABS\*\+0x157f00f0
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[0-9a-f ]*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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[0-9a-f ]*: (4e 80 04 20|20 04 80 4e) bctr
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\.\.\.
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0*137e00fc <far>:
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[0-9a-f ]*: (4e 80 00 20|20 00 80 4e) blr
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\.\.\.
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0*13bf00e0 <far2far>:
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[0-9a-f ]*: (4e 80 00 20|20 00 80 4e) blr
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\.\.\.
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0*157e00e4 <huge>:
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[0-9a-f ]*: (4e 80 00 20|20 00 80 4e) blr
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Disassembly of section \.branch_lt:
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0*157f00e8 .*:
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[0-9a-f ]*: (00 00 00 00|e0 00 bf 13) .*
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[0-9a-f ]*: R_PPC64_RELATIVE \*ABS\*\+0x13bf00e0
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[0-9a-f ]*: (13 bf 00 e0|00 00 00 00) .*
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[0-9a-f ]*: (00 00 00 00|e4 00 7e 15) .*
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[0-9a-f ]*: R_PPC64_RELATIVE \*ABS\*\+0x157e00e4
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[0-9a-f ]*: (15 7e 00 e4|00 00 00 00) .*
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