d908c8af5a
* arm-dis.c: Add necessary casts for printing integer values. Use %s when printing string values. * hppa-dis.c: Likewise. * m68k-dis.c: Likewise. * microblaze-dis.c: Likewise. * mips-dis.c: Likewise. * ppc-dis.c: Likewise. * sparc-dis.c: Likewise. * dis-asm.h (fprintf_ftype): Add ATTRIBUTE_FPTR_PRINTF_2.
723 lines
21 KiB
C
723 lines
21 KiB
C
/* ppc-dis.c -- Disassemble PowerPC instructions
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Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
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2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
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Written by Ian Lance Taylor, Cygnus Support
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "dis-asm.h"
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#include "elf-bfd.h"
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#include "elf/ppc.h"
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#include "opintl.h"
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#include "opcode/ppc.h"
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/* This file provides several disassembler functions, all of which use
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the disassembler interface defined in dis-asm.h. Several functions
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are provided because this file handles disassembly for the PowerPC
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in both big and little endian mode and also for the POWER (RS/6000)
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chip. */
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static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
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ppc_cpu_t);
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struct dis_private
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{
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/* Stash the result of parsing disassembler_options here. */
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ppc_cpu_t dialect;
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} private;
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#define POWERPC_DIALECT(INFO) \
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(((struct dis_private *) ((INFO)->private_data))->dialect)
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struct ppc_mopt {
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const char *opt;
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ppc_cpu_t cpu;
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ppc_cpu_t sticky;
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};
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struct ppc_mopt ppc_opts[] = {
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{ "403", (PPC_OPCODE_PPC | PPC_OPCODE_403),
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0 },
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{ "405", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405),
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0 },
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{ "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
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| PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
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0 },
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{ "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
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| PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
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0 },
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{ "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
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| PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
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0 },
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{ "601", (PPC_OPCODE_PPC | PPC_OPCODE_601),
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0 },
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{ "603", (PPC_OPCODE_PPC),
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0 },
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{ "604", (PPC_OPCODE_PPC),
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0 },
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{ "620", (PPC_OPCODE_PPC | PPC_OPCODE_64),
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0 },
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{ "7400", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
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0 },
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{ "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
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0 },
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{ "7450", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
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0 },
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{ "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
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0 },
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{ "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS)
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, 0 },
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{ "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
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| PPC_OPCODE_A2),
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0 },
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{ "altivec", (PPC_OPCODE_PPC),
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PPC_OPCODE_ALTIVEC },
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{ "any", 0,
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PPC_OPCODE_ANY },
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{ "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
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0 },
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{ "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
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0 },
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{ "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
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0 },
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{ "com", (PPC_OPCODE_COMMON),
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0 },
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{ "e300", (PPC_OPCODE_PPC | PPC_OPCODE_E300),
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0 },
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{ "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
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| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500),
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0 },
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{ "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500MC),
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0 },
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{ "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
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| PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
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0 },
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{ "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_POWER7),
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0 },
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{ "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
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| PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
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0 },
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{ "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
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| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500),
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0 },
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{ "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
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0 },
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{ "power4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
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0 },
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{ "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5),
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0 },
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{ "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
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0 },
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{ "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
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0 },
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{ "ppc", (PPC_OPCODE_PPC),
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0 },
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{ "ppc32", (PPC_OPCODE_PPC),
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0 },
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{ "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_64),
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0 },
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{ "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE),
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0 },
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{ "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
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0 },
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{ "pwr", (PPC_OPCODE_POWER),
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0 },
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{ "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
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0 },
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{ "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
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0 },
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{ "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5),
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0 },
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{ "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5),
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0 },
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{ "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
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0 },
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{ "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
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0 },
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{ "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
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0 },
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{ "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
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PPC_OPCODE_SPE },
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{ "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
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| PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
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0 },
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{ "vle", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE),
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PPC_OPCODE_VLE },
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{ "vsx", (PPC_OPCODE_PPC),
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PPC_OPCODE_VSX },
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};
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/* Switch between Booke and VLE dialects for interlinked dumps. */
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static ppc_cpu_t
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get_powerpc_dialect (struct disassemble_info *info)
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{
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ppc_cpu_t dialect = 0;
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dialect = POWERPC_DIALECT (info);
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/* Disassemble according to the section headers flags for VLE-mode. */
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if (dialect & PPC_OPCODE_VLE
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&& info->section->owner != NULL
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&& bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
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&& elf_object_id (info->section->owner) == PPC32_ELF_DATA
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&& (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
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return dialect;
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else
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return dialect & ~ PPC_OPCODE_VLE;
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}
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/* Handle -m and -M options that set cpu type, and .machine arg. */
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ppc_cpu_t
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ppc_parse_cpu (ppc_cpu_t ppc_cpu, const char *arg)
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{
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const ppc_cpu_t retain_mask = (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
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| PPC_OPCODE_SPE | PPC_OPCODE_ANY
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| PPC_OPCODE_VLE | PPC_OPCODE_PMR);
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/* Sticky bits. */
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ppc_cpu_t retain_flags = ppc_cpu & retain_mask;
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unsigned int i;
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for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
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if (strcmp (ppc_opts[i].opt, arg) == 0)
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{
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if (ppc_opts[i].sticky)
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{
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retain_flags |= ppc_opts[i].sticky;
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if ((ppc_cpu & ~retain_mask) != 0)
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break;
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}
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ppc_cpu = ppc_opts[i].cpu;
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break;
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}
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if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
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return 0;
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ppc_cpu |= retain_flags;
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return ppc_cpu;
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}
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/* Determine which set of machines to disassemble for. */
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static void
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powerpc_init_dialect (struct disassemble_info *info)
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{
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ppc_cpu_t dialect = 0;
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char *arg;
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struct dis_private *priv = calloc (sizeof (*priv), 1);
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if (priv == NULL)
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priv = &private;
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arg = info->disassembler_options;
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while (arg != NULL)
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{
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ppc_cpu_t new_cpu = 0;
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char *end = strchr (arg, ',');
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if (end != NULL)
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*end = 0;
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if ((new_cpu = ppc_parse_cpu (dialect, arg)) != 0)
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dialect = new_cpu;
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else if (strcmp (arg, "32") == 0)
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dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
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else if (strcmp (arg, "64") == 0)
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dialect |= PPC_OPCODE_64;
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else
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fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
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if (end != NULL)
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*end++ = ',';
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arg = end;
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}
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if ((dialect & ~(ppc_cpu_t) PPC_OPCODE_64) == 0)
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{
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if (info->mach == bfd_mach_ppc64)
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dialect |= PPC_OPCODE_64;
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else
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dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
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if (info->mach == bfd_mach_ppc_vle)
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dialect |= PPC_OPCODE_PPC | PPC_OPCODE_VLE;
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else
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/* Choose a reasonable default. */
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dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601
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| PPC_OPCODE_ALTIVEC);
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}
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info->private_data = priv;
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POWERPC_DIALECT(info) = dialect;
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}
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#define PPC_OPCD_SEGS 64
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static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
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#define VLE_OPCD_SEGS 32
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static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
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/* Calculate opcode table indices to speed up disassembly,
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and init dialect. */
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void
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disassemble_init_powerpc (struct disassemble_info *info)
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{
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int i;
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unsigned short last;
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i = powerpc_num_opcodes;
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while (--i >= 0)
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{
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unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
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powerpc_opcd_indices[op] = i;
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}
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last = powerpc_num_opcodes;
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for (i = PPC_OPCD_SEGS; i > 0; --i)
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{
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if (powerpc_opcd_indices[i] == 0)
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powerpc_opcd_indices[i] = last;
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last = powerpc_opcd_indices[i];
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}
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i = vle_num_opcodes;
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while (--i >= 0)
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{
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unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
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unsigned seg = VLE_OP_TO_SEG (op);
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vle_opcd_indices[seg] = i;
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}
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last = vle_num_opcodes;
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for (i = VLE_OPCD_SEGS; i > 0; --i)
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{
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if (vle_opcd_indices[i] == 0)
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vle_opcd_indices[i] = last;
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last = vle_opcd_indices[i];
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}
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if (info->arch == bfd_arch_powerpc)
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powerpc_init_dialect (info);
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}
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/* Print a big endian PowerPC instruction. */
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int
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print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
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{
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return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
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}
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/* Print a little endian PowerPC instruction. */
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int
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print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
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{
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return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
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}
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/* Print a POWER (RS/6000) instruction. */
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int
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print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
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{
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return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
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}
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|
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/* Extract the operand value from the PowerPC or POWER instruction. */
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static long
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operand_value_powerpc (const struct powerpc_operand *operand,
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unsigned long insn, ppc_cpu_t dialect)
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{
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long value;
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int invalid;
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/* Extract the value from the instruction. */
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if (operand->extract)
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value = (*operand->extract) (insn, dialect, &invalid);
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else
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{
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if (operand->shift >= 0)
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value = (insn >> operand->shift) & operand->bitm;
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else
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value = (insn << -operand->shift) & operand->bitm;
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if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
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{
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/* BITM is always some number of zeros followed by some
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number of ones, followed by some number of zeros. */
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unsigned long top = operand->bitm;
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/* top & -top gives the rightmost 1 bit, so this
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fills in any trailing zeros. */
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top |= (top & -top) - 1;
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top &= ~(top >> 1);
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value = (value ^ top) - top;
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}
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}
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return value;
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}
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|
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/* Determine whether the optional operand(s) should be printed. */
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|
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static int
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skip_optional_operands (const unsigned char *opindex,
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unsigned long insn, ppc_cpu_t dialect)
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{
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const struct powerpc_operand *operand;
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for (; *opindex != 0; opindex++)
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{
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operand = &powerpc_operands[*opindex];
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if ((operand->flags & PPC_OPERAND_NEXT) != 0
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|| ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
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&& operand_value_powerpc (operand, insn, dialect) != 0))
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return 0;
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}
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return 1;
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}
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/* Find a match for INSN in the opcode table, given machine DIALECT.
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|
A DIALECT of -1 is special, matching all machine opcode variations. */
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|
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static const struct powerpc_opcode *
|
|
lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
|
|
{
|
|
const struct powerpc_opcode *opcode;
|
|
const struct powerpc_opcode *opcode_end;
|
|
unsigned long op;
|
|
|
|
/* Get the major opcode of the instruction. */
|
|
op = PPC_OP (insn);
|
|
|
|
/* Find the first match in the opcode table for this major opcode. */
|
|
opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
|
|
for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
|
|
opcode < opcode_end;
|
|
++opcode)
|
|
{
|
|
const unsigned char *opindex;
|
|
const struct powerpc_operand *operand;
|
|
int invalid;
|
|
|
|
if ((insn & opcode->mask) != opcode->opcode
|
|
|| (dialect != (ppc_cpu_t) -1
|
|
&& ((opcode->flags & dialect) == 0
|
|
|| (opcode->deprecated & dialect) != 0)))
|
|
continue;
|
|
|
|
/* Check validity of operands. */
|
|
invalid = 0;
|
|
for (opindex = opcode->operands; *opindex != 0; opindex++)
|
|
{
|
|
operand = powerpc_operands + *opindex;
|
|
if (operand->extract)
|
|
(*operand->extract) (insn, dialect, &invalid);
|
|
}
|
|
if (invalid)
|
|
continue;
|
|
|
|
return opcode;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
/* Find a match for INSN in the VLE opcode table. */
|
|
|
|
static const struct powerpc_opcode *
|
|
lookup_vle (unsigned long insn)
|
|
{
|
|
const struct powerpc_opcode *opcode;
|
|
const struct powerpc_opcode *opcode_end;
|
|
unsigned op, seg;
|
|
|
|
op = PPC_OP (insn);
|
|
if (op >= 0x20 && op <= 0x37)
|
|
{
|
|
/* This insn has a 4-bit opcode. */
|
|
op &= 0x3c;
|
|
}
|
|
seg = VLE_OP_TO_SEG (op);
|
|
|
|
/* Find the first match in the opcode table for this major opcode. */
|
|
opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
|
|
for (opcode = vle_opcodes + vle_opcd_indices[seg];
|
|
opcode < opcode_end;
|
|
++opcode)
|
|
{
|
|
unsigned long table_opcd = opcode->opcode;
|
|
unsigned long table_mask = opcode->mask;
|
|
bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
|
|
unsigned long insn2;
|
|
const unsigned char *opindex;
|
|
const struct powerpc_operand *operand;
|
|
int invalid;
|
|
|
|
insn2 = insn;
|
|
if (table_op_is_short)
|
|
insn2 >>= 16;
|
|
if ((insn2 & table_mask) != table_opcd)
|
|
continue;
|
|
|
|
/* Check validity of operands. */
|
|
invalid = 0;
|
|
for (opindex = opcode->operands; *opindex != 0; ++opindex)
|
|
{
|
|
operand = powerpc_operands + *opindex;
|
|
if (operand->extract)
|
|
(*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
|
|
}
|
|
if (invalid)
|
|
continue;
|
|
|
|
return opcode;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
/* Print a PowerPC or POWER instruction. */
|
|
|
|
static int
|
|
print_insn_powerpc (bfd_vma memaddr,
|
|
struct disassemble_info *info,
|
|
int bigendian,
|
|
ppc_cpu_t dialect)
|
|
{
|
|
bfd_byte buffer[4];
|
|
int status;
|
|
unsigned long insn;
|
|
const struct powerpc_opcode *opcode;
|
|
bfd_boolean insn_is_short;
|
|
|
|
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
|
|
if (status != 0)
|
|
{
|
|
/* The final instruction may be a 2-byte VLE insn. */
|
|
if ((dialect & PPC_OPCODE_VLE) != 0)
|
|
{
|
|
/* Clear buffer so unused bytes will not have garbage in them. */
|
|
buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
|
|
status = (*info->read_memory_func) (memaddr, buffer, 2, info);
|
|
if (status != 0)
|
|
{
|
|
(*info->memory_error_func) (status, memaddr, info);
|
|
return -1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
(*info->memory_error_func) (status, memaddr, info);
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
if (bigendian)
|
|
insn = bfd_getb32 (buffer);
|
|
else
|
|
insn = bfd_getl32 (buffer);
|
|
|
|
/* Get the major opcode of the insn. */
|
|
opcode = NULL;
|
|
insn_is_short = FALSE;
|
|
if ((dialect & PPC_OPCODE_VLE) != 0)
|
|
{
|
|
opcode = lookup_vle (insn);
|
|
if (opcode != NULL)
|
|
insn_is_short = PPC_OP_SE_VLE(opcode->mask);
|
|
}
|
|
if (opcode == NULL)
|
|
opcode = lookup_powerpc (insn, dialect);
|
|
if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
|
|
opcode = lookup_powerpc (insn, (ppc_cpu_t) -1);
|
|
|
|
if (opcode != NULL)
|
|
{
|
|
const unsigned char *opindex;
|
|
const struct powerpc_operand *operand;
|
|
int need_comma;
|
|
int need_paren;
|
|
int skip_optional;
|
|
|
|
if (opcode->operands[0] != 0)
|
|
(*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
|
|
else
|
|
(*info->fprintf_func) (info->stream, "%s", opcode->name);
|
|
|
|
if (insn_is_short)
|
|
/* The operands will be fetched out of the 16-bit instruction. */
|
|
insn >>= 16;
|
|
|
|
/* Now extract and print the operands. */
|
|
need_comma = 0;
|
|
need_paren = 0;
|
|
skip_optional = -1;
|
|
for (opindex = opcode->operands; *opindex != 0; opindex++)
|
|
{
|
|
long value;
|
|
|
|
operand = powerpc_operands + *opindex;
|
|
|
|
/* Operands that are marked FAKE are simply ignored. We
|
|
already made sure that the extract function considered
|
|
the instruction to be valid. */
|
|
if ((operand->flags & PPC_OPERAND_FAKE) != 0)
|
|
continue;
|
|
|
|
/* If all of the optional operands have the value zero,
|
|
then don't print any of them. */
|
|
if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
|
|
{
|
|
if (skip_optional < 0)
|
|
skip_optional = skip_optional_operands (opindex, insn,
|
|
dialect);
|
|
if (skip_optional)
|
|
continue;
|
|
}
|
|
|
|
value = operand_value_powerpc (operand, insn, dialect);
|
|
|
|
if (need_comma)
|
|
{
|
|
(*info->fprintf_func) (info->stream, ",");
|
|
need_comma = 0;
|
|
}
|
|
|
|
/* Print the operand as directed by the flags. */
|
|
if ((operand->flags & PPC_OPERAND_GPR) != 0
|
|
|| ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
|
|
(*info->fprintf_func) (info->stream, "r%ld", value);
|
|
else if ((operand->flags & PPC_OPERAND_FPR) != 0)
|
|
(*info->fprintf_func) (info->stream, "f%ld", value);
|
|
else if ((operand->flags & PPC_OPERAND_VR) != 0)
|
|
(*info->fprintf_func) (info->stream, "v%ld", value);
|
|
else if ((operand->flags & PPC_OPERAND_VSR) != 0)
|
|
(*info->fprintf_func) (info->stream, "vs%ld", value);
|
|
else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
|
|
(*info->print_address_func) (memaddr + value, info);
|
|
else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
|
|
(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
|
|
else if ((operand->flags & PPC_OPERAND_FSL) != 0)
|
|
(*info->fprintf_func) (info->stream, "fsl%ld", value);
|
|
else if ((operand->flags & PPC_OPERAND_FCR) != 0)
|
|
(*info->fprintf_func) (info->stream, "fcr%ld", value);
|
|
else if ((operand->flags & PPC_OPERAND_UDI) != 0)
|
|
(*info->fprintf_func) (info->stream, "%ld", value);
|
|
else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
|
|
&& (((dialect & PPC_OPCODE_PPC) != 0)
|
|
|| ((dialect & PPC_OPCODE_VLE) != 0)))
|
|
(*info->fprintf_func) (info->stream, "cr%ld", value);
|
|
else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
|
|
&& (((dialect & PPC_OPCODE_PPC) != 0)
|
|
|| ((dialect & PPC_OPCODE_VLE) != 0)))
|
|
{
|
|
static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
|
|
int cr;
|
|
int cc;
|
|
|
|
cr = value >> 2;
|
|
if (cr != 0)
|
|
(*info->fprintf_func) (info->stream, "4*cr%d+", cr);
|
|
cc = value & 3;
|
|
(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
|
|
}
|
|
else
|
|
(*info->fprintf_func) (info->stream, "%d", (int) value);
|
|
|
|
if (need_paren)
|
|
{
|
|
(*info->fprintf_func) (info->stream, ")");
|
|
need_paren = 0;
|
|
}
|
|
|
|
if ((operand->flags & PPC_OPERAND_PARENS) == 0)
|
|
need_comma = 1;
|
|
else
|
|
{
|
|
(*info->fprintf_func) (info->stream, "(");
|
|
need_paren = 1;
|
|
}
|
|
}
|
|
|
|
/* We have found and printed an instruction.
|
|
If it was a short VLE instruction we have more to do. */
|
|
if (insn_is_short)
|
|
{
|
|
memaddr += 2;
|
|
return 2;
|
|
}
|
|
else
|
|
/* Otherwise, return. */
|
|
return 4;
|
|
}
|
|
|
|
/* We could not find a match. */
|
|
(*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
|
|
|
|
return 4;
|
|
}
|
|
|
|
void
|
|
print_ppc_disassembler_options (FILE *stream)
|
|
{
|
|
unsigned int i, col;
|
|
|
|
fprintf (stream, _("\n\
|
|
The following PPC specific disassembler options are supported for use with\n\
|
|
the -M switch:\n"));
|
|
|
|
for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
|
|
{
|
|
col += fprintf (stream, " %s,", ppc_opts[i].opt);
|
|
if (col > 66)
|
|
{
|
|
fprintf (stream, "\n");
|
|
col = 0;
|
|
}
|
|
}
|
|
fprintf (stream, " 32, 64\n");
|
|
}
|