ed443b61e1
When I exercise GDBserver software single step, I see the following error, which has been already handled by GDB properly. In GDBserver log, we can see, GDBserver tries to single step instruction on 0xb6e0a6e4, and destination address is 0xffff0fe0, stop pc is 0xb6e0a6e4 Writing f001f0e7 to 0xffff0fe0 in process 7132 Failed to insert breakpoint at 0xffff0fe0 (Input/output error). Failed to insert breakpoint at 0xffff0fe0 (-1). (gdb) disassemble __aeabi_read_tp,+8 Dump of assembler code from 0xb6e0a6e0 to 0xb6e0a6e8: 0xb6e0a6e0 <__aeabi_read_tp+0>: mvn r0, #61440 ; 0xf000 0xb6e0a6e4 <__aeabi_read_tp+4>: sub pc, r0, #31 however, it fails inserting breakpoint there. This problem has already fixed by GDB, see comments in arm-linux-tdep.c:arm_linux_software_single_step /* The Linux kernel offers some user-mode helpers in a high page. We can not read this page (as of 2.6.23), and even if we could then we couldn't set breakpoints in it, and even if we could then the atomic operations would fail when interrupted. They are all called as functions and return to the address in LR, so step to there instead. */ so we need to do the same thing in GDB side as well. This patch adds a new field fixup in arm_get_next_pcs_ops, so that we can fix up PC for arm-linux target. In this way, both GDB and GDBserver can single step instructions going to kernel helpers. gdb: 2016-02-12 Yao Qi <yao.qi@linaro.org> * arch/arm-get-next-pcs.c (arm_get_next_pcs): Call self->ops->fixup if it isn't NULL. * arch/arm-get-next-pcs.h: Include gdb_vecs.h. (struct arm_get_next_pcs_ops) <fixup>: New field. * arch/arm-linux.c: Include common-regcache.h and arch/arm-get-next-pcs.h. (arm_linux_get_next_pcs_fixup): New function. * arch/arm-linux.h (arm_linux_get_next_pcs_fixup): Declare. * arm-linux-tdep.c (arm_linux_get_next_pcs_ops): Initialize it with arm_linux_get_next_pcs_fixup. (arm_linux_software_single_step): Move code to arm_linux_get_next_pcs_fixup. * arm-tdep.c (arm_get_next_pcs_ops): Initialize it. gdb/gdbserver: 2016-02-12 Yao Qi <yao.qi@linaro.org> * linux-arm-low.c (get_next_pcs_ops): Initialize it with arm_linux_get_next_pcs_fixup.
66 lines
2.2 KiB
C
66 lines
2.2 KiB
C
/* Common code for ARM software single stepping support.
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Copyright (C) 1988-2016 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef ARM_GET_NEXT_PCS_H
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#define ARM_GET_NEXT_PCS_H 1
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#include "gdb_vecs.h"
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/* Forward declaration. */
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struct arm_get_next_pcs;
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/* get_next_pcs operations. */
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struct arm_get_next_pcs_ops
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{
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ULONGEST (*read_mem_uint) (CORE_ADDR memaddr, int len, int byte_order);
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CORE_ADDR (*syscall_next_pc) (struct arm_get_next_pcs *self, CORE_ADDR pc);
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CORE_ADDR (*addr_bits_remove) (struct arm_get_next_pcs *self, CORE_ADDR val);
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int (*is_thumb) (struct arm_get_next_pcs *self);
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/* Fix up PC if needed. */
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CORE_ADDR (*fixup) (struct arm_get_next_pcs *self, CORE_ADDR pc);
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};
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/* Context for a get_next_pcs call on ARM. */
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struct arm_get_next_pcs
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{
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/* Operations implementations. */
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struct arm_get_next_pcs_ops *ops;
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/* Byte order for data. */
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int byte_order;
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/* Byte order for code. */
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int byte_order_for_code;
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/* Whether the target has 32-bit thumb-2 breakpoint defined or
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not. */
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int has_thumb2_breakpoint;
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/* Registry cache. */
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struct regcache *regcache;
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};
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/* Initialize arm_get_next_pcs. */
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void arm_get_next_pcs_ctor (struct arm_get_next_pcs *self,
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struct arm_get_next_pcs_ops *ops,
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int byte_order,
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int byte_order_for_code,
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int has_thumb2_breakpoint,
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struct regcache *regcache);
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/* Find the next possible PCs after the current instruction executes. */
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VEC (CORE_ADDR) *arm_get_next_pcs (struct arm_get_next_pcs *self);
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#endif /* ARM_GET_NEXT_PCS_H */
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