92fa45795d
[ChangeLog] start-sanitize-gxsim 1998-11-13 Frank Ch. Eigler <fche@elastic.org> * configure.in: Added "--enable-sim-gx" option. * configure: Regenerated. end-sanitize-gxsim [common/ChangeLog] 1998-11-13 Frank Ch. Eigler <fche@elastic.org> start-sanitize-gxsim * Make-common.im: Build sim-gx.o and sim-gx-run.o. * sim-gx.c: New file: target-independent gx routines. * sim-gx.h: Declarations for gx structs and routines. * sim-gx-run.c: New file: target-independent gx driver. * sim-base.h: Add gx block vector to state struct. end-sanitize-gxsim * aclocal.m4: Add tests for dlopen family.
1038 lines
34 KiB
C
1038 lines
34 KiB
C
/* GX M32R implementation.
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Copyright (C) 1998 Cygnus Solutions.
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*/
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#include <stdio.h>
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#include <time.h>
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#include <stdlib.h>
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/* common simulator framework */
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#include "sim-main.h"
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#include "sim-base.h"
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#include "sim-core.h"
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#include "sim-gx.h"
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#include "sim-assert.h"
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#include "targ-vals.h"
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/* internal functions */
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void m32r_emit_long_insn(sim_gx_block* block, PCADDR pc, unsigned insn, int optimized);
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void m32r_emit_short_insn(sim_gx_block* block, PCADDR pc, unsigned insn, int optimized);
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/* callback functions */
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unsigned m32r_gx_load(unsigned pc, unsigned addr);
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void m32r_gx_store(unsigned pc, unsigned addr, unsigned data);
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signed char m32r_gx_load1(unsigned pc, unsigned addr);
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void m32r_gx_store1(unsigned pc, unsigned addr, signed char data);
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signed short m32r_gx_load2(unsigned pc, unsigned addr);
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void m32r_gx_store2(unsigned pc, unsigned addr, signed short data);
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void m32r_gx_syscall(tgx_syscall_data* data);
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/* external functions */
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void
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tgx_block_ctor(sim_gx_block* block, sim_cia cia)
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{
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/* pick translation boundaries */
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unsigned_4 origin, length, divisor;
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#define GX_PAGE_SIZE 4096
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origin = (cia / GX_PAGE_SIZE) * GX_PAGE_SIZE;
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length = GX_PAGE_SIZE;
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/* fill in general target-dependent fields */
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divisor = 4; /* m32r instruction-pairs occur on word boundaries */
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tgx_block_ctor2(block, origin, length, divisor);
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}
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void
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tgx_block_ctor2(sim_gx_block* block, unsigned_4 origin,
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unsigned_4 length, unsigned_4 divisor)
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{
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block->origin = origin;
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block->length = length;
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block->divisor = divisor;
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/* allocate pc_flags array */
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block->pc_flags = zalloc(block->length / block->divisor);
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/* allocate tgx_callbacks */
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block->callbacks = zalloc(sizeof(tgx_callbacks));
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block->callbacks->load = m32r_gx_load;
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block->callbacks->store = m32r_gx_store;
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block->callbacks->load1 = m32r_gx_load1;
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block->callbacks->store1 = m32r_gx_store1;
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block->callbacks->load2 = m32r_gx_load2;
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block->callbacks->store2 = m32r_gx_store2;
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block->callbacks->syscall = m32r_gx_syscall;
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}
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void
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tgx_emit_pre_function(sim_gx_block* gx, int optimized)
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{
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sim_gx_compiled_block* block = optimized ? gx->optimized_block : gx->learning_block;
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ASSERT(block->source_file != NULL);
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fprintf(block->source_file, "\n");
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fprintf(block->source_file, "#include <stdio.h>\n");
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fprintf(block->source_file, "\n");
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fprintf(block->source_file, /* match with definition in sim-main.h! */
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"typedef struct tgx_cpu_regs\n"
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"{\n"
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" unsigned int h_pc; /* program counter */\n"
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" signed int h_gr[16]; /* general registers */\n"
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" unsigned int h_cr[16]; /* control registers */\n"
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" long long h_accum; /* accumulator */\n"
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" unsigned h_lock; /* lock */\n"
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"} tgx_cpu_regs;\n");
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fprintf(block->source_file, /* match with definition in sim-main.h! */
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"typedef struct tgx_syscall_data\n"
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"{\n"
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" unsigned pc;\n"
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" unsigned func;\n"
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" unsigned arg1;\n"
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" unsigned arg2;\n"
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" unsigned arg3;\n"
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" unsigned errcode;\n"
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" unsigned result;\n"
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" unsigned result2;\n"
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"} tgx_syscall_data;\n");
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fprintf(block->source_file, /* match with definition in sim-main.h! */
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"typedef struct tgx_callbacks\n"
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"{\n"
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" unsigned (*load)(unsigned pc, unsigned addr);\n"
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" void (*store)(unsigned pc, unsigned addr, unsigned data);\n"
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" signed char (*load1)(unsigned pc, unsigned addr);\n"
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" void (*store1)(unsigned pc, unsigned addr, signed char data);\n"
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" signed short (*load2)(unsigned pc, unsigned addr);\n"
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" void (*store2)(unsigned pc, unsigned addr, signed short data);\n"
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" void (*syscall)(tgx_syscall_data* data);\n"
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"} tgx_callbacks;\n");
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}
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void
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tgx_emit_load_block(sim_gx_block* gx, int optimized)
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{
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sim_gx_compiled_block* block =
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optimized ? gx->optimized_block : gx->learning_block;
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ASSERT(block->source_file != NULL);
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fprintf(block->source_file, /* match with definition above */
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" unsigned int pc = regs->h_pc;\n"
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" unsigned int npc = pc;\n"
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" signed int temp;\n"
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" signed int gr0 = regs->h_gr[0], gr1 = regs->h_gr[1];\n"
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" signed int gr2 = regs->h_gr[2], gr3 = regs->h_gr[3];\n"
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" signed int gr4 = regs->h_gr[4], gr5 = regs->h_gr[5];\n"
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" signed int gr6 = regs->h_gr[6], gr7 = regs->h_gr[7];\n"
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" signed int gr8 = regs->h_gr[8], gr9 = regs->h_gr[9];\n"
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" signed int gr10 = regs->h_gr[10], gr11 = regs->h_gr[11];\n"
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" signed int gr12 = regs->h_gr[12], gr13 = regs->h_gr[13];\n"
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" signed int gr14 = regs->h_gr[14];\n"
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" unsigned int cr0 = regs->h_cr[0], cr1 = regs->h_cr[1];\n"
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" unsigned int cr2 = regs->h_cr[2], cr3 = regs->h_cr[3];\n"
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" unsigned int cr4 = regs->h_cr[4], cr5 = regs->h_cr[5];\n"
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" unsigned int cr6 = regs->h_cr[6], cr7 = regs->h_cr[7];\n"
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" unsigned int cr8 = regs->h_cr[8], cr9 = regs->h_cr[9];\n"
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" unsigned int cr10 = regs->h_cr[10], cr11 = regs->h_cr[11];\n"
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" unsigned int cr12 = regs->h_cr[12], cr13 = regs->h_cr[13];\n"
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" unsigned int cr14 = regs->h_cr[14], cr15 = regs->h_cr[15];\n"
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" long long accum = regs->h_accum;\n"
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" unsigned cond = cr0 & 0x01;\n"
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" unsigned sm = cr0 & 0x80;\n"
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" unsigned int gr15 = sm ? cr3 : cr2;\n"
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" unsigned lock = regs->h_lock;\n");
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}
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sim_cia
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tgx_emit_insn(sim_gx_block* gx, sim_cia cia, int optimized)
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{
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PCADDR pc = cia;
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SIM_DESC sd = CURRENT_STATE;
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sim_cpu* cpu = STATE_CPU (sd, 0);
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USI insn = sim_core_read_unaligned_4 (cpu, NULL_CIA, exec_map, cia);
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USI insn1 = (insn >> 16) & 0xffff;
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USI insn2 = insn & 0xffff;
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sim_gx_compiled_block* block =
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optimized ? gx->optimized_block : gx->learning_block;
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ASSERT(block->source_file != NULL);
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/* classify instruction word */
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if (insn & 0x80000000) /* single long word */
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m32r_emit_long_insn(gx, pc, insn, optimized);
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else /* two sequential half words */
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{
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/* translate first instruction */
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m32r_emit_short_insn(gx, pc, insn1, optimized);
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if(insn2 & 0x8000) /* parallel? */
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{
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fprintf(block->source_file, " /* || */\n");
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insn2 &= 0x7fff;
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/* XXX: genuine parallelism handling */
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}
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else
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fprintf(block->source_file, " /* -> */\n");
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/* translate second instruction */
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m32r_emit_short_insn(gx, pc + 2, insn2, optimized);
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}
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return cia + 4; /* next instruction pair */
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}
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void
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tgx_emit_save_block(sim_gx_block* gx, int optimized)
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{
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sim_gx_compiled_block* block =
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optimized ? gx->optimized_block : gx->learning_block;
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ASSERT(block->source_file != NULL);
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fprintf(block->source_file, /* match with definition above */
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" cr0 = (cr0 & 0x00c140) | (sm ? 0x80 : 0 ) | (cond ? 1 : 0);\n"
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" cr1 = cond ? 1 : 0;\n"
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" cr2 = sm ? cr2 : gr15;\n"
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" cr3 = sm ? gr15 : cr3;\n"
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" regs->h_pc = npc;\n"
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" regs->h_gr[0] = gr0, regs->h_gr[1] = gr1;\n"
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" regs->h_gr[2] = gr2, regs->h_gr[3] = gr3;\n"
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" regs->h_gr[4] = gr4, regs->h_gr[5] = gr5;\n"
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" regs->h_gr[6] = gr6, regs->h_gr[7] = gr7;\n"
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" regs->h_gr[8] = gr8, regs->h_gr[9] = gr9;\n"
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" regs->h_gr[10] = gr10, regs->h_gr[11] = gr11;\n"
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" regs->h_gr[12] = gr12, regs->h_gr[13] = gr13;\n"
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" regs->h_gr[14] = gr14, regs->h_gr[15] = gr15;\n"
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" regs->h_cr[0] = cr0, regs->h_cr[1] = cr1;\n"
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" regs->h_cr[2] = cr2, regs->h_cr[3] = cr3;\n"
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" regs->h_cr[4] = cr4, regs->h_cr[5] = cr5;\n"
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" regs->h_cr[6] = cr6, regs->h_cr[7] = cr7;\n"
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" regs->h_cr[8] = cr8, regs->h_cr[9] = cr9;\n"
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" regs->h_cr[10] = cr10, regs->h_cr[11] = cr11;\n"
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" regs->h_cr[12] = cr12, regs->h_cr[13] = cr13;\n"
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" regs->h_cr[14] = cr14, regs->h_cr[15] = cr15;\n"
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" regs->h_accum = accum;\n"
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" regs->h_lock = lock;\n");
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}
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void
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tgx_emit_post_function(sim_gx_block* gx, int optimized)
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{
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sim_gx_compiled_block* block =
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optimized ? gx->optimized_block : gx->learning_block;
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ASSERT(block->source_file != NULL);
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fprintf(block->source_file, "\n/* end of file */\n");
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}
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void
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tgx_block_dtor(sim_gx_block* block)
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{
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}
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int
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tgx_optimize_test(sim_gx_block* block)
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{
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unsigned_4 current_time = time(NULL);
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unsigned_4 constant_time = current_time - block->learn_last_change;
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int opt;
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/* try another optimize run if the system has settled down */
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opt = (block->compile_time != 0
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&& block->learn_last_change != 0
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&& constant_time > block->compile_time);
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/*
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if(opt)
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printf("optimize_test: now: %d, chg: %d, comp: %d, count: %d => opt %d\n",
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current_time, block->learn_last_change, block->compile_time,
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block->opt_compile_count, opt);
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*/
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return opt;
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}
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unsigned
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m32r_gx_load(unsigned pc, unsigned addr)
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{
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SIM_DESC sd = CURRENT_STATE;
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sim_cpu* cpu = STATE_CPU (sd, 0);
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USI data = sim_core_read_unaligned_4 (cpu, pc, read_map, addr);
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return data;
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}
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void
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m32r_gx_store(unsigned pc, unsigned addr, unsigned data)
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{
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SIM_DESC sd = CURRENT_STATE;
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sim_cpu* cpu = STATE_CPU (sd, 0);
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sim_core_write_unaligned_4 (cpu, pc, write_map, addr, data);
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}
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signed char
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m32r_gx_load1(unsigned pc, unsigned addr)
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{
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SIM_DESC sd = CURRENT_STATE;
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sim_cpu* cpu = STATE_CPU (sd, 0);
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signed char data = sim_core_read_unaligned_1 (cpu, pc, read_map, addr);
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return data;
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}
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void
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m32r_gx_store1(unsigned pc, unsigned addr, signed char data)
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{
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SIM_DESC sd = CURRENT_STATE;
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sim_cpu* cpu = STATE_CPU (sd, 0);
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sim_core_write_unaligned_1 (cpu, pc, write_map, addr, data);
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}
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signed short
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m32r_gx_load2(unsigned pc, unsigned addr)
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{
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SIM_DESC sd = CURRENT_STATE;
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sim_cpu* cpu = STATE_CPU (sd, 0);
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signed short data = sim_core_read_unaligned_2 (cpu, pc, read_map, addr);
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return data;
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}
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void
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m32r_gx_store2(unsigned pc, unsigned addr, signed short data)
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{
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SIM_DESC sd = CURRENT_STATE;
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sim_cpu* cpu = STATE_CPU (sd, 0);
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sim_core_write_unaligned_2 (cpu, pc, write_map, addr, data);
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}
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static int
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syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
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unsigned long taddr, char *buf, int bytes)
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{
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SIM_DESC sd = (SIM_DESC) sc->p1;
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SIM_CPU *cpu = (SIM_CPU *) sc->p2;
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return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
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}
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static int
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syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
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unsigned long taddr, const char *buf, int bytes)
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{
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SIM_DESC sd = (SIM_DESC) sc->p1;
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SIM_CPU *cpu = (SIM_CPU *) sc->p2;
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return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
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}
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void
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m32r_gx_syscall(tgx_syscall_data* data)
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{
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SIM_DESC sd = CURRENT_STATE;
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sim_cpu* cpu = STATE_CPU (sd, 0);
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host_callback *cb = STATE_CALLBACK (sd);
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CB_SYSCALL s;
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CB_SYSCALL_INIT (&s);
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s.func = data->func;
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s.arg1 = data->arg1;
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s.arg2 = data->arg2;
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s.arg3 = data->arg3;
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if (s.func == TARGET_SYS_exit)
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{
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sim_engine_halt (sd, cpu, NULL, data->pc, sim_exited, s.arg1);
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exit(s.arg1);
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}
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s.p1 = (PTR) sd;
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s.p2 = (PTR) cpu;
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s.read_mem = syscall_read_mem;
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s.write_mem = syscall_write_mem;
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cb_syscall (cb, &s);
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data->errcode = s.errcode;
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data->result = s.result;
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data->result2 = s.result2;
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}
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void
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m32r_emit_long_insn(sim_gx_block* gx, PCADDR pc, unsigned insn, int optimized)
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{
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int op1 = (insn & 0xf0000000) >> 28;
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int r1 = (insn & 0x0f000000) >> 24;
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int op2 = (insn & 0x00f00000) >> 20;
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int r2 = (insn & 0x000f0000) >> 16;
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short lit2 = (insn & 0x0000ffff);
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int lit3 = (insn & 0x00ffffff);
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sim_gx_compiled_block* block = optimized ? gx->optimized_block : gx->learning_block;
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FILE* f = block->source_file;
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ASSERT(block->source_file != NULL);
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if(op1 == 0x8 && op2 == 0x4 && r1 == 0)
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{
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fprintf(f, " /* CMPI R%d,#%d */\n", r2, lit2);
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fprintf(f, " cond = (gr%d < %d);\n", r2, lit2);
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}
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else if(op1 == 0x8 && op2 == 0x5 && r1 == 0)
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{
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fprintf(f, " /* CMPUI R%d,#%d */\n", r2, lit2);
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fprintf(f, " cond = ((unsigned) gr%d < %u);\n", r2, (unsigned)((int) lit2));
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}
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else if(op1 == 0x8 && op2 == 0x8)
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{
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fprintf(f, " /* ADDV3 R%d,R%d,#%d */\n", r1, r2, lit2);
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fprintf(f, " temp = gr%d + %d;\n", r2, lit2);
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fprintf(f, " cond = (~(gr%d & %d) & (gr%d ^ temp)) & (1<<31);\n", r2, lit2, r2);
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fprintf(f, " gr%d = temp;\n", r1);
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}
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else if(op1 == 0x8 && op2 == 0xa)
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{
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fprintf(f, " /* ADD3 R%d,R%d,#%d */\n", r1, r2, lit2);
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fprintf(f, " gr%d = gr%d + %d;\n", r1, r2, lit2);
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}
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else if(op1 == 0x8 && op2 == 0xc)
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{
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fprintf(f, " /* AND3 R%d,R%d,#%u */\n", r1, r2, (unsigned short) lit2);
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fprintf(f, " gr%d = gr%d & %u;\n", r1, r2, (unsigned short) lit2);
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}
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else if(op1 == 0x8 && op2 == 0xd)
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{
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fprintf(f, " /* XOR3 R%d,R%d,#%d */\n", r1, r2, lit2);
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fprintf(f, " gr%d = gr%d ^ %d;\n", r1, r2, lit2);
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}
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else if(op1 == 0x8 && op2 == 0xe)
|
|
{
|
|
fprintf(f, " /* OR3 R%d,R%d,#%u */\n", r1, r2, (unsigned short) lit2);
|
|
fprintf(f, " gr%d = gr%d | %u;\n", r1, r2, (unsigned short) lit2);
|
|
}
|
|
|
|
else if(op1 == 0x9 && op2 == 0x0 && lit2 == 0)
|
|
{
|
|
fprintf(f, " /* DIV R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " if(gr%d != 0)\n", r2);
|
|
fprintf(f, " gr%d = gr%d / gr%d;\n", r1, r1, r2);
|
|
}
|
|
else if(op1 == 0x9 && op2 == 0x1 && lit2 == 0)
|
|
{
|
|
fprintf(f, " /* DIVU R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " if(gr%d != 0)\n", r2);
|
|
fprintf(f, " gr%d = (unsigned) gr%d / (unsigned) gr%d;\n", r1, r1, r2);
|
|
}
|
|
else if(op1 == 0x9 && op2 == 0x2 && lit2 == 0)
|
|
{
|
|
fprintf(f, " /* REM R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " if(gr%d != 0)\n", r2);
|
|
fprintf(f, " gr%d = gr%d %% gr%d;\n", r1, r1, r2);
|
|
}
|
|
else if(op1 == 0x9 && op2 == 0x3 && lit2 == 0)
|
|
{
|
|
fprintf(f, " /* REMU R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " if(gr%d != 0)\n", r2);
|
|
fprintf(f, " gr%d = (unsigned) gr%d %% (unsigned) gr%d;\n", r1, r1, r2);
|
|
}
|
|
else if(op1 == 0x9 && op2 == 0x8)
|
|
{
|
|
fprintf(f, " /* SRL3 R%d,R%d,#%d */\n", r1, r2, lit2);
|
|
fprintf(f, " gr%d = (unsigned) gr%d >> %d;\n", r1, r2, (lit2 & 0x1f));
|
|
}
|
|
else if(op1 == 0x9 && op2 == 0xa)
|
|
{
|
|
fprintf(f, " /* SRA3 R%d,R%d,#%d */\n", r1, r2, lit2);
|
|
fprintf(f, " gr%d = gr%d >> %d;\n", r1, r2, (lit2 & 0x1f));
|
|
}
|
|
else if(op1 == 0x9 && op2 == 0xc)
|
|
{
|
|
fprintf(f, " /* SLL3 R%d,R%d,#%d */\n", r1, r2, lit2);
|
|
fprintf(f, " gr%d = gr%d << %d;\n", r1, r2, (lit2 & 0x1f));
|
|
}
|
|
else if(op1 == 0x9 && op2 == 0xf && r2 == 0)
|
|
{
|
|
fprintf(f, " /* LDI R%d,#%d */\n", r1, lit2);
|
|
fprintf(f, " gr%d = %d;\n", r1, lit2);
|
|
}
|
|
|
|
else if(op1 == 0xa && op2 == 0x0)
|
|
{
|
|
fprintf(f, " /* STB R%d,@(%d,R%d) */\n", r1, lit2, r2);
|
|
fprintf(f, " (*(callbacks->store1))(0x%08x, gr%d + %d, gr%d & 0xff);\n", (unsigned)pc, r2, lit2, r1);
|
|
}
|
|
else if(op1 == 0xa && op2 == 0x2)
|
|
{
|
|
fprintf(f, " /* STH R%d,@(%d,R%d) */\n", r1, lit2, r2);
|
|
fprintf(f, " (*(callbacks->store2))(0x%08x, gr%d + %d, gr%d & 0xffff);\n", (unsigned)pc, r2, lit2, r1);
|
|
}
|
|
else if(op1 == 0xa && op2 == 0x4)
|
|
{
|
|
fprintf(f, " /* ST R%d,@(%d,R%d) */\n", r1, lit2, r2);
|
|
fprintf(f, " (*(callbacks->store))(0x%08x, gr%d + %d, gr%d);\n", (unsigned)pc, r2, lit2, r1);
|
|
}
|
|
else if(op1 == 0xa && op2 == 0x8)
|
|
{
|
|
fprintf(f, " /* LDB R%d,@(%d,R%d) */\n", r1, lit2, r2);
|
|
fprintf(f, " gr%d = (*(callbacks->load1))(0x%08x, gr%d + %d);\n", r1, (unsigned)pc, r2, lit2);
|
|
}
|
|
else if(op1 == 0xa && op2 == 0x9)
|
|
{
|
|
fprintf(f, " /* LDUB R%d,@(%d,R%d) */\n", r1, lit2, r2);
|
|
fprintf(f, " gr%d = (unsigned char)(*(callbacks->load1))(0x%08x, gr%d + %d);\n", r1, (unsigned)pc, r2, lit2);
|
|
}
|
|
else if(op1 == 0xa && op2 == 0xa)
|
|
{
|
|
fprintf(f, " /* LDH R%d,@(%d,R%d) */\n", r1, lit2, r2);
|
|
fprintf(f, " gr%d = (*(callbacks->load2))(0x%08x, gr%d + %d);\n", r1, (unsigned)pc, r2, lit2);
|
|
}
|
|
else if(op1 == 0xa && op2 == 0xb)
|
|
{
|
|
fprintf(f, " /* LDUH R%d,@(%d,R%d) */\n", r1, lit2, r2);
|
|
fprintf(f, " gr%d = (unsigned short)(*(callbacks->load2))(0x%08x, gr%d + %d);\n", r1, (unsigned)pc, r2, lit2);
|
|
}
|
|
else if(op1 == 0xa && op2 == 0xc)
|
|
{
|
|
fprintf(f, " /* LD R%d,@(%d,R%d) */\n", r1, lit2, r2);
|
|
fprintf(f, " gr%d = (*(callbacks->load))(0x%08x, gr%d + %d);\n", r1, (unsigned)pc, r2, lit2);
|
|
}
|
|
|
|
else if(op1 == 0xb && op2 == 0x0)
|
|
{
|
|
unsigned newpc = (pc & 0xfffffffc) + (((int) lit2) << 2);
|
|
fprintf(f, " /* BEQ R%d,R%d,%d */\n", r1, r2, lit2);
|
|
fprintf(f, " if (gr%d == gr%d)\n", r1, r2);
|
|
fprintf(f, " {\n");
|
|
fprintf(f, " npc = 0x%08x;\n", newpc);
|
|
fprintf(f, " goto %s;\n", (GX_PC_INCLUDES(gx,newpc)) ? "shortjump" : "longjump");
|
|
fprintf(f, " }\n");
|
|
}
|
|
else if(op1 == 0xb && op2 == 0x1)
|
|
{
|
|
unsigned newpc = (pc & 0xfffffffc) + (((int) lit2) << 2);
|
|
fprintf(f, " /* BNE R%d,R%d,%d */\n", r1, r2, lit2);
|
|
fprintf(f, " if (gr%d != gr%d)\n", r1, r2);
|
|
fprintf(f, " {\n");
|
|
fprintf(f, " npc = 0x%08x;\n", newpc);
|
|
fprintf(f, " goto %s;\n", (GX_PC_INCLUDES(gx,newpc)) ? "shortjump" : "longjump");
|
|
fprintf(f, " }\n");
|
|
}
|
|
else if(op1 == 0xb && op2 == 0x8 && r1 == 0)
|
|
{
|
|
unsigned newpc = (pc & 0xfffffffc) + (((int) lit2) << 2);
|
|
fprintf(f, " /* BEQZ R%d,%d */\n", r2, lit2);
|
|
fprintf(f, " if (gr%d == 0)\n", r2);
|
|
fprintf(f, " {\n");
|
|
fprintf(f, " npc = 0x%08x;\n", newpc);
|
|
fprintf(f, " goto %s;\n", (GX_PC_INCLUDES(gx,newpc)) ? "shortjump" : "longjump");
|
|
fprintf(f, " }\n");
|
|
}
|
|
else if(op1 == 0xb && op2 == 0x9 && r1 == 0)
|
|
{
|
|
unsigned newpc = (pc & 0xfffffffc) + (((int) lit2) << 2);
|
|
fprintf(f, " /* BNEZ R%d,%d */\n", r2, lit2);
|
|
fprintf(f, " if (gr%d != 0)\n", r2);
|
|
fprintf(f, " {\n");
|
|
fprintf(f, " npc = 0x%08x;\n", newpc);
|
|
fprintf(f, " goto %s;\n", (GX_PC_INCLUDES(gx,newpc)) ? "shortjump" : "longjump");
|
|
fprintf(f, " }\n");
|
|
}
|
|
else if(op1 == 0xb && op2 == 0xa && r1 == 0x0)
|
|
{
|
|
unsigned newpc = (pc & 0xfffffffc) + (((int) lit2) << 2);
|
|
fprintf(f, " /* BLTZ R%d,%d */\n", r2, lit2);
|
|
fprintf(f, " if (gr%d < 0)\n", r2);
|
|
fprintf(f, " {\n");
|
|
fprintf(f, " npc = 0x%08x;\n", newpc);
|
|
fprintf(f, " goto %s;\n", (GX_PC_INCLUDES(gx,newpc)) ? "shortjump" : "longjump");
|
|
fprintf(f, " }\n");
|
|
}
|
|
else if(op1 == 0xb && op2 == 0xb && r1 == 0x0)
|
|
{
|
|
unsigned newpc = (pc & 0xfffffffc) + (((int) lit2) << 2);
|
|
fprintf(f, " /* BGEZ R%d,%d */\n", r2, lit2);
|
|
fprintf(f, " if (gr%d >= 0)\n", r2);
|
|
fprintf(f, " {\n");
|
|
fprintf(f, " npc = 0x%08x;\n", newpc);
|
|
fprintf(f, " goto %s;\n", (GX_PC_INCLUDES(gx,newpc)) ? "shortjump" : "longjump");
|
|
fprintf(f, " }\n");
|
|
}
|
|
else if(op1 == 0xb && op2 == 0xc && r1 == 0x0)
|
|
{
|
|
unsigned newpc = (pc & 0xfffffffc) + (((int) lit2) << 2);
|
|
fprintf(f, " /* BLEZ R%d,%d */\n", r2, lit2);
|
|
fprintf(f, " if (gr%d <= 0)\n", r2);
|
|
fprintf(f, " {\n");
|
|
fprintf(f, " npc = 0x%08x;\n", newpc);
|
|
fprintf(f, " goto %s;\n", (GX_PC_INCLUDES(gx,newpc)) ? "shortjump" : "longjump");
|
|
fprintf(f, " }\n");
|
|
}
|
|
else if(op1 == 0xb && op2 == 0xd && r1 == 0x0)
|
|
{
|
|
unsigned newpc = (pc & 0xfffffffc) + (((int) lit2) << 2);
|
|
fprintf(f, " /* BGTZ R%d,%d */\n", r2, lit2);
|
|
fprintf(f, " if (gr%d > 0)\n", r2);
|
|
fprintf(f, " {\n");
|
|
fprintf(f, " npc = 0x%08x;\n", newpc);
|
|
fprintf(f, " goto %s;\n", (GX_PC_INCLUDES(gx,newpc)) ? "shortjump" : "longjump");
|
|
fprintf(f, " }\n");
|
|
}
|
|
|
|
else if(op1 == 0xd && op2 == 0xc && r2 == 0)
|
|
{
|
|
fprintf(f, " /* SETH R%d,#%d */\n", r1, lit2);
|
|
fprintf(f, " gr%d = 0x%08x;\n", r1, (lit2 << 16));
|
|
}
|
|
|
|
else if(op1 == 0xe)
|
|
{
|
|
fprintf(f, " /* LD24 R%d,#%d */\n", r1, lit3);
|
|
fprintf(f, " gr%d = 0x%08x;\n", r1, lit3);
|
|
}
|
|
|
|
else if(op1 == 0xf && r1 == 0xc)
|
|
{
|
|
unsigned newpc = (pc & 0xfffffffc) + (((lit3 << 8) >> 8) << 2);
|
|
fprintf(f, " /* BC %d */\n", lit3);
|
|
fprintf(f, " if (cond)\n");
|
|
fprintf(f, " {\n");
|
|
fprintf(f, " npc = 0x%08x;\n", newpc);
|
|
fprintf(f, " goto %s;\n", (GX_PC_INCLUDES(gx,newpc)) ? "shortjump" : "longjump");
|
|
fprintf(f, " }\n");
|
|
}
|
|
else if(op1 == 0xf && r1 == 0xd)
|
|
{
|
|
unsigned newpc = (pc & 0xfffffffc) + (((lit3 << 8) >> 8) << 2);
|
|
fprintf(f, " /* BNC %d */\n", lit3);
|
|
fprintf(f, " if (! cond)\n");
|
|
fprintf(f, " {\n");
|
|
fprintf(f, " npc = 0x%08x;\n", newpc);
|
|
fprintf(f, " goto %s;\n", (GX_PC_INCLUDES(gx,newpc)) ? "shortjump" : "longjump");
|
|
fprintf(f, " }\n");
|
|
}
|
|
else if(op1 == 0xf && r1 == 0xe)
|
|
{
|
|
unsigned newpc = (pc & 0xfffffffc) + (((lit3 << 8) >> 8) << 2);
|
|
unsigned retpc = (pc & 0xfffffffc) + 4;
|
|
fprintf(f, " /* BL %d */\n", lit3);
|
|
fprintf(f, " gr14 = 0x%08x;\n", retpc);
|
|
fprintf(f, " npc = 0x%08x;\n", newpc);
|
|
fprintf(f, " goto %s;\n", (GX_PC_INCLUDES(gx,newpc)) ? "shortjump" : "longjump");
|
|
}
|
|
else if(op1 == 0xf && r1 == 0xf)
|
|
{
|
|
unsigned newpc = (pc & 0xfffffffc) + (((lit3 << 8) >> 8) << 2);
|
|
fprintf(f, " /* BRA %d */\n", lit3);
|
|
fprintf(f, " npc = 0x%08x;\n", newpc);
|
|
fprintf(f, " goto %s;\n", (GX_PC_INCLUDES(gx,newpc)) ? "shortjump" : "longjump");
|
|
}
|
|
|
|
else
|
|
{
|
|
/* illegal instruction */
|
|
/* XXX */
|
|
fprintf(f, " printf(\"ILLEGAL INSN 0x%08x @ PC 0x%08x\\n\");\n", insn, (unsigned)pc);
|
|
fprintf(f, " abort();\n");
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
m32r_emit_short_insn(sim_gx_block* gx, PCADDR pc, unsigned insn, int optimized)
|
|
{
|
|
int op1 = (insn & 0xf000) >> 12;
|
|
int r1 = (insn & 0x0f00) >> 8;
|
|
int op2 = (insn & 0x00f0) >> 4;
|
|
int op2part = (insn & 0x00e0) >> 5;
|
|
int r2 = (insn & 0x000f);
|
|
signed char c = (insn & 0x00ff);
|
|
signed char c5 = (insn & 0x001f);
|
|
sim_gx_compiled_block* block = optimized ? gx->optimized_block : gx->learning_block;
|
|
FILE* f = block->source_file;
|
|
|
|
ASSERT(f != NULL);
|
|
|
|
if(0)
|
|
; /* place holder */
|
|
else if(op1 == 0x0 && op2 == 0x0)
|
|
{
|
|
fprintf(f, " /* SUBV R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " temp = gr%d - gr%d;\n", r1, r2);
|
|
fprintf(f, " cond = (unsigned) gr%d < (unsigned) gr%d;\n", r1, r2);
|
|
fprintf(f, " gr%d = temp;\n", r1);
|
|
}
|
|
else if(op1 == 0x0 && op2 == 0x1)
|
|
{
|
|
fprintf(f, " /* SUBX R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " temp = gr%d - gr%d - (cond ? 1:0);\n", r1, r2);
|
|
fprintf(f, " cond = (unsigned) gr%d < (unsigned) gr%d;\n", r1, r2);
|
|
fprintf(f, " gr%d = temp;\n", r1);
|
|
}
|
|
else if(op1 == 0x0 && op2 == 0x2)
|
|
{
|
|
fprintf(f, " /* SUB R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = gr%d - gr%d;\n", r1, r1, r2);
|
|
}
|
|
else if(op1 == 0x0 && op2 == 0x3)
|
|
{
|
|
fprintf(f, " /* NEG R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = 0 - gr%d;\n", r1, r2);
|
|
}
|
|
else if(op1 == 0x0 && op2 == 0x4)
|
|
{
|
|
fprintf(f, " /* CMP R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " cond = (gr%d < gr%d);\n", r1, r2);
|
|
}
|
|
else if(op1 == 0x0 && op2 == 0x5)
|
|
{
|
|
fprintf(f, " /* CMPU R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " cond = ((unsigned) gr%d < (unsigned) gr%d);\n", r1, r2);
|
|
}
|
|
else if(op1 == 0x0 && op2 == 0x8)
|
|
{
|
|
fprintf(f, " /* ADDV R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " temp = gr%d + gr%d;\n", r1, r2);
|
|
fprintf(f, " cond = ((gr%d & gr%d) | (gr%d & ~temp) | (gr%d & ~temp)) & (1<<31);\n", r1, r2, r1, r2);
|
|
fprintf(f, " cond = (gr%d ^ gr%d ^ temp ^ cond) & (1<<31);\n", r1, r2);
|
|
fprintf(f, " gr%d = temp;\n", r1);
|
|
}
|
|
else if(op1 == 0x0 && op2 == 0x9)
|
|
{
|
|
fprintf(f, " /* ADDX R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " temp = gr%d + gr%d + (cond ? 1:0);\n", r1, r2);
|
|
fprintf(f, " cond = ((gr%d & gr%d) | (gr%d & ~temp) | (gr%d & ~temp)) & (1<<31);\n", r1, r2, r1, r2);
|
|
fprintf(f, " gr%d = temp;\n", r1);
|
|
}
|
|
else if(op1 == 0x0 && op2 == 0xa)
|
|
{
|
|
fprintf(f, " /* ADD R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = gr%d + gr%d;\n", r1, r1, r2);
|
|
}
|
|
else if(op1 == 0x0 && op2 == 0xb)
|
|
{
|
|
fprintf(f, " /* NOT R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = ~ gr%d;\n", r1, r2);
|
|
}
|
|
else if(op1 == 0x0 && op2 == 0xc)
|
|
{
|
|
fprintf(f, " /* AND R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = gr%d & gr%d;\n", r1, r1, r2);
|
|
}
|
|
else if(op1 == 0x0 && op2 == 0xd)
|
|
{
|
|
fprintf(f, " /* XOR R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = gr%d ^ gr%d;\n", r1, r1, r2);
|
|
}
|
|
else if(op1 == 0x0 && op2 == 0xe)
|
|
{
|
|
fprintf(f, " /* OR R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = gr%d | gr%d;\n", r1, r1, r2);
|
|
}
|
|
|
|
else if(op1 == 0x1 && op2 == 0x0)
|
|
{
|
|
fprintf(f, " /* SRL R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = (unsigned) gr%d >> (gr%d & 0x1f);\n", r1, r1, r2);
|
|
}
|
|
else if(op1 == 0x1 && op2 == 0x2)
|
|
{
|
|
fprintf(f, " /* SRA R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = gr%d >> (gr%d & 0x1f);\n", r1, r1, r2);
|
|
}
|
|
else if(op1 == 0x1 && op2 == 0x4)
|
|
{
|
|
fprintf(f, " /* SLL R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = gr%d << (gr%d & 0x1f);\n", r1, r1, r2);
|
|
}
|
|
else if(op1 == 0x1 && op2 == 0x6)
|
|
{
|
|
fprintf(f, " /* MUL R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = gr%d * gr%d;\n", r1, r1, r2);
|
|
}
|
|
else if(op1 == 0x1 && op2 == 0x8)
|
|
{
|
|
fprintf(f, " /* MV R%d,R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = gr%d;\n", r1, r2);
|
|
}
|
|
else if(op1 == 0x1 && op2 == 0x9)
|
|
{
|
|
fprintf(f, " /* MVFC R%d,CR%d */\n", r1, r2);
|
|
if(r2 == 0) /* psw */
|
|
fprintf(f, " gr%d = (cr0 & 0x00c140) | (sm ? 0x80 : 0 ) | (cond ? 1 : 0);\n", r1);
|
|
else if(r2 == 1) /* cbr */
|
|
fprintf(f, " gr%d = (cond ? 1 : 0);\n", r1);
|
|
else if(r2 == 2) /* spi */
|
|
{
|
|
fprintf(f, " if (sm) gr%d = cr2;\n", r1);
|
|
fprintf(f, " else gr%d = gr15;\n", r1);
|
|
}
|
|
else if(r2 == 3) /* spu */
|
|
{
|
|
fprintf(f, " if (!sm) gr%d = cr3;\n", r1);
|
|
fprintf(f, " else gr%d = gr15;\n", r1);
|
|
}
|
|
else
|
|
fprintf(f, " gr%d = cr%d;\n", r1, r2);
|
|
}
|
|
else if(op1 == 0x1 && op2 == 0xa)
|
|
{
|
|
fprintf(f, " /* MVTC R%d,CR%d */\n", r1, r2);
|
|
if(r2 == 0) /* psw */
|
|
{
|
|
fprintf(f, " cr0 = gr%d & 0x0000c1c1;\n", r1);
|
|
fprintf(f, " cond = cr0 & 1;\n");
|
|
fprintf(f, " cr2 = sm ? cr2 : gr15;\n");
|
|
fprintf(f, " cr3 = sm ? gr15 : cr3;\n");
|
|
fprintf(f, " sm = cr0 & 80;\n");
|
|
fprintf(f, " gr15 = sm ? cr3 : cr2;\n");
|
|
}
|
|
else if(r2 == 1) /* cbr */
|
|
; /* no effect */
|
|
else if(r2 == 2) /* spi */
|
|
{
|
|
fprintf(f, " if (sm) cr2 = gr%d;\n", r1);
|
|
fprintf(f, " else gr15 = gr%d;\n", r1);
|
|
}
|
|
else if(r2 == 3) /* spu */
|
|
{
|
|
fprintf(f, " if (!sm) cr3 = gr%d;\n", r1);
|
|
fprintf(f, " else gr15 = gr%d;\n", r1);
|
|
}
|
|
else if(r2 == 6) /* bpc */
|
|
fprintf(f, " cr6 = gr%d & 0xfffffffe;\n", r1);
|
|
else
|
|
fprintf(f, " cr%d = gr%d;\n", r1, r2);
|
|
}
|
|
else if(op1 == 0x1 && op2 == 0xc && r1 == 0xe)
|
|
{
|
|
fprintf(f, " /* JL R%d */\n", r2);
|
|
fprintf(f, " gr14 = (0x%08x & 0xfffffffc) + 4;\n", (unsigned)pc);
|
|
fprintf(f, " npc = gr%d & 0xfffffffc;\n", r2);
|
|
fprintf(f, " goto unknownjump;\n");
|
|
}
|
|
else if(op1 == 0x1 && op2 == 0xc && r1 == 0xf)
|
|
{
|
|
fprintf(f, " /* JMP R%d */\n", r2);
|
|
fprintf(f, " npc = gr%d & 0xfffffffc;\n", r2);
|
|
fprintf(f, " goto unknownjump;\n");
|
|
}
|
|
else if(op1 == 0x1 && op2 == 0xd && r1 == 0x0 && r2 == 0x6)
|
|
{
|
|
fprintf(f, " /* RTE */\n");
|
|
fprintf(f, " cr0 = (cr0 & 0xff00) | (cr0 >> 8);\n");
|
|
fprintf(f, " cond = cr0 & 0x01;\n");
|
|
fprintf(f, " sm = cr0 & 0x80;\n");
|
|
fprintf(f, " gr15 = sm ? cr3 : cr2;\n");
|
|
fprintf(f, " npc = cr6 & 0xfffffffc;\n");
|
|
fprintf(f, " goto unknownjump;\n");
|
|
}
|
|
else if(op1 == 0x1 && op2 == 0xf)
|
|
{
|
|
fprintf(f, " /* TRAP #%d */\n", r2);
|
|
if (r2 == TRAP_SYSCALL) /* general syscall ABI */
|
|
{
|
|
fprintf(f, " {\n");
|
|
fprintf(f, " tgx_syscall_data d = { 0x%08x, gr0, gr1, gr2, gr3 };\n", (unsigned) pc);
|
|
fprintf(f, " (*(callbacks->syscall))(&d);\n");
|
|
fprintf(f, " gr2 = d.errcode;\n");
|
|
fprintf(f, " gr1 = d.result;\n");
|
|
fprintf(f, " gr0 = d.result2;\n");
|
|
fprintf(f, " }\n");
|
|
}
|
|
else if (r2 == 1) /* gdb breakpoint */
|
|
{
|
|
fprintf(f, " rc = %d;\n", GX_F_HALT);
|
|
fprintf(f, " goto save;\n");
|
|
}
|
|
else
|
|
{
|
|
fprintf(f, " cr6 = 0x%08x;\n", (unsigned)(pc + 4));
|
|
fprintf(f, " cr0 = (cr0 & 0x000040) | (sm ? 0x80 : 0 ) | (cond ? 1 : 0);\n");
|
|
fprintf(f, " cr0 = (cr0 & 0x0000ff) << 8 | (cr0 & 0x0000ff);\n");
|
|
fprintf(f, " npc = 0x%08x;\n", 0x40 + (r2 * 4)); /* EIT_TRAP_BASE_ADDR */
|
|
fprintf(f, " goto unknownjump;\n");
|
|
}
|
|
}
|
|
|
|
else if(op1 == 0x2 && op2 == 0x0)
|
|
{
|
|
fprintf(f, " /* STB R%d,@R%d */\n", r1, r2);
|
|
fprintf(f, " (*(callbacks->store1))(0x%08x, gr%d, gr%d & 0xff);\n", (unsigned)pc, r2, r1);
|
|
}
|
|
else if(op1 == 0x2 && op2 == 0x2)
|
|
{
|
|
fprintf(f, " /* STH R%d,@R%d */\n", r1, r2);
|
|
fprintf(f, " (*(callbacks->store2))(0x%08x, gr%d, gr%d & 0x0000ffff);\n", (unsigned)pc, r2, r1);
|
|
}
|
|
else if(op1 == 0x2 && op2 == 0x4)
|
|
{
|
|
fprintf(f, " /* ST R%d,@R%d */\n", r1, r2);
|
|
fprintf(f, " (*(callbacks->store))(0x%08x, gr%d, gr%d);\n", (unsigned)pc, r2, r1);
|
|
}
|
|
else if(op1 == 0x2 && op2 == 0x5)
|
|
{
|
|
fprintf(f, " /* UNLOCK R%d,@R%d */\n", r1, r2);
|
|
fprintf(f, " if(lock)\n");
|
|
fprintf(f, " {\n");
|
|
fprintf(f, " lock = 0;\n");
|
|
fprintf(f, " (*(callbacks->store))(0x%08x, gr%d, gr%d);\n", (unsigned)pc, r2, r1);
|
|
fprintf(f, " }\n");
|
|
}
|
|
else if(op1 == 0x2 && op2 == 0x6)
|
|
{
|
|
fprintf(f, " /* ST R%d,@+R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = gr%d + 4;\n", r2, r2);
|
|
fprintf(f, " (*(callbacks->store))(0x%08x, gr%d, gr%d);\n", (unsigned)pc, r2, r1);
|
|
}
|
|
else if(op1 == 0x2 && op2 == 0x7)
|
|
{
|
|
fprintf(f, " /* ST R%d,@-R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = gr%d - 4;\n", r2, r2);
|
|
fprintf(f, " (*(callbacks->store))(0x%08x, gr%d, gr%d);\n", (unsigned)pc, r2, r1);
|
|
}
|
|
else if(op1 == 0x2 && op2 == 0x8)
|
|
{
|
|
fprintf(f, " /* LDB R%d,@R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = (*(callbacks->load1))(0x%08x, gr%d);\n", r1, (unsigned)pc, r2);
|
|
}
|
|
else if(op1 == 0x2 && op2 == 0x9)
|
|
{
|
|
fprintf(f, " /* LDUB R%d,@R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = (unsigned char)(*(callbacks->load1))(0x%08x, gr%d);\n", r1, (unsigned)pc, r2);
|
|
}
|
|
else if(op1 == 0x2 && op2 == 0xa)
|
|
{
|
|
fprintf(f, " /* LDH R%d,@R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = (*(callbacks->load2))(0x%08x, gr%d);\n", r1, (unsigned)pc, r2);
|
|
}
|
|
else if(op1 == 0x2 && op2 == 0xb)
|
|
{
|
|
fprintf(f, " /* LDUH R%d,@R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = (unsigned short)(*(callbacks->load2))(0x%08x, gr%d);\n", r1, (unsigned)pc, r2);
|
|
}
|
|
else if(op1 == 0x2 && op2 == 0xc)
|
|
{
|
|
fprintf(f, " /* LD R%d,@R%d */\n", r1, r2);
|
|
fprintf(f, " gr%d = (*(callbacks->load))(0x%08x, gr%d);\n", r1, (unsigned)pc, r2);
|
|
}
|
|
else if(op1 == 0x2 && op2 == 0xd)
|
|
{
|
|
fprintf(f, " /* LOCK R%d,@R%d */\n", r1, r2);
|
|
fprintf(f, " lock = 1;\n");
|
|
fprintf(f, " gr%d = (*(callbacks->load))(0x%08x, gr%d);\n", r1, (unsigned)pc, r2);
|
|
}
|
|
else if(op1 == 0x2 && op2 == 0xe)
|
|
{
|
|
fprintf(f, " /* LD R%d,@R%d+ */\n", r1, r2);
|
|
fprintf(f, " gr%d = (*(callbacks->load))(0x%08x, gr%d);\n", r1, (unsigned)pc, r2);
|
|
fprintf(f, " gr%d = gr%d + 4;\n", r2, r2);
|
|
}
|
|
|
|
else if(op1 == 0x4)
|
|
{
|
|
fprintf(f, " /* ADDI R%d,#%d */\n", r1, c);
|
|
fprintf(f, " gr%d = gr%d + %d;\n", r1, r1, c);
|
|
}
|
|
|
|
else if(op1 == 0x5 && op2part == 0x0)
|
|
{
|
|
fprintf(f, " /* SRLI R%d,#%d */\n", r1, c5);
|
|
fprintf(f, " gr%d = ((unsigned) gr%d) >> %d;\n", r1, r1, c5);
|
|
}
|
|
else if(op1 == 0x5 && op2part == 0x1)
|
|
{
|
|
fprintf(f, " /* SRAI R%d,#%d */\n", r1, c5);
|
|
fprintf(f, " gr%d = gr%d >> %d;\n", r1, r1, c5);
|
|
}
|
|
else if(op1 == 0x5 && op2part == 0x2)
|
|
{
|
|
fprintf(f, " /* SRLI R%d,#%d */\n", r1, c5);
|
|
fprintf(f, " gr%d = gr%d << %d;\n", r1, r1, c5);
|
|
}
|
|
|
|
else if(op1 == 0x6)
|
|
{
|
|
fprintf(f, " /* LDI R%d,#%d */\n", r1, c);
|
|
fprintf(f, " gr%d = 0x%08x;\n", r1, c);
|
|
}
|
|
|
|
else if(op1 == 0x7 && r1 == 0xc)
|
|
{
|
|
unsigned newpc = (pc & 0xfffffffc) + (((int) c) << 2);
|
|
fprintf(f, " /* BC %d */\n", c);
|
|
fprintf(f, " if (cond)\n");
|
|
fprintf(f, " {\n");
|
|
fprintf(f, " npc = 0x%08x;\n", newpc);
|
|
fprintf(f, " goto %s;\n", (GX_PC_INCLUDES(gx,newpc)) ? "shortjump" : "longjump");
|
|
fprintf(f, " }\n");
|
|
}
|
|
else if(op1 == 0x7 && r1 == 0xd)
|
|
{
|
|
unsigned newpc = (pc & 0xfffffffc) + (((int) c) << 2);
|
|
fprintf(f, " /* BNC %d */\n", c);
|
|
fprintf(f, " if (! cond)\n");
|
|
fprintf(f, " {\n");
|
|
fprintf(f, " npc = 0x%08x;\n", newpc);
|
|
fprintf(f, " goto %s;\n", (GX_PC_INCLUDES(gx,newpc)) ? "shortjump" : "longjump");
|
|
fprintf(f, " }\n");
|
|
}
|
|
else if(op1 == 0x7 && r1 == 0xe)
|
|
{
|
|
unsigned newpc = (pc & 0xfffffffc) + (((int) c) << 2);
|
|
unsigned retpc = (pc & 0xfffffffc) + 4;
|
|
fprintf(f, " /* BL %d */\n", c);
|
|
fprintf(f, " gr14 = 0x%08x;\n", retpc);
|
|
fprintf(f, " npc = 0x%08x;\n", newpc);
|
|
fprintf(f, " goto %s;\n", (GX_PC_INCLUDES(gx,newpc)) ? "shortjump" : "longjump");
|
|
}
|
|
else if(op1 == 0x7 && r1 == 0xf)
|
|
{
|
|
unsigned newpc = (pc & 0xfffffffc) + (((int) c) << 2);
|
|
fprintf(f, " /* BRA %d */\n", c);
|
|
fprintf(f, " npc = 0x%08x;\n", newpc);
|
|
fprintf(f, " goto %s;\n", (GX_PC_INCLUDES(gx,newpc)) ? "shortjump" : "longjump");
|
|
}
|
|
|
|
else if(op1 == 0x7 && op2 == 0x0 && r1 == 0x0 && r1 == 0x0)
|
|
{
|
|
fprintf(f, " /* NOP */\n");
|
|
}
|
|
|
|
else
|
|
{
|
|
/* illegal instruction */
|
|
/* XXX */
|
|
fprintf(f, " printf(\"ILLEGAL INSN 0x%04x @ PC 0x%08x\\n\");\n", insn, (unsigned) pc);
|
|
fprintf(f, " abort();\n");
|
|
}
|
|
}
|
|
|