472 lines
21 KiB
C
472 lines
21 KiB
C
/* Table of opcodes for the PA-RISC.
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Copyright (C) 1990, 1991, 1993 Free Software Foundation, Inc.
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Contributed by the Center for Software Science at the
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University of Utah (pa-gdb-bugs@cs.utah.edu).
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This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
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GAS/GDB is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 1, or (at your option)
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any later version.
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GAS/GDB is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS or GDB; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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#if !defined(__STDC__) && !defined(const)
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#define const
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#endif
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/*
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* Structure of an opcode table entry.
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*/
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/* There are two kinds of delay slot nullification: normal which is
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* controled by the nullification bit, and conditional, which depends
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* on the direction of the branch and its success or failure.
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*
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* NONE is unfortunately #defined in the hiux system include files.
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* #undef it away.
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*/
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#undef NONE
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enum delay_type {NONE, NORMAL, CONDITIONAL};
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struct pa_opcode
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{
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const char *name;
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unsigned long int match; /* Bits that must be set... */
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unsigned long int mask; /* ... in these bits. */
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char *args;
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/* Nonzero if this is a delayed branch instruction. */
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/* What uses this field? Nothing in opcodes or gas that I saw.
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If nothing needs it, we could reduce this table by 20% (for
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most machines). KR */
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char delayed;
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};
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/*
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All hppa opcodes are 32 bits.
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The match component is a mask saying which bits must match a
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particular opcode in order for an instruction to be an instance
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of that opcode.
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The args component is a string containing one character
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for each operand of the instruction.
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Bit positions in this description follow HP usage of lsb = 31,
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"at" is lsb of field.
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In the args field, the following characters must match exactly:
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'+,() '
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In the args field, the following characters are unused:
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' "#$% *+- ./ 3 :; = @'
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' B L [\] _'
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' e gh lm qr { } '
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Here are all the characters:
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' !"#$%&'()*+-,./0123456789:;<=>?@'
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'ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_'
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'abcdefghijklmnopqrstuvwxyz{|}~'
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Kinds of operands:
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x integer register field at 15.
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b integer register field at 10.
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t integer register field at 31.
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y floating point register field at 31
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5 5 bit immediate at 15.
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s 2 bit space specifier at 17.
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S 3 bit space specifier at 18.
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c indexed load completer.
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C short load and store completer.
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Y Store Bytes Short completer
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< non-negated compare/subtract conditions.
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a compare/subtract conditions
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d non-negated add conditions
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& logical instruction conditions
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U unit instruction conditions
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> shift/extract/deposit conditions.
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~ bvb,bb conditions
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V 5 bit immediate value at 31
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i 11 bit immediate value at 31
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j 14 bit immediate value at 31
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k 21 bit immediate value at 31
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n nullification for branch instructions
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N nullification for spop and copr instructions
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w 12 bit branch displacement
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W 17 bit branch displacement (PC relative)
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z 17 bit branch displacement (just a number, not an address)
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Also these:
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p 5 bit shift count at 26 (to support the SHD instruction) encoded as
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31-p
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P 5 bit bit position at 26
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T 5 bit field length at 31 (encoded as 32-T)
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A 13 bit immediate at 18 (to support the BREAK instruction)
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^ like b, but describes a control register
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Z System Control Completer (to support LPA, LHA, etc.)
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D 26 bit immediate at 31 (to support the DIAG instruction)
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f 3 bit Special Function Unit identifier at 25
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O 20 bit Special Function Unit operation split between 15 bits at 20
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and 5 bits at 31
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o 15 bit Special Function Unit operation at 20
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2 22 bit Special Function Unit operation split between 17 bits at 20
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and 5 bits at 31
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1 15 bit Special Function Unit operation split between 10 bits at 20
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and 5 bits at 31
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0 10 bit Special Function Unit operation split between 5 bits at 20
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and 5 bits at 31
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u 3 bit coprocessor unit identifier at 25
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F Source Floating Point Operand Format Completer encoded 2 bits at 20
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I Source Floating Point Operand Format Completer encoded 1 bits at 20
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(for 0xe format FP instructions)
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G Destination Floating Point Operand Format Completer encoded 2 bits at 18
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M Floating-Point Compare Conditions (encoded as 5 bits at 31)
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? negated compare/subtract conditions.
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! non-negated add conditions.
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s 2 bit space specifier at 17.
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b register field at 10.
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r 5 bit immediate value at 31 (for the break instruction)
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(very similar to V above, except the value is unsigned instead of
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low_sign_ext)
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R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
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(same as r above, except the value is in a different location)
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Q 5 bit immediate value at 10 (a bit position specified in
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the bb instruction. It's the same as r above, except the
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value is in a different location)
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| shift/extract/deposit conditions when used in a conditional branch
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And these (PJH) for PA-89 F.P. registers and instructions:
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v a 't' operand type extended to handle L/R register halves.
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E a 'b' operand type extended to handle L/R register halves.
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X an 'x' operand type extended to handle L/R register halves.
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J a 'b' operand type further extended to handle extra 1.1 registers
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K a 'x' operand type further extended to handle extra 1.1 registers
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4 a variation of the 'b' operand type for 'fmpyadd' and 'fmpysub'
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6 a variation of the 'x' operand type for 'fmpyadd' and 'fmpysub'
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7 a variation of the 't' operand type for 'fmpyadd' and 'fmpysub'
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8 5 bit register field at 20 (used in 'fmpyadd' and 'fmpysub')
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9 5 bit register field at 25 (used in 'fmpyadd' and 'fmpysub')
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H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
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(very similar to 'F')
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*/
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/* The order of the opcodes in this table is significant:
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* The assembler requires that all instances of the same mnemonic must be
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consecutive. If they aren't, the assembler will bomb at runtime.
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* The disassembler should not care about the order of the opcodes. */
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static const struct pa_opcode pa_opcodes[] =
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{
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/* pseudo-instructions */
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{ "b", 0xe8000000, 0xffe0e000, "nW", NORMAL}, /* bl foo,r0 */
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{ "ldi", 0x34000000, 0xffe0c000, "j,x"}, /* ldo val(r0),r */
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{ "comib", 0x84000000, 0xfc000000, "?n5,b,w", CONDITIONAL}, /* comib{tf}*/
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{ "comb", 0x80000000, 0xfc000000, "?nx,b,w", CONDITIONAL}, /* comb{tf} */
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{ "addb", 0xa0000000, 0xfc000000, "!nx,b,w", CONDITIONAL}, /* addb{tf} */
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{ "addib", 0xa4000000, 0xfc000000, "!n5,b,w", CONDITIONAL}, /* addib{tf}*/
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{ "nop", 0x08000240, 0xffffffff, ""}, /* or 0,0,0 */
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{ "copy", 0x08000240, 0xffe0ffe0, "x,t"}, /* or r,0,t */
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{ "mtsar", 0x01601840, 0xffe0ffff, "x"}, /* mtctl r,cr11 */
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/* Loads and Stores for integer registers. */
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{ "ldw", 0x48000000, 0xfc000000, "j(s,b),x"},
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{ "ldw", 0x48000000, 0xfc000000, "j(b),x"},
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{ "ldh", 0x44000000, 0xfc000000, "j(s,b),x"},
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{ "ldh", 0x44000000, 0xfc000000, "j(b),x"},
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{ "ldb", 0x40000000, 0xfc000000, "j(s,b),x"},
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{ "ldb", 0x40000000, 0xfc000000, "j(b),x"},
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{ "stw", 0x68000000, 0xfc000000, "x,j(s,b)"},
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{ "stw", 0x68000000, 0xfc000000, "x,j(b)"},
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{ "sth", 0x64000000, 0xfc000000, "x,j(s,b)"},
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{ "sth", 0x64000000, 0xfc000000, "x,j(b)"},
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{ "stb", 0x60000000, 0xfc000000, "x,j(s,b)"},
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{ "stb", 0x60000000, 0xfc000000, "x,j(b)"},
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{ "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x"},
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{ "ldwm", 0x4c000000, 0xfc000000, "j(b),x"},
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{ "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)"},
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{ "stwm", 0x6c000000, 0xfc000000, "x,j(b)"},
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{ "ldwx", 0x0c000080, 0xfc001fc0, "cx(s,b),t"},
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{ "ldwx", 0x0c000080, 0xfc001fc0, "cx(b),t"},
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{ "ldhx", 0x0c000040, 0xfc001fc0, "cx(s,b),t"},
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{ "ldhx", 0x0c000040, 0xfc001fc0, "cx(b),t"},
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{ "ldbx", 0x0c000000, 0xfc001fc0, "cx(s,b),t"},
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{ "ldbx", 0x0c000000, 0xfc001fc0, "cx(b),t"},
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{ "ldwax", 0x0c000180, 0xfc00dfc0, "cx(b),t"},
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{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cx(s,b),t"},
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{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cx(b),t"},
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{ "ldws", 0x0c001080, 0xfc001fc0, "C5(s,b),t"},
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{ "ldws", 0x0c001080, 0xfc001fc0, "C5(b),t"},
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{ "ldhs", 0x0c001040, 0xfc001fc0, "C5(s,b),t"},
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{ "ldhs", 0x0c001040, 0xfc001fc0, "C5(b),t"},
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{ "ldbs", 0x0c001000, 0xfc001fc0, "C5(s,b),t"},
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{ "ldbs", 0x0c001000, 0xfc001fc0, "C5(b),t"},
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{ "ldwas", 0x0c001180, 0xfc00dfc0, "C5(b),t"},
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{ "ldcws", 0x0c0011c0, 0xfc001fc0, "C5(s,b),t"},
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{ "ldcws", 0x0c0011c0, 0xfc001fc0, "C5(b),t"},
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{ "stws", 0x0c001280, 0xfc001fc0, "Cx,V(s,b)"},
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{ "stws", 0x0c001280, 0xfc001fc0, "Cx,V(b)"},
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{ "sths", 0x0c001240, 0xfc001fc0, "Cx,V(s,b)"},
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{ "sths", 0x0c001240, 0xfc001fc0, "Cx,V(b)"},
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{ "stbs", 0x0c001200, 0xfc001fc0, "Cx,V(s,b)"},
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{ "stbs", 0x0c001200, 0xfc001fc0, "Cx,V(b)"},
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{ "stwas", 0x0c001380, 0xfc00dfc0, "Cx,V(b)"},
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{ "stbys", 0x0c001300, 0xfc001fc0, "Yx,V(s,b)"},
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{ "stbys", 0x0c001300, 0xfc001fc0, "Yx,V(b)"},
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/* Immediate instructions. */
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{ "ldo", 0x34000000, 0xfc00c000, "j(b),x"},
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{ "ldil", 0x20000000, 0xfc000000, "k,b"},
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{ "addil", 0x28000000, 0xfc000000, "k,b"},
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/* Branching instructions. */
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{ "bl", 0xe8000000, 0xfc00e000, "nW,b", NORMAL},
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{ "gate", 0xe8002000, 0xfc00e000, "nW,b", NORMAL},
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{ "blr", 0xe8004000, 0xfc00e001, "nx,b", NORMAL},
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{ "bv", 0xe800c000, 0xfc00e001, "nx(b)", NORMAL},
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{ "bv", 0xe800c000, 0xfc00e001, "n(b)", NORMAL},
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{ "be", 0xe0000000, 0xfc000000, "nz(S,b)", NORMAL},
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{ "ble", 0xe4000000, 0xfc000000, "nz(S,b)", NORMAL},
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{ "movb", 0xc8000000, 0xfc000000, "|nx,b,w", CONDITIONAL},
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{ "movib", 0xcc000000, 0xfc000000, "|n5,b,w", CONDITIONAL},
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{ "combt", 0x80000000, 0xfc000000, "<nx,b,w", CONDITIONAL},
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{ "combf", 0x88000000, 0xfc000000, "<nx,b,w", CONDITIONAL},
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{ "comibt", 0x84000000, 0xfc000000, "<n5,b,w", CONDITIONAL},
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{ "comibf", 0x8c000000, 0xfc000000, "<n5,b,w", CONDITIONAL},
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{ "addbt", 0xa0000000, 0xfc000000, "!nx,b,w", CONDITIONAL},
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{ "addbf", 0xa8000000, 0xfc000000, "!nx,b,w", CONDITIONAL},
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{ "addibt", 0xa4000000, 0xfc000000, "!n5,b,w", CONDITIONAL},
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{ "addibf", 0xac000000, 0xfc000000, "!n5,b,w", CONDITIONAL},
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{ "bvb", 0xc0000000, 0xffe00000, "~nx,w", CONDITIONAL},
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{ "bb", 0xc4000000, 0xfc000000, "~nx,Q,w", CONDITIONAL},
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/* Computation Instructions */
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{ "add", 0x08000600, 0xfc000fe0, "dx,b,t", CONDITIONAL},
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{ "addl", 0x08000a00, 0xfc000fe0, "dx,b,t", CONDITIONAL},
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{ "addo", 0x08000e00, 0xfc000fe0, "dx,b,t", CONDITIONAL},
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{ "addc", 0x08000700, 0xfc000fe0, "dx,b,t", CONDITIONAL},
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{ "addco", 0x08000f00, 0xfc000fe0, "dx,b,t", CONDITIONAL},
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{ "sh1add", 0x08000640, 0xfc000fe0, "dx,b,t", CONDITIONAL},
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{ "sh1addl", 0x08000a40, 0xfc000fe0, "dx,b,t", CONDITIONAL},
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{ "sh1addo", 0x08000e40, 0xfc000fe0, "dx,b,t", CONDITIONAL},
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{ "sh2add", 0x08000680, 0xfc000fe0, "dx,b,t", CONDITIONAL},
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{ "sh2addl", 0x08000a80, 0xfc000fe0, "dx,b,t", CONDITIONAL},
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{ "sh2addo", 0x08000e80, 0xfc000fe0, "dx,b,t", CONDITIONAL},
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{ "sh3add", 0x080006c0, 0xfc000fe0, "dx,b,t", CONDITIONAL},
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{ "sh3addl", 0x08000ac0, 0xfc000fe0, "dx,b,t", CONDITIONAL},
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{ "sh3addo", 0x08000ec0, 0xfc000fe0, "dx,b,t", CONDITIONAL},
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{ "sub", 0x08000400, 0xfc000fe0, "ax,b,t", CONDITIONAL},
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{ "subo", 0x08000c00, 0xfc000fe0, "ax,b,t", CONDITIONAL},
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{ "subb", 0x08000500, 0xfc000fe0, "ax,b,t", CONDITIONAL},
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{ "subbo", 0x08000d00, 0xfc000fe0, "ax,b,t", CONDITIONAL},
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{ "subt", 0x080004c0, 0xfc000fe0, "ax,b,t", CONDITIONAL},
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{ "subto", 0x08000cc0, 0xfc000fe0, "ax,b,t", CONDITIONAL},
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{ "ds", 0x08000440, 0xfc000fe0, "ax,b,t", CONDITIONAL},
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{ "comclr", 0x08000880, 0xfc000fe0, "ax,b,t", CONDITIONAL},
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{ "or", 0x08000240, 0xfc000fe0, "&x,b,t", CONDITIONAL},
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{ "xor", 0x08000280, 0xfc000fe0, "&x,b,t", CONDITIONAL},
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{ "and", 0x08000200, 0xfc000fe0, "&x,b,t", CONDITIONAL},
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{ "andcm", 0x08000000, 0xfc000fe0, "&x,b,t", CONDITIONAL},
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{ "uxor", 0x08000380, 0xfc000fe0, "Ux,b,t", CONDITIONAL},
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{ "uaddcm", 0x08000980, 0xfc000fe0, "Ux,b,t", CONDITIONAL},
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{ "uaddcmt", 0x080009c0, 0xfc000fe0, "Ux,b,t", CONDITIONAL},
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{ "dcor", 0x08000b80, 0xfc1f0fe0, "Ub,t", CONDITIONAL},
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{ "idcor", 0x08000bc0, 0xfc1f0fe0, "Ub,t", CONDITIONAL},
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{ "addi", 0xb4000000, 0xfc000800, "di,b,x", CONDITIONAL},
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{ "addio", 0xb4000800, 0xfc000800, "di,b,x", CONDITIONAL},
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{ "addit", 0xb0000000, 0xfc000800, "di,b,x", CONDITIONAL},
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{ "addito", 0xb0000800, 0xfc000800, "di,b,x", CONDITIONAL},
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{ "subi", 0x94000000, 0xfc000800, "ai,b,x", CONDITIONAL},
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{ "subio", 0x94000800, 0xfc000800, "ai,b,x", CONDITIONAL},
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{ "comiclr", 0x90000000, 0xfc000800, "ai,b,x", CONDITIONAL},
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/* Extract and Deposit Instructions */
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{ "vshd", 0xd0000000, 0xfc001fe0, ">x,b,t", CONDITIONAL},
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{ "shd", 0xd0000800, 0xfc001c00, ">x,b,p,t", CONDITIONAL},
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{ "vextru", 0xd0001000, 0xfc001fe0, ">b,T,x", CONDITIONAL},
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{ "vextrs", 0xd0001400, 0xfc001fe0, ">b,T,x", CONDITIONAL},
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{ "extru", 0xd0001800, 0xfc001c00, ">b,P,T,x", CONDITIONAL},
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{ "extrs", 0xd0001c00, 0xfc001c00, ">b,P,T,x", CONDITIONAL},
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{ "zvdep", 0xd4000000, 0xfc001fe0, ">x,T,b", CONDITIONAL},
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{ "vdep", 0xd4000400, 0xfc001fe0, ">x,T,b", CONDITIONAL},
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{ "zdep", 0xd4000800, 0xfc001c00, ">x,p,T,b", CONDITIONAL},
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{ "dep", 0xd4000c00, 0xfc001c00, ">x,p,T,b", CONDITIONAL},
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{ "zvdepi", 0xd4001000, 0xfc001fe0, ">5,T,b", CONDITIONAL},
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{ "vdepi", 0xd4001400, 0xfc001fe0, ">5,T,b", CONDITIONAL},
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{ "zdepi", 0xd4001800, 0xfc001c00, ">5,p,T,b", CONDITIONAL},
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{ "depi", 0xd4001c00, 0xfc001c00, ">5,p,T,b", CONDITIONAL},
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/* System Control Instructions */
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{ "break", 0x00000000, 0xfc001fe0, "r,A"},
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{ "rfi", 0x00000c00, 0xffffffff, ""},
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{ "rfir", 0x00000ca0, 0xffffffff, ""},
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{ "ssm", 0x00000d60, 0xffe0ffe0, "R,t"},
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{ "rsm", 0x00000e60, 0xffe0ffe0, "R,t"},
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{ "mtsm", 0x00001860, 0xffe0ffff, "x"},
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{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t"},
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{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(b),t"},
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{ "mtsp", 0x00001820, 0xffe01fff, "x,S"},
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{ "mtctl", 0x00001840, 0xfc00ffff, "x,^"},
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{ "mfsp", 0x000004a0, 0xffff1fe0, "S,t"},
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{ "mfctl", 0x000008a0, 0xfc1fffe0, "^,t"},
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{ "sync", 0x00000400, 0xffffffff, ""},
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{ "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t"},
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{ "prober", 0x04001180, 0xfc003fe0, "(b),x,t"},
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{ "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t"},
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{ "proberi", 0x04003180, 0xfc003fe0, "(b),R,t"},
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{ "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t"},
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{ "probew", 0x040011c0, 0xfc003fe0, "(b),x,t"},
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{ "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t"},
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{ "probewi", 0x040031c0, 0xfc003fe0, "(b),R,t"},
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|
{ "lpa", 0x04001340, 0xfc003fc0, "Zx(s,b),t"},
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|
{ "lpa", 0x04001340, 0xfc003fc0, "Zx(b),t"},
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|
{ "lha", 0x04001300, 0xfc003fc0, "Zx(s,b),t"},
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{ "lha", 0x04001300, 0xfc003fc0, "Zx(b),t"},
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|
{ "pdtlb", 0x04001200, 0xfc003fdf, "Zx(s,b)"},
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|
{ "pdtlb", 0x04001200, 0xfc003fdf, "Zx(b)"},
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|
{ "pitlb", 0x04000200, 0xfc003fdf, "Zx(s,b)"},
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|
{ "pitlb", 0x04000200, 0xfc003fdf, "Zx(b)"},
|
|
{ "pdtlbe", 0x04001240, 0xfc003fdf, "Zx(s,b)"},
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|
{ "pdtlbe", 0x04001240, 0xfc003fdf, "Zx(b)"},
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|
{ "pitlbe", 0x04000240, 0xfc003fdf, "Zx(s,b)"},
|
|
{ "pitlbe", 0x04000240, 0xfc003fdf, "Zx(b)"},
|
|
{ "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)"},
|
|
{ "idtlba", 0x04001040, 0xfc003fff, "x,(b)"},
|
|
{ "iitlba", 0x04000040, 0xfc003fff, "x,(s,b)"},
|
|
{ "iitlba", 0x04000040, 0xfc003fff, "x,(b)"},
|
|
{ "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)"},
|
|
{ "idtlbp", 0x04001000, 0xfc003fff, "x,(b)"},
|
|
{ "iitlbp", 0x04000000, 0xfc003fff, "x,(s,b)"},
|
|
{ "iitlbp", 0x04000000, 0xfc003fff, "x,(b)"},
|
|
{ "pdc", 0x04001380, 0xfc003fdf, "Zx(s,b)"},
|
|
{ "pdc", 0x04001380, 0xfc003fdf, "Zx(b)"},
|
|
{ "fdc", 0x04001280, 0xfc003fdf, "Zx(s,b)"},
|
|
{ "fdc", 0x04001280, 0xfc003fdf, "Zx(b)"},
|
|
{ "fic", 0x04000280, 0xfc003fdf, "Zx(s,b)"},
|
|
{ "fic", 0x04000280, 0xfc003fdf, "Zx(b)"},
|
|
{ "fdce", 0x040012c0, 0xfc003fdf, "Zx(s,b)"},
|
|
{ "fdce", 0x040012c0, 0xfc003fdf, "Zx(b)"},
|
|
{ "fice", 0x040002c0, 0xfc003fdf, "Zx(s,b)"},
|
|
{ "fice", 0x040002c0, 0xfc003fdf, "Zx(b)"},
|
|
{ "diag", 0x14000000, 0xfc000000, "D"},
|
|
|
|
/* gfw and gfr are not in the HP PA 1.1 manual, but they are in either
|
|
the Timex FPU or the Mustang ERS (not sure which) manual. */
|
|
{ "gfw", 0x04001680, 0xfc003fdf, "Zx(s,b)"},
|
|
{ "gfw", 0x04001680, 0xfc003fdf, "Zx(b)"},
|
|
{ "gfr", 0x04001a80, 0xfc003fdf, "Zx(s,b)"},
|
|
{ "gfr", 0x04001a80, 0xfc003fdf, "Zx(b)"},
|
|
|
|
/* Floating Point Coprocessor Instructions */
|
|
|
|
{ "fldwx", 0x24000000, 0xfc001f80, "cx(s,b),v"},
|
|
{ "fldwx", 0x24000000, 0xfc001f80, "cx(b),v"},
|
|
{ "flddx", 0x2c000000, 0xfc001fc0, "cx(s,b),y"},
|
|
{ "flddx", 0x2c000000, 0xfc001fc0, "cx(b),y"},
|
|
{ "fstwx", 0x24000200, 0xfc001fc0, "cv,x(s,b)"},
|
|
{ "fstwx", 0x24000200, 0xfc001fc0, "cv,x(b)"},
|
|
{ "fstdx", 0x2c000200, 0xfc001fc0, "cy,x(s,b)"},
|
|
{ "fstdx", 0x2c000200, 0xfc001fc0, "cy,x(b)"},
|
|
{ "fstqx", 0x3c000200, 0xfc001fc0, "cy,x(s,b)"},
|
|
{ "fstqx", 0x3c000200, 0xfc001fc0, "cy,x(b)"},
|
|
{ "fldws", 0x24001000, 0xfc001f80, "C5(s,b),v"},
|
|
{ "fldws", 0x24001000, 0xfc001f80, "C5(b),v"},
|
|
{ "fldds", 0x2c001000, 0xfc001fc0, "C5(s,b),y"},
|
|
{ "fldds", 0x2c001000, 0xfc001fc0, "C5(b),y"},
|
|
{ "fstws", 0x24001200, 0xfc001f80, "Cv,5(s,b)"},
|
|
{ "fstws", 0x24001200, 0xfc001f80, "Cy,5(b)"},
|
|
{ "fstds", 0x2c001200, 0xfc001fc0, "Cy,5(s,b)"},
|
|
{ "fstds", 0x2c001200, 0xfc001fc0, "Cy,5(b)"},
|
|
{ "fstqs", 0x3c001200, 0xfc001fc0, "Cy,5(s,b)"},
|
|
{ "fstqs", 0x3c001200, 0xfc001fc0, "Cy,5(b)"},
|
|
{ "fadd", 0x30000600, 0xfc00e7e0, "FE,X,v"},
|
|
{ "fadd", 0x38000600, 0xfc00e720, "IJ,K,v"},
|
|
{ "fsub", 0x30002600, 0xfc00e7e0, "FE,X,v"},
|
|
{ "fsub", 0x38002600, 0xfc00e720, "IJ,K,v"},
|
|
{ "fmpy", 0x30004600, 0xfc00e7e0, "FE,X,v"},
|
|
{ "fmpy", 0x38004600, 0xfc00e720, "IJ,K,v"},
|
|
{ "fdiv", 0x30006600, 0xfc00e7e0, "FE,X,v"},
|
|
{ "fdiv", 0x38006600, 0xfc00e720, "IJ,K,v"},
|
|
{ "fsqrt", 0x30008000, 0xfc1fe7e0, "FE,v"},
|
|
{ "fsqrt", 0x38008000, 0xfc1fe720, "FJ,v"},
|
|
{ "fabs", 0x30006000, 0xfc1fe7e0, "FE,v"},
|
|
{ "fabs", 0x38006000, 0xfc1fe720, "FJ,v"},
|
|
{ "frem", 0x30008600, 0xfc00e7e0, "FE,X,v"},
|
|
{ "frem", 0x38008600, 0xfc00e720, "FJ,K,v"},
|
|
{ "frnd", 0x3000a000, 0xfc1fe7e0, "FE,v"},
|
|
{ "frnd", 0x3800a000, 0xfc1fe720, "FJ,v"},
|
|
{ "fcpy", 0x30004000, 0xfc1fe7e0, "FE,v"},
|
|
{ "fcpy", 0x38004000, 0xfc1fe720, "FJ,v"},
|
|
{ "fcnvff", 0x30000200, 0xfc1f87e0, "FGE,v"},
|
|
{ "fcnvff", 0x38000200, 0xfc1f8720, "FGJ,v"},
|
|
{ "fcnvxf", 0x30008200, 0xfc1f87e0, "FGE,v"},
|
|
{ "fcnvxf", 0x38008200, 0xfc1f8720, "FGJ,v"},
|
|
{ "fcnvfx", 0x30010200, 0xfc1f87e0, "FGE,v"},
|
|
{ "fcnvfx", 0x38010200, 0xfc1f8720, "FGJ,v"},
|
|
{ "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGE,v"},
|
|
{ "fcnvfxt", 0x38018200, 0xfc1f8720, "FGJ,v"},
|
|
{ "fcmp", 0x30000400, 0xfc00e7e0, "FME,X"},
|
|
{ "fcmp", 0x38000400, 0xfc00e720, "IMJ,K"},
|
|
{ "xmpyu", 0x38004700, 0xfc00e720, "E,X,v"},
|
|
{ "fmpyadd", 0x18000000, 0xfc000000, "H4,6,7,9,8"},
|
|
{ "fmpysub", 0x98000000, 0xfc000000, "H4,6,7,9,8"},
|
|
{ "ftest", 0x30002420, 0xffffffff, ""},
|
|
|
|
|
|
/* Assist Instructions */
|
|
|
|
{ "spop0", 0x10000000, 0xfc000600, "f,ON", NORMAL},
|
|
{ "spop1", 0x10000200, 0xfc000600, "f,oNt", NORMAL},
|
|
{ "spop2", 0x10000400, 0xfc000600, "f,1Nb", NORMAL},
|
|
{ "spop3", 0x10000600, 0xfc000600, "f,0Nx,b", NORMAL},
|
|
{ "copr", 0x30000000, 0xfc000000, "u,2N", NORMAL},
|
|
{ "cldwx", 0x24000000, 0xfc001e00, "ucx(s,b),t"},
|
|
{ "cldwx", 0x24000000, 0xfc001e00, "ucx(b),t"},
|
|
{ "clddx", 0x2c000000, 0xfc001e00, "ucx(s,b),t"},
|
|
{ "clddx", 0x2c000000, 0xfc001e00, "ucx(b),t"},
|
|
{ "cstwx", 0x24000200, 0xfc001e00, "uct,x(s,b)"},
|
|
{ "cstwx", 0x24000200, 0xfc001e00, "uct,x(b)"},
|
|
{ "cstdx", 0x2c000200, 0xfc001e00, "uct,x(s,b)"},
|
|
{ "cstdx", 0x2c000200, 0xfc001e00, "uct,x(b)"},
|
|
{ "cldws", 0x24001000, 0xfc001e00, "uC5(s,b),t"},
|
|
{ "cldws", 0x24001000, 0xfc001e00, "uC5(b),t"},
|
|
{ "cldds", 0x2c001000, 0xfc001e00, "uC5(s,b),t"},
|
|
{ "cldds", 0x2c001000, 0xfc001e00, "uC5(b),t"},
|
|
{ "cstws", 0x24001200, 0xfc001e00, "uCt,5(s,b)"},
|
|
{ "cstws", 0x24001200, 0xfc001e00, "uCt,5(b)"},
|
|
{ "cstds", 0x2c001200, 0xfc001e00, "uCt,5(s,b)"},
|
|
{ "cstds", 0x2c001200, 0xfc001e00, "uCt,5(b)"},
|
|
};
|
|
|
|
#define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0]))
|
|
|
|
/* SKV 12/18/92. Added some denotations for various operands. */
|
|
|
|
#define PA_IMM11_AT_31 'i'
|
|
#define PA_IMM14_AT_31 'j'
|
|
#define PA_IMM21_AT_31 'k'
|
|
#define PA_DISP12 'w'
|
|
#define PA_DISP17 'W'
|
|
|
|
#define N_HPPA_OPERAND_FORMATS 5
|