5accf1ff56
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* callback.c: Use 'deprecated' rather than 'depreciated.'
[ igen/ChangeLog ]
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* igen.c: Use 'deprecated' rather than 'depreciated.'
[ mips/ChangeLog ]
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* interp.c: Use 'deprecated' rather than 'depreciated.'
* sim-main.h: Likewise.
805 lines
30 KiB
C
805 lines
30 KiB
C
/* MIPS Simulator definition.
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Copyright (C) 1997, 1998 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef SIM_MAIN_H
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#define SIM_MAIN_H
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/* This simulator doesn't cache the Current Instruction Address */
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/* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
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/* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
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#define SIM_HAVE_BIENDIAN
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/* hobble some common features for moment */
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#define WITH_WATCHPOINTS 1
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#define WITH_MODULO_MEMORY 1
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#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
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mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
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#include "sim-basics.h"
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typedef address_word sim_cia;
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#include "sim-base.h"
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/* Deprecated macros and types for manipulating 64bit values. Use
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../common/sim-bits.h and ../common/sim-endian.h macros instead. */
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typedef signed64 word64;
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typedef unsigned64 uword64;
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#define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
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#define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
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#define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
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#define SET64HI(t) (((uword64)(t))<<32)
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#define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
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#define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
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/* Check if a value will fit within a halfword: */
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#define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
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/* Floating-point operations: */
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#include "sim-fpu.h"
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/* FPU registers must be one of the following types. All other values
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are reserved (and undefined). */
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typedef enum {
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fmt_single = 0,
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fmt_double = 1,
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fmt_word = 4,
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fmt_long = 5,
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/* The following are well outside the normal acceptable format
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range, and are used in the register status vector. */
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fmt_unknown = 0x10000000,
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fmt_uninterpreted = 0x20000000,
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fmt_uninterpreted_32 = 0x40000000,
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fmt_uninterpreted_64 = 0x80000000U,
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} FP_formats;
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unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats));
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#define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
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void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
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#define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
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int NaN PARAMS ((unsigned64 op, FP_formats fmt));
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int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
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int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
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unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
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unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
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unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
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unsigned64 Max PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Min PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
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#define Convert(rm,op,from,to) \
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convert (SD, CPU, cia, rm, op, from, to)
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/* Macro to update FPSR condition-code field. This is complicated by
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the fact that there is a hole in the index range of the bits within
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the FCSR register. Also, the number of bits visible depends on the
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MIPS ISA version being supported. */
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#define SETFCC(cc,v) {\
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int bit = ((cc == 0) ? 23 : (24 + (cc)));\
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FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
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}
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#define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
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/* This should be the COC1 value at the start of the preceding
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instruction: */
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#define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
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#ifdef TARGET_ENABLE_FR
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/* FIXME: this should be enabled for all targets, but needs testing first. */
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#define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
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? ((SR & status_FR) ? 64 : 32) \
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: (WITH_TARGET_FLOATING_POINT_BITSIZE))
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#else
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#define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
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#endif
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/* Standard FCRS bits: */
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#define IR (0) /* Inexact Result */
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#define UF (1) /* UnderFlow */
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#define OF (2) /* OverFlow */
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#define DZ (3) /* Division by Zero */
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#define IO (4) /* Invalid Operation */
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#define UO (5) /* Unimplemented Operation */
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/* Get masks for individual flags: */
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#if 1 /* SAFE version */
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#define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
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#define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
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#define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
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#else
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#define FP_FLAGS(b) (1 << ((b) + 2))
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#define FP_ENABLE(b) (1 << ((b) + 7))
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#define FP_CAUSE(b) (1 << ((b) + 12))
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#endif
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#define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
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#define FP_MASK_RM (0x3)
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#define FP_SH_RM (0)
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#define FP_RM_NEAREST (0) /* Round to nearest (Round) */
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#define FP_RM_TOZERO (1) /* Round to zero (Trunc) */
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#define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */
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#define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */
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#define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
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/* HI/LO register accesses */
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/* For some MIPS targets, the HI/LO registers have certain timing
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restrictions in that, for instance, a read of a HI register must be
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separated by at least three instructions from a preceeding read.
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The struct below is used to record the last access by each of A MT,
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MF or other OP instruction to a HI/LO register. See mips.igen for
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more details. */
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typedef struct _hilo_access {
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signed64 timestamp;
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address_word cia;
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} hilo_access;
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typedef struct _hilo_history {
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hilo_access mt;
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hilo_access mf;
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hilo_access op;
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} hilo_history;
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/* Integer ALU operations: */
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#include "sim-alu.h"
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#define ALU32_END(ANS) \
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if (ALU32_HAD_OVERFLOW) \
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SignalExceptionIntegerOverflow (); \
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(ANS) = (signed32) ALU32_OVERFLOW_RESULT
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#define ALU64_END(ANS) \
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if (ALU64_HAD_OVERFLOW) \
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SignalExceptionIntegerOverflow (); \
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(ANS) = ALU64_OVERFLOW_RESULT;
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/* The following is probably not used for MIPS IV onwards: */
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/* Slots for delayed register updates. For the moment we just have a
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fixed number of slots (rather than a more generic, dynamic
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system). This keeps the simulator fast. However, we only allow
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for the register update to be delayed for a single instruction
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cycle. */
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#define PSLOTS (8) /* Maximum number of instruction cycles */
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typedef struct _pending_write_queue {
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int in;
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int out;
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int total;
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int slot_delay[PSLOTS];
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int slot_size[PSLOTS];
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int slot_bit[PSLOTS];
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void *slot_dest[PSLOTS];
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unsigned64 slot_value[PSLOTS];
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} pending_write_queue;
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#ifndef PENDING_TRACE
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#define PENDING_TRACE 0
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#endif
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#define PENDING_IN ((CPU)->pending.in)
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#define PENDING_OUT ((CPU)->pending.out)
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#define PENDING_TOTAL ((CPU)->pending.total)
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#define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
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#define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
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#define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
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#define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
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#define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
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/* Invalidate the pending write queue, all pending writes are
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discarded. */
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#define PENDING_INVALIDATE() \
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memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
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/* Schedule a write to DEST for N cycles time. For 64 bit
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destinations, schedule two writes. For floating point registers,
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the caller should schedule a write to both the dest register and
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the FPR_STATE register. When BIT is non-negative, only BIT of DEST
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is updated. */
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#define PENDING_SCHED(DEST,VAL,DELAY,BIT) \
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do { \
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if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \
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sim_engine_abort (SD, CPU, cia, \
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"PENDING_SCHED - buffer overflow\n"); \
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if (PENDING_TRACE) \
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sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n", \
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(unsigned long) cia, (unsigned long) &(DEST), \
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(unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
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PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
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PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \
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PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \
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PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \
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PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \
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PENDING_SLOT_BIT[PENDING_IN] = (BIT); \
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PENDING_IN = (PENDING_IN + 1) % PSLOTS; \
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PENDING_TOTAL += 1; \
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} while (0)
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#define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
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#define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
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#define PENDING_TICK() pending_tick (SD, CPU, cia)
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#define PENDING_FLUSH() abort () /* think about this one */
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#define PENDING_FP() abort () /* think about this one */
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/* For backward compatibility */
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#define PENDING_FILL(R,VAL) \
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do { \
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if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR) \
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{ \
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PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 1, -1); \
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PENDING_SCHED(FPR_STATE[(R) - FGRIDX], fmt_uninterpreted, 1, -1); \
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} \
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else \
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PENDING_SCHED(GPR[(R)], VAL, 1, -1); \
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} while (0)
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enum float_operation
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{
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FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD,
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FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS,
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FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
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};
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struct _sim_cpu {
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/* The following are internal simulator state variables: */
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#define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
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#define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
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address_word dspc; /* delay-slot PC */
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#define DSPC ((CPU)->dspc)
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#define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
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#define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
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/* State of the simulator */
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unsigned int state;
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unsigned int dsstate;
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#define STATE ((CPU)->state)
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#define DSSTATE ((CPU)->dsstate)
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/* Flags in the "state" variable: */
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#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
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#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
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#define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
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#define simPCOC0 (1 << 17) /* COC[1] from current */
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#define simPCOC1 (1 << 18) /* COC[1] from previous */
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#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
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#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
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#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
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#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
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#ifndef ENGINE_ISSUE_PREFIX_HOOK
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#define ENGINE_ISSUE_PREFIX_HOOK() \
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{ \
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/* Perform any pending writes */ \
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PENDING_TICK(); \
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/* Set previous flag, depending on current: */ \
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if (STATE & simPCOC0) \
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STATE |= simPCOC1; \
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else \
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STATE &= ~simPCOC1; \
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/* and update the current value: */ \
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if (GETFCC(0)) \
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STATE |= simPCOC0; \
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else \
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STATE &= ~simPCOC0; \
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}
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#endif /* ENGINE_ISSUE_PREFIX_HOOK */
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/* This is nasty, since we have to rely on matching the register
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numbers used by GDB. Unfortunately, depending on the MIPS target
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GDB uses different register numbers. We cannot just include the
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relevant "gdb/tm.h" link, since GDB may not be configured before
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the sim world, and also the GDB header file requires too much other
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state. */
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#ifndef TM_MIPS_H
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#define LAST_EMBED_REGNUM (89)
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#define NUM_REGS (LAST_EMBED_REGNUM + 1)
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#endif
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/* To keep this default simulator simple, and fast, we use a direct
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vector of registers. The internal simulator engine then uses
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manifests to access the correct slot. */
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unsigned_word registers[LAST_EMBED_REGNUM + 1];
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int register_widths[NUM_REGS];
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#define REGISTERS ((CPU)->registers)
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#define GPR (®ISTERS[0])
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#define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
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/* While space is allocated for the floating point registers in the
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main registers array, they are stored separatly. This is because
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their size may not necessarily match the size of either the
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general-purpose or system specific registers */
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#define NR_FGR (32)
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#define FGRIDX (38)
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fp_word fgr[NR_FGR];
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#define FGR ((CPU)->fgr)
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#define LO (REGISTERS[33])
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#define HI (REGISTERS[34])
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#define PCIDX 37
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#define PC (REGISTERS[PCIDX])
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#define CAUSE (REGISTERS[36])
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#define SRIDX (32)
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#define SR (REGISTERS[SRIDX]) /* CPU status register */
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#define FCR0IDX (71)
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#define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
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#define FCR31IDX (70)
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#define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
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#define FCSR (FCR31)
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#define Debug (REGISTERS[86])
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#define DEPC (REGISTERS[87])
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#define EPC (REGISTERS[88])
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/* All internal state modified by signal_exception() that may need to be
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rolled back for passing moment-of-exception image back to gdb. */
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unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
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unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
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int exc_suspended;
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#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
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#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
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#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
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unsigned_word c0_config_reg;
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#define C0_CONFIG ((CPU)->c0_config_reg)
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/* The following are pseudonyms for standard registers */
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#define ZERO (REGISTERS[0])
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#define V0 (REGISTERS[2])
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#define A0 (REGISTERS[4])
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#define A1 (REGISTERS[5])
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#define A2 (REGISTERS[6])
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#define A3 (REGISTERS[7])
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#define T8IDX 24
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#define T8 (REGISTERS[T8IDX])
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#define SPIDX 29
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#define SP (REGISTERS[SPIDX])
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#define RAIDX 31
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#define RA (REGISTERS[RAIDX])
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/* While space is allocated in the main registers arrray for some of
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the COP0 registers, that space isn't sufficient. Unknown COP0
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registers overflow into the array below */
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#define NR_COP0_GPR 32
|
|
unsigned_word cop0_gpr[NR_COP0_GPR];
|
|
#define COP0_GPR ((CPU)->cop0_gpr)
|
|
#define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
|
|
|
|
/* Keep the current format state for each register: */
|
|
FP_formats fpr_state[32];
|
|
#define FPR_STATE ((CPU)->fpr_state)
|
|
|
|
pending_write_queue pending;
|
|
|
|
/* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
|
|
read-write instructions. It is set when a linked load occurs. It
|
|
is tested and cleared by the conditional store. It is cleared
|
|
(during other CPU operations) when a store to the location would
|
|
no longer be atomic. In particular, it is cleared by exception
|
|
return instructions. */
|
|
int llbit;
|
|
#define LLBIT ((CPU)->llbit)
|
|
|
|
|
|
/* The HIHISTORY and LOHISTORY timestamps are used to ensure that
|
|
corruptions caused by using the HI or LO register too close to a
|
|
following operation is spotted. See mips.igen for more details. */
|
|
|
|
hilo_history hi_history;
|
|
#define HIHISTORY (&(CPU)->hi_history)
|
|
hilo_history lo_history;
|
|
#define LOHISTORY (&(CPU)->lo_history)
|
|
|
|
#define check_branch_bug()
|
|
#define mark_branch_bug(TARGET)
|
|
|
|
|
|
|
|
sim_cpu_base base;
|
|
};
|
|
|
|
|
|
/* MIPS specific simulator watch config */
|
|
|
|
void watch_options_install PARAMS ((SIM_DESC sd));
|
|
|
|
struct swatch {
|
|
sim_event *pc;
|
|
sim_event *clock;
|
|
sim_event *cycles;
|
|
};
|
|
|
|
|
|
/* FIXME: At present much of the simulator is still static */
|
|
struct sim_state {
|
|
|
|
struct swatch watch;
|
|
|
|
sim_cpu cpu[MAX_NR_PROCESSORS];
|
|
#if (WITH_SMP)
|
|
#define STATE_CPU(sd,n) (&(sd)->cpu[n])
|
|
#else
|
|
#define STATE_CPU(sd,n) (&(sd)->cpu[0])
|
|
#endif
|
|
|
|
|
|
sim_state_base base;
|
|
};
|
|
|
|
|
|
|
|
/* Status information: */
|
|
|
|
/* TODO : these should be the bitmasks for these bits within the
|
|
status register. At the moment the following are VR4300
|
|
bit-positions: */
|
|
#define status_KSU_mask (0x18) /* mask for KSU bits */
|
|
#define status_KSU_shift (3) /* shift for field */
|
|
#define ksu_kernel (0x0)
|
|
#define ksu_supervisor (0x1)
|
|
#define ksu_user (0x2)
|
|
#define ksu_unknown (0x3)
|
|
|
|
#define SR_KSU ((SR & status_KSU_mask) >> status_KSU_shift)
|
|
|
|
#define status_IE (1 << 0) /* Interrupt enable */
|
|
#define status_EIE (1 << 16) /* Enable Interrupt Enable */
|
|
#define status_EXL (1 << 1) /* Exception level */
|
|
#define status_RE (1 << 25) /* Reverse Endian in user mode */
|
|
#define status_FR (1 << 26) /* enables MIPS III additional FP registers */
|
|
#define status_SR (1 << 20) /* soft reset or NMI */
|
|
#define status_BEV (1 << 22) /* Location of general exception vectors */
|
|
#define status_TS (1 << 21) /* TLB shutdown has occurred */
|
|
#define status_ERL (1 << 2) /* Error level */
|
|
#define status_IM7 (1 << 15) /* Timer Interrupt Mask */
|
|
#define status_RP (1 << 27) /* Reduced Power mode */
|
|
|
|
/* Specializations for TX39 family */
|
|
#define status_IEc (1 << 0) /* Interrupt enable (current) */
|
|
#define status_KUc (1 << 1) /* Kernel/User mode */
|
|
#define status_IEp (1 << 2) /* Interrupt enable (previous) */
|
|
#define status_KUp (1 << 3) /* Kernel/User mode */
|
|
#define status_IEo (1 << 4) /* Interrupt enable (old) */
|
|
#define status_KUo (1 << 5) /* Kernel/User mode */
|
|
#define status_IM_mask (0xff) /* Interrupt mask */
|
|
#define status_IM_shift (8)
|
|
#define status_NMI (1 << 20) /* NMI */
|
|
#define status_NMI (1 << 20) /* NMI */
|
|
|
|
/* Status bits used by MIPS32/MIPS64. */
|
|
#define status_UX (1 << 5) /* 64-bit user addrs */
|
|
#define status_SX (1 << 6) /* 64-bit supervisor addrs */
|
|
#define status_KX (1 << 7) /* 64-bit kernel addrs */
|
|
#define status_TS (1 << 21) /* TLB shutdown has occurred */
|
|
#define status_PX (1 << 23) /* Enable 64 bit operations */
|
|
#define status_MX (1 << 24) /* Enable MDMX resources */
|
|
#define status_CU0 (1 << 28) /* Coprocessor 0 usable */
|
|
#define status_CU1 (1 << 29) /* Coprocessor 1 usable */
|
|
#define status_CU2 (1 << 30) /* Coprocessor 2 usable */
|
|
#define status_CU3 (1 << 31) /* Coprocessor 3 usable */
|
|
|
|
#define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */
|
|
#define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */
|
|
#define cause_CE_mask 0x30000000 /* Coprocessor exception */
|
|
#define cause_CE_shift 28
|
|
#define cause_EXC2_mask 0x00070000
|
|
#define cause_EXC2_shift 16
|
|
#define cause_IP7 (1 << 15) /* Interrupt pending */
|
|
#define cause_SIOP (1 << 12) /* SIO pending */
|
|
#define cause_IP3 (1 << 11) /* Int 0 pending */
|
|
#define cause_IP2 (1 << 10) /* Int 1 pending */
|
|
|
|
#define cause_EXC_mask (0x1c) /* Exception code */
|
|
#define cause_EXC_shift (2)
|
|
|
|
#define cause_SW0 (1 << 8) /* Software interrupt 0 */
|
|
#define cause_SW1 (1 << 9) /* Software interrupt 1 */
|
|
#define cause_IP_mask (0x3f) /* Interrupt pending field */
|
|
#define cause_IP_shift (10)
|
|
|
|
#define cause_set_EXC(x) CAUSE = (CAUSE & ~cause_EXC_mask) | ((x << cause_EXC_shift) & cause_EXC_mask)
|
|
#define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
|
|
|
|
|
|
/* NOTE: We keep the following status flags as bit values (1 for true,
|
|
0 for false). This allows them to be used in binary boolean
|
|
operations without worrying about what exactly the non-zero true
|
|
value is. */
|
|
|
|
/* UserMode */
|
|
#ifdef SUBTARGET_R3900
|
|
#define UserMode ((SR & status_KUc) ? 1 : 0)
|
|
#else
|
|
#define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
|
|
#endif /* SUBTARGET_R3900 */
|
|
|
|
/* BigEndianMem */
|
|
/* Hardware configuration. Affects endianness of LoadMemory and
|
|
StoreMemory and the endianness of Kernel and Supervisor mode
|
|
execution. The value is 0 for little-endian; 1 for big-endian. */
|
|
#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
|
|
/*(state & simBE) ? 1 : 0)*/
|
|
|
|
/* ReverseEndian */
|
|
/* This mode is selected if in User mode with the RE bit being set in
|
|
SR (Status Register). It reverses the endianness of load and store
|
|
instructions. */
|
|
#define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
|
|
|
|
/* BigEndianCPU */
|
|
/* The endianness for load and store instructions (0=little;1=big). In
|
|
User mode this endianness may be switched by setting the state_RE
|
|
bit in the SR register. Thus, BigEndianCPU may be computed as
|
|
(BigEndianMem EOR ReverseEndian). */
|
|
#define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
|
|
|
|
|
|
|
|
/* Exceptions: */
|
|
|
|
/* NOTE: These numbers depend on the processor architecture being
|
|
simulated: */
|
|
enum ExceptionCause {
|
|
Interrupt = 0,
|
|
TLBModification = 1,
|
|
TLBLoad = 2,
|
|
TLBStore = 3,
|
|
AddressLoad = 4,
|
|
AddressStore = 5,
|
|
InstructionFetch = 6,
|
|
DataReference = 7,
|
|
SystemCall = 8,
|
|
BreakPoint = 9,
|
|
ReservedInstruction = 10,
|
|
CoProcessorUnusable = 11,
|
|
IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */
|
|
Trap = 13,
|
|
FPE = 15,
|
|
DebugBreakPoint = 16, /* Impl. dep. in MIPS32/MIPS64. */
|
|
MDMX = 22,
|
|
Watch = 23,
|
|
MCheck = 24,
|
|
CacheErr = 30,
|
|
NMIReset = 31, /* Reserved in MIPS32/MIPS64. */
|
|
|
|
|
|
/* The following exception code is actually private to the simulator
|
|
world. It is *NOT* a processor feature, and is used to signal
|
|
run-time errors in the simulator. */
|
|
SimulatorFault = 0xFFFFFFFF
|
|
};
|
|
|
|
#define TLB_REFILL (0)
|
|
#define TLB_INVALID (1)
|
|
|
|
|
|
/* The following break instructions are reserved for use by the
|
|
simulator. The first is used to halt the simulation. The second
|
|
is used by gdb for break-points. NOTE: Care must be taken, since
|
|
this value may be used in later revisions of the MIPS ISA. */
|
|
#define HALT_INSTRUCTION_MASK (0x03FFFFC0)
|
|
|
|
#define HALT_INSTRUCTION (0x03ff000d)
|
|
#define HALT_INSTRUCTION2 (0x0000ffcd)
|
|
|
|
|
|
#define BREAKPOINT_INSTRUCTION (0x0005000d)
|
|
#define BREAKPOINT_INSTRUCTION2 (0x0000014d)
|
|
|
|
|
|
|
|
void interrupt_event (SIM_DESC sd, void *data);
|
|
|
|
void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
|
|
#define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction))
|
|
#define SignalExceptionInterrupt(level) signal_exception (SD, CPU, cia, Interrupt, level)
|
|
#define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch)
|
|
#define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore)
|
|
#define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad)
|
|
#define SignalExceptionDataReference() signal_exception (SD, CPU, cia, DataReference)
|
|
#define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf)
|
|
#define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE)
|
|
#define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow)
|
|
#define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
|
|
#define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset)
|
|
#define SignalExceptionTLBRefillStore() signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
|
|
#define SignalExceptionTLBRefillLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
|
|
#define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
|
|
#define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
|
|
#define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification)
|
|
#define SignalExceptionMDMX() signal_exception (SD, CPU, cia, MDMX)
|
|
#define SignalExceptionWatch() signal_exception (SD, CPU, cia, Watch)
|
|
#define SignalExceptionMCheck() signal_exception (SD, CPU, cia, MCheck)
|
|
#define SignalExceptionCacheErr() signal_exception (SD, CPU, cia, CacheErr)
|
|
|
|
/* Co-processor accesses */
|
|
|
|
/* XXX FIXME: For now, assume that FPU (cp1) is always usable. */
|
|
#define COP_Usable(coproc_num) (coproc_num == 1)
|
|
|
|
void cop_lw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
|
|
void cop_ld PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
|
|
unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
|
|
uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
|
|
|
|
#define COP_LW(coproc_num,coproc_reg,memword) \
|
|
cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
|
|
#define COP_LD(coproc_num,coproc_reg,memword) \
|
|
cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
|
|
#define COP_SW(coproc_num,coproc_reg) \
|
|
cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
|
|
#define COP_SD(coproc_num,coproc_reg) \
|
|
cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
|
|
|
|
|
|
void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
|
|
#define DecodeCoproc(instruction) \
|
|
decode_coproc (SD, CPU, cia, (instruction))
|
|
|
|
int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
|
|
|
|
|
|
|
|
/* Memory accesses */
|
|
|
|
/* The following are generic to all versions of the MIPS architecture
|
|
to date: */
|
|
|
|
/* Memory Access Types (for CCA): */
|
|
#define Uncached (0)
|
|
#define CachedNoncoherent (1)
|
|
#define CachedCoherent (2)
|
|
#define Cached (3)
|
|
|
|
#define isINSTRUCTION (1 == 0) /* FALSE */
|
|
#define isDATA (1 == 1) /* TRUE */
|
|
#define isLOAD (1 == 0) /* FALSE */
|
|
#define isSTORE (1 == 1) /* TRUE */
|
|
#define isREAL (1 == 0) /* FALSE */
|
|
#define isRAW (1 == 1) /* TRUE */
|
|
/* The parameter HOST (isTARGET / isHOST) is ignored */
|
|
#define isTARGET (1 == 0) /* FALSE */
|
|
/* #define isHOST (1 == 1) TRUE */
|
|
|
|
/* The "AccessLength" specifications for Loads and Stores. NOTE: This
|
|
is the number of bytes minus 1. */
|
|
#define AccessLength_BYTE (0)
|
|
#define AccessLength_HALFWORD (1)
|
|
#define AccessLength_TRIPLEBYTE (2)
|
|
#define AccessLength_WORD (3)
|
|
#define AccessLength_QUINTIBYTE (4)
|
|
#define AccessLength_SEXTIBYTE (5)
|
|
#define AccessLength_SEPTIBYTE (6)
|
|
#define AccessLength_DOUBLEWORD (7)
|
|
#define AccessLength_QUADWORD (15)
|
|
|
|
#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
|
|
? AccessLength_DOUBLEWORD /*7*/ \
|
|
: AccessLength_WORD /*3*/)
|
|
#define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
|
|
|
|
|
|
INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
|
|
#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
|
|
address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
|
|
|
|
INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
|
|
#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
|
|
load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
|
|
|
|
INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
|
|
#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
|
|
store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
|
|
|
|
INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
|
|
#define CacheOp(op,pAddr,vAddr,instruction) \
|
|
cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
|
|
|
|
INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
|
|
#define SyncOperation(stype) \
|
|
sync_operation (SD, CPU, cia, (stype))
|
|
|
|
INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
|
|
#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
|
|
prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
|
|
|
|
void unpredictable_action (sim_cpu *cpu, address_word cia);
|
|
#define NotWordValue(val) not_word_value (SD_, (val))
|
|
#define Unpredictable() unpredictable (SD_)
|
|
|
|
INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
|
|
#define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
|
|
INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
|
|
#define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
|
|
#define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
|
|
|
|
void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
|
|
extern FILE *tracefh;
|
|
|
|
INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
|
|
extern SIM_CORE_SIGNAL_FN mips_core_signal;
|
|
|
|
char* pr_addr PARAMS ((SIM_ADDR addr));
|
|
char* pr_uword64 PARAMS ((uword64 addr));
|
|
|
|
|
|
#define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
|
|
|
|
void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
|
|
void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
|
|
void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
|
|
|
|
|
|
#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
|
|
#include "sim-main.c"
|
|
#endif
|
|
|
|
#endif
|