339 lines
8.4 KiB
C
339 lines
8.4 KiB
C
/* This file is part of the program psim.
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Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef _PSIM_CONFIG_H_
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#define _PSIM_CONFIG_H_
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/* endianness of the host/target:
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If the build process is aware (at compile time) of the endianness
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of the host/target it is able to eliminate slower generic endian
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handling code.
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Possible values are 0 (unknown), LITTLE_ENDIAN, BIG_ENDIAN */
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#ifndef WITH_HOST_BYTE_ORDER
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#define WITH_HOST_BYTE_ORDER 0 /*unknown*/
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#endif
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#ifndef WITH_TARGET_BYTE_ORDER
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#define WITH_TARGET_BYTE_ORDER 0 /*unknown*/
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#endif
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extern int current_host_byte_order;
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#define CURRENT_HOST_BYTE_ORDER (WITH_HOST_BYTE_ORDER \
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? WITH_HOST_BYTE_ORDER \
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: current_host_byte_order)
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extern int current_target_byte_order;
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#define CURRENT_TARGET_BYTE_ORDER (WITH_TARGET_BYTE_ORDER \
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? WITH_TARGET_BYTE_ORDER \
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: current_target_byte_order)
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/* XOR endian.
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In addition to the above, the simulator can support the's horrible
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XOR endian mode (for instance implemented by the PowerPC). This
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feature makes it possible to control the endian mode of a processor
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using the MSR. */
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/* #define WITH_XOR_ENDIAN 8 */
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/* Intel host BSWAP support:
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Whether to use bswap on the 486 and pentiums rather than the 386
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sequence that uses xchgb/rorl/xchgb */
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#ifndef WITH_BSWAP
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#define WITH_BSWAP 0
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#endif
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/* SMP support:
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Sets a limit on the number of processors that can be simulated. If
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WITH_SMP is set to zero (0), the simulator is restricted to
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suporting only on processor (and as a consequence leaves the SMP
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code out of the build process).
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The actual number of processors is taken from the device
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/options/smp@<nr-cpu> */
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#if defined (WITH_SMP)
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#if WITH_SMP
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#define MAX_NR_PROCESSORS WITH_SMP
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#else
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#define MAX_NR_PROCESSORS 1
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#endif
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#endif
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/* Word size of host/target:
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Set these according to your host and target requirements. At this
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point in time, I've only compiled (not run) for a 64bit and never
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built for a 64bit host. This will always remain a compile time
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option */
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#ifndef WITH_TARGET_WORD_BITSIZE
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#define WITH_TARGET_WORD_BITSIZE 32 /* compiled only */
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#endif
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#ifndef WITH_HOST_WORD_BITSIZE
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#define WITH_HOST_WORD_BITSIZE 32 /* 64bit ready? */
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#endif
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/* Program environment:
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Three environments are available - UEA (user), VEA (virtual) and
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OEA (perating). The former two are environment that users would
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expect to see (VEA includes things like coherency and the time
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base) while OEA is what an operating system expects to see. By
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setting these to specific values, the build process is able to
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eliminate non relevent environment code
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CURRENT_ENVIRONMENT specifies which of vea or oea is required for
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the current runtime. */
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#if defined (WITH_ENVIRONMENT)
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#define USER_ENVIRONMENT 1
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#define VIRTUAL_ENVIRONMENT 2
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#define OPERATING_ENVIRONMENT 3
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extern int current_environment;
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#define CURRENT_ENVIRONMENT (WITH_ENVIRONMENT \
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? WITH_ENVIRONMENT \
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: current_environment)
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#endif
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/* Callback/Default Memory.
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Core includes a builtin memory type (raw_memory) that is
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implemented using an array. raw_memory does not require any
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additional functions etc.
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Callback memory is where the core calls a core device for the data
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it requires.
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Default memory is an extenstion of this where for addresses that do
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not map into either a callback or core memory range a default map
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can be used.
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The OEA model uses callback memory for devices and default memory
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for buses.
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The VEA model uses callback memory to capture `page faults'.
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While it may be possible to eliminate callback/default memory (and
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hence also eliminate an additional test per memory fetch) it
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probably is not worth the effort.
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BTW, while raw_memory could have been implemented as a callback,
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profiling has shown that there is a biger win (at least for the
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x86) in eliminating a function call for the most common
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(raw_memory) case. */
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#ifndef WITH_CALLBACK_MEMORY
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#define WITH_CALLBACK_MEMORY 1
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#endif
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/* Alignment:
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The PowerPC may or may not handle miss aligned transfers. An
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implementation normally handles miss aligned transfers in big
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endian mode but generates an exception in little endian mode.
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This model. Instead allows both little and big endian modes to
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either take exceptions or handle miss aligned transfers.
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If 0 is specified then for big-endian mode miss alligned accesses
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are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the
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processor will fault on them (STRICT_ALIGNMENT). */
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#if defined (WITH_ALIGNMENT)
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#define NONSTRICT_ALIGNMENT 1
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#define STRICT_ALIGNMENT 2
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extern int current_alignment;
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#define CURRENT_ALIGNMENT (WITH_ALIGNMENT \
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? WITH_ALIGNMENT \
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: current_alignment)
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#endif
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/* Floating point suport:
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Should the processor trap for all floating point instructions (as
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if the hardware wasn't implemented) or implement the floating point
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instructions directly. */
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#if defined (WITH_FLOATING_POINT)
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#define SOFT_FLOATING_POINT 1
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#define HARD_FLOATING_POINT 2
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extern int current_floating_point;
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#define CURRENT_FLOATING_POINT (WITH_FLOATING_POINT \
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? WITH_FLOATING_POINT \
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: current_floating_point)
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#endif
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/* Debugging:
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Control the inclusion of debugging code. */
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/* Include the tracing code. Disabling this eliminates all tracing
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code */
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#ifndef WITH_TRACE
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#define WITH_TRACE 1
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#endif
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/* include code that checks assertions scattered through out the
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program */
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#ifndef WITH_ASSERT
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#define WITH_ASSERT 1
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#endif
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/* Whether to check instructions for reserved bits being set */
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/* #define WITH_RESERVED_BITS 1 */
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/* include monitoring code */
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#define MONITOR_INSTRUCTION_ISSUE 1
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#define MONITOR_LOAD_STORE_UNIT 2
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/* do not define WITH_MON by default */
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#define DEFAULT_WITH_MON (MONITOR_LOAD_STORE_UNIT \
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| MONITOR_INSTRUCTION_ISSUE)
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/* Current CPU model (models are in the generated models.h include file) */
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#ifndef WITH_MODEL
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#define WITH_MODEL 0
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#endif
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#define CURRENT_MODEL (WITH_MODEL \
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? WITH_MODEL \
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: current_model)
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#ifndef WITH_DEFAULT_MODEL
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#define WITH_DEFAULT_MODEL DEFAULT_MODEL
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#endif
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#define MODEL_ISSUE_IGNORE (-1)
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#define MODEL_ISSUE_PROCESS 1
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#ifndef WITH_MODEL_ISSUE
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#define WITH_MODEL_ISSUE 0
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#endif
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extern int current_model_issue;
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#define CURRENT_MODEL_ISSUE (WITH_MODEL_ISSUE \
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? WITH_MODEL_ISSUE \
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: current_model_issue)
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/* Whether or not input/output just uses stdio, or uses printf_filtered for
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output, and polling input for input. */
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#define DONT_USE_STDIO 2
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#define DO_USE_STDIO 1
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#ifndef WITH_STDIO
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#define WITH_STDIO 0
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#endif
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extern int current_stdio;
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#define CURRENT_STDIO (WITH_STDIO \
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? WITH_STDIO \
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: current_stdio)
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/* Specify that configured calls pass parameters in registers when the
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convention is that they are placed on the stack */
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#ifndef WITH_REGPARM
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#define WITH_REGPARM 0
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#endif
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/* Specify that configured calls use an alternative calling mechanism */
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#ifndef WITH_STDCALL
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#define WITH_STDCALL 0
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#endif
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/* complete/verify/print the simulator configuration */
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/* For prefered_target_byte_order arugment */
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#if defined (bfd_little_endian)
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#define PREFERED_TARGET_BYTE_ORDER(IMAGE) ((IMAGE) == NULL \
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? 0 \
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: bfd_little_endian(IMAGE) \
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? LITTLE_ENDIAN \
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: BIG_ENDIAN)
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#else
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#define PREFERED_TARGET_BYTE_ORDER(IMAGE) ((IMAGE) == NULL \
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? 0 \
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: !(IMAGE)->xvec->byteorder_big_p \
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? LITTLE_ENDIAN \
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: BIG_ENDIAN)
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#endif
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extern void sim_config (SIM_DESC sd,
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int prefered_target_byte_order);
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extern void print_sim_config (SIM_DESC sd);
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#endif /* _PSIM_CONFIG_H */
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