1e1e3b618f
* *Modified Files: * .Sanitize ChangeLog *Added Files: * Makefile.in README.Cygnus config.in configure configure.in * device.c device.h dma.c dma.h engine-sky.c gencode.c gpuif.c * gpuif.h hardware.c hardware.h interp.c m16.igen mdmx.igen * mips.dc mips.igen pke0.c pke0.h pke1.c pke1.h r5900.igen * sim-main.h tconfig.in vr5400.igen vu0.c vu0.h vu1.c vu1.h
241 lines
5.6 KiB
Text
241 lines
5.6 KiB
Text
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// Integer Instructions
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// --------------------
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//
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// MulAcc is the Multiply Accumulator.
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// This register is mapped on the the HI and LO registers.
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// Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
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// Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
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:function:::unsigned64:MulAcc:
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{
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unsigned64 result = U8_4 (HI, LO);
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return result;
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}
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:function:::void:SET_MulAcc:unsigned64 value
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{
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*AL4_8 (&HI) = VH4_8 (value);
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*AL4_8 (&LO) = VL4_8 (value);
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}
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:function:::signed64:SignedMultiply:signed32 l, signed32 r
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{
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signed64 result = (signed64) l * (signed64) r;
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return result;
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}
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:function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
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{
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unsigned64 result = (unsigned64) l * (unsigned64) r;
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return result;
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}
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:function:::unsigned64:Low32Bits:unsigned64 value
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{
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unsigned64 result = (signed64) (signed32) VL4_8 (value);
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return result;
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}
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:function:::unsigned64:High32Bits:unsigned64 value
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{
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unsigned64 result = (signed64) (signed32) VH4_8 (value);
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return result;
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}
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// Multiply and Move LO.
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000000,5.RS,5.RT,5.RD,00001,011000::::MUL
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"mul r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply and Move LO.
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000000,5.RS,5.RT,5.RD,00001,011001::::MULU
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"mulu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Multiply and Move HI.
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000000,5.RS,5.RT,5.RD,01001,011000::::MULHI
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"mulhi r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply and Move HI.
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000000,5.RS,5.RT,5.RD,01001,011001::::MULHIU
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"mulhiu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Multiply, Negate and Move LO.
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000000,5.RS,5.RT,5.RD,00011,011000::::MULS
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"muls r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 - SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply, Negate and Move LO.
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000000,5.RS,5.RT,5.RD,00011,011001::::MULSU
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"mulsu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Multiply, Negate and Move HI.
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000000,5.RS,5.RT,5.RD,01011,011000::::MULSHI
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"mulshi r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 - SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply, Negate and Move HI.
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000000,5.RS,5.RT,5.RD,01011,011001::::MULSHIU
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"mulshiu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Multiply, Accumulate and Move LO.
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000000,5.RS,5.RT,5.RD,00101,011000::::MACC
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"macc r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply, Accumulate and Move LO.
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000000,5.RS,5.RT,5.RD,00101,011001::::MACCU
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"maccu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Multiply, Accumulate and Move HI.
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000000,5.RS,5.RT,5.RD,01101,011000::::MACCHI
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"macchi r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply, Accumulate and Move HI.
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000000,5.RS,5.RT,5.RD,01101,011001::::MACCHIU
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"macchiu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Multiply, Negate, Accumulate and Move LO.
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000000,5.RS,5.RT,5.RD,00111,011000::::MSAC
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"msac r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply, Negate, Accumulate and Move LO.
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000000,5.RS,5.RT,5.RD,00111,011001::::MSACU
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"msacu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Multiply, Negate, Accumulate and Move HI.
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000000,5.RS,5.RT,5.RD,01111,011000::::MSACHI
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"msachi r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply, Negate, Accumulate and Move HI.
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000000,5.RS,5.RT,5.RD,01111,011001::::MSACHIU
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"msachiu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Rotate Right.
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000000,00001,5.RT,5.RD,5.SHIFT,000010::::ROR
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"ror r<RD>, r<RT>, <SHIFT>"
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*vr5400:
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{
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int s = SHIFT;
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GPR[RD] = ROTR32 (GPR[RT], s);
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}
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// Rotate Right Variable.
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000000,5.RS,5.RT,5.RD,00001,000110::::RORV
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"rorv r<RD>, r<RT>, <RS>"
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*vr5400:
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{
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int s = MASKED (GPR[RS], 4, 0);
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GPR[RD] = ROTR32 (GPR[RT], s);
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}
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// Double Rotate Right.
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000000,00001,5.RT,5.RD,5.SHIFT,111010::::DROR
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"dror r<RD>, r<RT>, <SHIFT>"
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*vr5400:
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{
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int s = SHIFT;
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GPR[RD] = ROTR64 (GPR[RT], s);
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}
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// Double Rotate Right Plus 32.
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000000,00001,5.RT,5.RD,5.SHIFT,111110::::DROR32
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"dror32 r<RD>, r<RT>, <SHIFT>"
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*vr5400:
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{
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int s = SHIFT + 32;
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GPR[RD] = ROTR64 (GPR[RT], s);
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}
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// Double Rotate Right Variable.
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000000,5.RS,5.RT,5.RD,00001,010110::::DRORV
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"drorv r<RD>, r<RT>, <RS>"
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*vr5400:
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{
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int s = MASKED (GPR[RS], 5, 0);
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GPR[RD] = ROTR64 (GPR[RT], s);
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}
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