416 lines
13 KiB
Text
416 lines
13 KiB
Text
/* -- asm.c */
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/* Handle shigh(), high(). */
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static const char *
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parse_h_hi16 (strp, opindex, min, max, valuep)
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const char **strp;
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int opindex;
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unsigned long min, max;
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unsigned long *valuep;
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{
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const char *errmsg;
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enum cgen_parse_operand_result result_type;
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/* FIXME: Need # in assembler syntax (means '#' is optional). */
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if (**strp == '#')
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++*strp;
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if (strncmp (*strp, "high(", 5) == 0)
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{
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*strp += 5;
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errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_ULO,
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&result_type, valuep);
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if (**strp != ')')
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return "missing `)'";
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++*strp;
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if (errmsg == NULL
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&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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*valuep >>= 16;
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return errmsg;
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}
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else if (strncmp (*strp, "shigh(", 6) == 0)
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{
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*strp += 6;
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errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_SLO,
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&result_type, valuep);
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if (**strp != ')')
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return "missing `)'";
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++*strp;
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if (errmsg == NULL
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&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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*valuep = (*valuep >> 16) + ((*valuep) & 0x8000 ? 1 : 0);
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return errmsg;
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}
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return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep);
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}
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/* Handle low() in a signed context. Also handle sda().
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The signedness of the value doesn't matter to low(), but this also
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handles the case where low() isn't present. */
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static const char *
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parse_h_slo16 (strp, opindex, min, max, valuep)
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const char **strp;
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int opindex;
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long min, max;
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long *valuep;
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{
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const char *errmsg;
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enum cgen_parse_operand_result result_type;
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/* FIXME: Need # in assembler syntax (means '#' is optional). */
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if (**strp == '#')
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++*strp;
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if (strncmp (*strp, "low(", 4) == 0)
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{
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*strp += 4;
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errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16,
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&result_type, valuep);
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if (**strp != ')')
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return "missing `)'";
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++*strp;
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return errmsg;
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}
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if (strncmp (*strp, "sda(", 4) == 0)
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{
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*strp += 4;
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errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_SDA16, NULL, valuep);
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if (**strp != ')')
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return "missing `)'";
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++*strp;
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return errmsg;
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}
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return cgen_parse_signed_integer (strp, opindex, min, max, valuep);
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}
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/* Handle low() in an unsigned context.
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The signedness of the value doesn't matter to low(), but this also
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handles the case where low() isn't present. */
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static const char *
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parse_h_ulo16 (strp, opindex, min, max, valuep)
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const char **strp;
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int opindex;
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unsigned long min, max;
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unsigned long *valuep;
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{
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const char *errmsg;
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enum cgen_parse_operand_result result_type;
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/* FIXME: Need # in assembler syntax (means '#' is optional). */
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if (**strp == '#')
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++*strp;
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if (strncmp (*strp, "low(", 4) == 0)
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{
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*strp += 4;
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errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16,
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&result_type, valuep);
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if (**strp != ')')
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return "missing `)'";
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++*strp;
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return errmsg;
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}
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return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep);
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}
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/* -- */
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/* Main entry point for operand parsing.
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This function is basically just a big switch statement. Earlier versions
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used tables to look up the function to use, but
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- if the table contains both assembler and disassembler functions then
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the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
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- using a switch statement avoids the function call overhead.
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This function could be moved into `parse_insn_normal', but keeping it
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separate makes clear the interface between `parse_insn_normal' and each of
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the handlers.
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*/
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CGEN_INLINE const char *
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m32r_cgen_parse_operand (opindex, strp, fields)
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int opindex;
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const char **strp;
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CGEN_FIELDS *fields;
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{
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const char *errmsg;
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switch (opindex)
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{
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case M32R_OPERAND_SR :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r2);
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break;
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case M32R_OPERAND_DR :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r1);
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break;
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case M32R_OPERAND_SRC1 :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r1);
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break;
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case M32R_OPERAND_SRC2 :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r2);
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break;
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case M32R_OPERAND_SCR :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, &fields->f_r2);
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break;
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case M32R_OPERAND_DCR :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, &fields->f_r1);
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break;
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case M32R_OPERAND_SIMM8 :
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errmsg = cgen_parse_signed_integer (strp, 7, -128, 127, &fields->f_simm8);
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break;
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case M32R_OPERAND_SIMM16 :
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errmsg = cgen_parse_signed_integer (strp, 8, -32768, 32767, &fields->f_simm16);
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break;
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case M32R_OPERAND_UIMM4 :
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errmsg = cgen_parse_unsigned_integer (strp, 9, 0, 15, &fields->f_uimm4);
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break;
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case M32R_OPERAND_UIMM5 :
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errmsg = cgen_parse_unsigned_integer (strp, 10, 0, 31, &fields->f_uimm5);
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break;
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case M32R_OPERAND_UIMM16 :
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errmsg = cgen_parse_unsigned_integer (strp, 11, 0, 65535, &fields->f_uimm16);
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break;
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case M32R_OPERAND_ACC_S :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_accums, &fields->f_acc_s);
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break;
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case M32R_OPERAND_ACC :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_accums, &fields->f_acc);
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break;
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case M32R_OPERAND_HI16 :
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errmsg = parse_h_hi16 (strp, 14, 0, 65535, &fields->f_hi16);
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break;
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case M32R_OPERAND_SLO16 :
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errmsg = parse_h_slo16 (strp, 15, -32768, 32767, &fields->f_simm16);
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break;
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case M32R_OPERAND_ULO16 :
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errmsg = parse_h_ulo16 (strp, 16, 0, 65535, &fields->f_uimm16);
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break;
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case M32R_OPERAND_UIMM24 :
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errmsg = cgen_parse_address (strp, 17, 0, NULL, &fields->f_uimm24);
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break;
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case M32R_OPERAND_DISP8 :
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errmsg = cgen_parse_address (strp, 18, 0, NULL, &fields->f_disp8);
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break;
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case M32R_OPERAND_DISP16 :
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errmsg = cgen_parse_address (strp, 19, 0, NULL, &fields->f_disp16);
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break;
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case M32R_OPERAND_DISP24 :
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errmsg = cgen_parse_address (strp, 20, 0, NULL, &fields->f_disp24);
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break;
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default :
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fprintf (stderr, "Unrecognized field %d while parsing.\n", opindex);
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abort ();
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}
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return errmsg;
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}
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/* Main entry point for operand insertion.
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This function is basically just a big switch statement. Earlier versions
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used tables to look up the function to use, but
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- if the table contains both assembler and disassembler functions then
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the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
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- using a switch statement avoids the function call overhead.
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This function could be moved into `parse_insn_normal', but keeping it
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separate makes clear the interface between `parse_insn_normal' and each of
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the handlers. It's also needed by GAS to insert operands that couldn't be
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resolved during parsing.
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*/
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CGEN_INLINE void
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m32r_cgen_insert_operand (opindex, fields, buffer)
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int opindex;
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CGEN_FIELDS *fields;
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cgen_insn_t *buffer;
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{
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switch (opindex)
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{
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case M32R_OPERAND_SR :
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insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_DR :
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insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SRC1 :
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insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SRC2 :
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insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SCR :
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insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_DCR :
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insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SIMM8 :
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insert_normal (fields->f_simm8, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SIMM16 :
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insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_UIMM4 :
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insert_normal (fields->f_uimm4, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_UIMM5 :
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insert_normal (fields->f_uimm5, 0|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_UIMM16 :
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insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_ACC_S :
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insert_normal (fields->f_acc_s, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_ACC :
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insert_normal (fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_HI16 :
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insert_normal (fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SLO16 :
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insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_ULO16 :
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insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_UIMM24 :
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insert_normal (fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_DISP8 :
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insert_normal (fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_DISP16 :
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insert_normal (fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_DISP24 :
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insert_normal (fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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default :
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fprintf (stderr, "Unrecognized field %d while building insn.\n",
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opindex);
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abort ();
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}
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}
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/* Main entry point for operand validation.
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This function is called from GAS when it has fully resolved an operand
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that couldn't be resolved during parsing.
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The result is NULL for success or an error message (which may be
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computed into a static buffer).
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*/
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CGEN_INLINE const char *
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m32r_cgen_validate_operand (opindex, fields)
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int opindex;
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const CGEN_FIELDS *fields;
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{
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const char *errmsg = NULL;
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switch (opindex)
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{
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case M32R_OPERAND_SR :
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/* nothing to do */
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break;
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case M32R_OPERAND_DR :
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/* nothing to do */
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break;
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case M32R_OPERAND_SRC1 :
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/* nothing to do */
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break;
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case M32R_OPERAND_SRC2 :
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/* nothing to do */
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break;
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case M32R_OPERAND_SCR :
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/* nothing to do */
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break;
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case M32R_OPERAND_DCR :
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/* nothing to do */
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break;
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case M32R_OPERAND_SIMM8 :
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errmsg = cgen_validate_signed_integer (fields->f_simm8, -128, 127);
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break;
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case M32R_OPERAND_SIMM16 :
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errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767);
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break;
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case M32R_OPERAND_UIMM4 :
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errmsg = cgen_validate_unsigned_integer (fields->f_uimm4, 0, 15);
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break;
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case M32R_OPERAND_UIMM5 :
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errmsg = cgen_validate_unsigned_integer (fields->f_uimm5, 0, 31);
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break;
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case M32R_OPERAND_UIMM16 :
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errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535);
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break;
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case M32R_OPERAND_ACC_S :
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/* nothing to do */
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break;
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case M32R_OPERAND_ACC :
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/* nothing to do */
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break;
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case M32R_OPERAND_HI16 :
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errmsg = cgen_validate_unsigned_integer (fields->f_hi16, 0, 65535);
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break;
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case M32R_OPERAND_SLO16 :
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errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767);
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break;
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case M32R_OPERAND_ULO16 :
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errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535);
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break;
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case M32R_OPERAND_UIMM24 :
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/* nothing to do */
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break;
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case M32R_OPERAND_DISP8 :
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/* nothing to do */
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break;
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case M32R_OPERAND_DISP16 :
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/* nothing to do */
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break;
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case M32R_OPERAND_DISP24 :
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/* nothing to do */
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break;
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default :
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fprintf (stderr, "Unrecognized field %d while validating operand.\n",
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opindex);
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abort ();
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}
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return errmsg;
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}
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cgen_parse_fn *m32r_cgen_parse_handlers[] = {
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0, /* default */
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parse_insn_normal,
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};
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cgen_insert_fn *m32r_cgen_insert_handlers[] = {
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0, /* default */
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insert_insn_normal,
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};
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void
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m32r_cgen_init_asm (mach, endian)
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int mach;
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enum cgen_endian endian;
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{
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m32r_cgen_init_tables (mach);
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cgen_set_cpu (& m32r_cgen_opcode_data, mach, endian);
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cgen_asm_init ();
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}
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