446 lines
13 KiB
C
446 lines
13 KiB
C
/* Engine header for Cpu tools GENerated simulators.
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Copyright (C) 1998, 1999, 2007, 2008, 2009 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This file is included by ${cpu}.h.
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It needs CGEN_INSN_WORD which is defined by ${cpu}.h.
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??? A lot of this could be moved to genmloop.sh to be put in eng.h
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and thus remove some conditional compilation. We'd still need
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CGEN_INSN_WORD though. */
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/* Semantic functions come in six versions on two axes:
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fast/full-featured, and using one of the simple/scache/compilation engines.
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A full featured simulator is always provided. --enable-sim-fast includes
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support for fast execution by duplicating the semantic code but leaving
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out all features like tracing and profiling.
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Using the scache is selected with --enable-sim-scache. */
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/* FIXME: --enable-sim-fast not implemented yet. */
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/* FIXME: undecided how to handle WITH_SCACHE_PBB. */
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/* There are several styles of engines, all generally supported by the
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same code:
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WITH_SCACHE && WITH_SCACHE_PBB - pseudo-basic-block scaching
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WITH_SCACHE && !WITH_SCACHE_PBB - scaching on an insn by insn basis
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!WITH_SCACHE - simple engine: fetch an insn, execute an insn
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The !WITH_SCACHE case can also be broken up into two flavours:
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extract the fields of the insn into an ARGBUF struct, or defer the
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extraction to the semantic handler. The former can be viewed as the
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WITH_SCACHE case with a cache size of 1 (thus there's no need for a
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WITH_EXTRACTION macro). The WITH_SCACHE case always extracts the fields
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into an ARGBUF struct. */
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#ifndef CGEN_ENGINE_H
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#define CGEN_ENGINE_H
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/* Instruction field support macros. */
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#define EXTRACT_MSB0_SINT(val, total, start, length) \
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(((INT) (val) << ((sizeof (INT) * 8) - (total) + (start))) \
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>> ((sizeof (INT) * 8) - (length)))
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#define EXTRACT_MSB0_UINT(val, total, start, length) \
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(((UINT) (val) << ((sizeof (UINT) * 8) - (total) + (start))) \
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>> ((sizeof (UINT) * 8) - (length)))
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#define EXTRACT_LSB0_SINT(val, total, start, length) \
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(((INT) (val) << ((sizeof (INT) * 8) - (start) - 1)) \
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>> ((sizeof (INT) * 8) - (length)))
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#define EXTRACT_LSB0_UINT(val, total, start, length) \
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(((UINT) (val) << ((sizeof (UINT) * 8) - (start) - 1)) \
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>> ((sizeof (UINT) * 8) - (length)))
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#define EXTRACT_MSB0_LGSINT(val, total, start, length) \
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(((CGEN_INSN_LGSINT) (val) << ((sizeof (CGEN_INSN_LGSINT) * 8) - (total) + (start))) \
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>> ((sizeof (CGEN_INSN_LGSINT) * 8) - (length)))
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#define EXTRACT_MSB0_LGUINT(val, total, start, length) \
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(((CGEN_INSN_UINT) (val) << ((sizeof (CGEN_INSN_LGUINT) * 8) - (total) + (start))) \
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>> ((sizeof (CGEN_INSN_LGUINT) * 8) - (length)))
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#define EXTRACT_LSB0_LGSINT(val, total, start, length) \
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(((CGEN_INSN_LGSINT) (val) << ((sizeof (CGEN_INSN_LGSINT) * 8) - (start) - 1)) \
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>> ((sizeof (CGEN_INSN_LGSINT) * 8) - (length)))
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#define EXTRACT_LSB0_LGUINT(val, total, start, length) \
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(((CGEN_INSN_LGUINT) (val) << ((sizeof (CGEN_INSN_LGUINT) * 8) - (start) - 1)) \
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>> ((sizeof (CGEN_INSN_LGUINT) * 8) - (length)))
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/* Semantic routines. */
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/* Type of the machine generated extraction fns. */
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/* ??? No longer used. */
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typedef void (EXTRACT_FN) (SIM_CPU *, IADDR, CGEN_INSN_WORD, ARGBUF *);
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/* Type of the machine generated semantic fns. */
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#if WITH_SCACHE
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/* Instruction fields are extracted into ARGBUF before calling the
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semantic routine. */
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#if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_GENWRITE
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typedef SEM_PC (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, PAREXEC *);
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#else
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typedef SEM_PC (SEMANTIC_FN) (SIM_CPU *, SEM_ARG);
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#endif
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#else
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/* Result of semantic routines is a status indicator (wip). */
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typedef unsigned int SEM_STATUS;
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/* Instruction fields are extracted by the semantic routine.
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??? TODO: multi word insns. */
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#if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_GENWRITE
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typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, PAREXEC *, CGEN_INSN_WORD);
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#else
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typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, CGEN_INSN_WORD);
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#endif
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#endif
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/* In the ARGBUF struct, a pointer to the semantic routine for the insn. */
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union sem {
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#if ! WITH_SEM_SWITCH_FULL
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SEMANTIC_FN *sem_full;
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#endif
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#if ! WITH_SEM_SWITCH_FAST
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SEMANTIC_FN *sem_fast;
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#endif
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#if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
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#ifdef __GNUC__
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void *sem_case;
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#else
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int sem_case;
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#endif
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#endif
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};
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/* Set the appropriate semantic handler in ABUF. */
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#if WITH_SEM_SWITCH_FULL
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#ifdef __GNUC__
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#define SEM_SET_FULL_CODE(abuf, idesc) \
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do { (abuf)->semantic.sem_case = (idesc)->sem_full_lab; } while (0)
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#else
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#define SEM_SET_FULL_CODE(abuf, idesc) \
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do { (abuf)->semantic.sem_case = (idesc)->num; } while (0)
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#endif
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#else
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#define SEM_SET_FULL_CODE(abuf, idesc) \
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do { (abuf)->semantic.sem_full = (idesc)->sem_full; } while (0)
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#endif
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#if WITH_SEM_SWITCH_FAST
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#ifdef __GNUC__
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#define SEM_SET_FAST_CODE(abuf, idesc) \
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do { (abuf)->semantic.sem_case = (idesc)->sem_fast_lab; } while (0)
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#else
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#define SEM_SET_FAST_CODE(abuf, idesc) \
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do { (abuf)->semantic.sem_case = (idesc)->num; } while (0)
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#endif
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#else
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#define SEM_SET_FAST_CODE(abuf, idesc) \
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do { (abuf)->semantic.sem_fast = (idesc)->sem_fast; } while (0)
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#endif
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#define SEM_SET_CODE(abuf, idesc, fast_p) \
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do { \
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if (fast_p) \
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SEM_SET_FAST_CODE ((abuf), (idesc)); \
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else \
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SEM_SET_FULL_CODE ((abuf), (idesc)); \
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} while (0)
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/* Return non-zero if IDESC is a conditional or unconditional CTI. */
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#define IDESC_CTI_P(idesc) \
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((CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) \
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& (CGEN_ATTR_MASK (CGEN_INSN_COND_CTI) \
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| CGEN_ATTR_MASK (CGEN_INSN_UNCOND_CTI))) \
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!= 0)
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/* Return non-zero if IDESC is a skip insn. */
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#define IDESC_SKIP_P(idesc) \
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((CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) \
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& CGEN_ATTR_MASK (CGEN_INSN_SKIP_CTI)) \
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!= 0)
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/* Return pointer to ARGBUF given ptr to SCACHE. */
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#define SEM_ARGBUF(sem_arg) (& (sem_arg) -> argbuf)
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/* There are several styles of engines, all generally supported by the
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same code:
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WITH_SCACHE && WITH_SCACHE_PBB - pseudo-basic-block scaching
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WITH_SCACHE && !WITH_SCACHE_PBB - scaching on an insn by insn basis
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!WITH_SCACHE - simple engine: fetch an insn, execute an insn
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??? The !WITH_SCACHE case can also be broken up into two flavours:
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extract the fields of the insn into an ARGBUF struct, or defer the
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extraction to the semantic handler. The WITH_SCACHE case always
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extracts the fields into an ARGBUF struct. */
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#if WITH_SCACHE
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#define CIA_ADDR(cia) (cia)
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#if WITH_SCACHE_PBB
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/* Return the scache pointer of the current insn. */
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#define SEM_SEM_ARG(vpc, sc) (vpc)
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/* Return the virtual pc of the next insn to execute
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(assuming this isn't a cti or the branch isn't taken). */
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#define SEM_NEXT_VPC(sem_arg, pc, len) ((sem_arg) + 1)
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/* Update the instruction counter. */
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#define PBB_UPDATE_INSN_COUNT(cpu,sc) \
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(CPU_INSN_COUNT (cpu) += SEM_ARGBUF (sc) -> fields.chain.insn_count)
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/* Do not append a `;' to invocations of this.
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npc,br_type are for communication between the cti insn and cti-chain. */
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#define SEM_BRANCH_INIT \
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IADDR npc = 0; /* assign a value for -Wall */ \
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SEM_BRANCH_TYPE br_type = SEM_BRANCH_UNTAKEN;
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/* SEM_IN_SWITCH is defined at the top of the mainloop.c files
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generated by genmloop.sh. It exists so generated semantic code needn't
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care whether it's being put in a switch or in a function. */
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#ifdef SEM_IN_SWITCH
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#define SEM_BRANCH_FINI(pcvar) \
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do { \
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pbb_br_npc = npc; \
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pbb_br_type = br_type; \
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} while (0)
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#else /* 1 semantic function per instruction */
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#define SEM_BRANCH_FINI(pcvar) \
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do { \
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CPU_PBB_BR_NPC (current_cpu) = npc; \
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CPU_PBB_BR_TYPE (current_cpu) = br_type; \
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} while (0)
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#endif
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#define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar) \
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do { \
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npc = (newval); \
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br_type = SEM_BRANCH_CACHEABLE; \
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} while (0)
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#define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \
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do { \
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npc = (newval); \
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br_type = SEM_BRANCH_UNCACHEABLE; \
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} while (0)
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#define SEM_SKIP_COMPILE(cpu, sc, skip) \
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do { \
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SEM_ARGBUF (sc) -> skip_count = (skip); \
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} while (0)
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#define SEM_SKIP_INSN(cpu, sc, vpcvar) \
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do { \
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(vpcvar) += SEM_ARGBUF (sc) -> skip_count; \
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} while (0)
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#else /* ! WITH_SCACHE_PBB */
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#define SEM_SEM_ARG(vpc, sc) (sc)
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#define SEM_NEXT_VPC(sem_arg, pc, len) ((pc) + (len))
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/* ??? May wish to move taken_p out of here and make it explicit. */
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#define SEM_BRANCH_INIT \
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int taken_p = 0;
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#ifndef TARGET_SEM_BRANCH_FINI
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#define TARGET_SEM_BRANCH_FINI(pcvar, taken_p)
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#endif
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#define SEM_BRANCH_FINI(pcvar) \
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do { TARGET_SEM_BRANCH_FINI (pcvar, taken_p); } while (0)
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#define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar) \
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do { \
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(pcvar) = (newval); \
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taken_p = 1; \
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} while (0)
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#define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \
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do { \
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(pcvar) = (newval); \
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taken_p = 1; \
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} while (0)
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#endif /* ! WITH_SCACHE_PBB */
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#else /* ! WITH_SCACHE */
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/* This is the "simple" engine case. */
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#define CIA_ADDR(cia) (cia)
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#define SEM_SEM_ARG(vpc, sc) (sc)
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#define SEM_NEXT_VPC(sem_arg, pc, len) ((pc) + (len))
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#define SEM_BRANCH_INIT \
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int taken_p = 0;
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#define SEM_BRANCH_VIA_CACHE(cpu, abuf, newval, pcvar) \
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do { \
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(pcvar) = (newval); \
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taken_p = 1; \
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} while (0)
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#define SEM_BRANCH_VIA_ADDR(cpu, abuf, newval, pcvar) \
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do { \
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(pcvar) = (newval); \
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taken_p = 1; \
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} while (0)
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/* Finish off branch insns.
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The target must define TARGET_SEM_BRANCH_FINI.
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??? This can probably go away when define-execute is finished. */
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#define SEM_BRANCH_FINI(pcvar, bool_attrs) \
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do { TARGET_SEM_BRANCH_FINI ((pcvar), (bool_attrs), taken_p); } while (0)
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/* Finish off non-branch insns.
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The target must define TARGET_SEM_NBRANCH_FINI.
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??? This can probably go away when define-execute is finished. */
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#define SEM_NBRANCH_FINI(pcvar, bool_attrs) \
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do { TARGET_SEM_NBRANCH_FINI ((pcvar), (bool_attrs)); } while (0)
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#endif /* ! WITH_SCACHE */
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/* Instruction information. */
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/* Sanity check, at most one of these may be true. */
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#if WITH_PARALLEL_READ + WITH_PARALLEL_WRITE + WITH_PARALLEL_GENWRITE > 1
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#error "At most one of WITH_PARALLEL_{READ,WRITE,GENWRITE} can be true."
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#endif
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/* Compile time computable instruction data. */
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struct insn_sem {
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/* The instruction type (a number that identifies each insn over the
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entire architecture). */
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CGEN_INSN_TYPE type;
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/* Index in IDESC table. */
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int index;
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/* Semantic format number. */
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int sfmt;
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#if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_ONLY
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/* Index in IDESC table of parallel handler. */
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int par_index;
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#endif
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#if WITH_PARALLEL_READ
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/* Index in IDESC table of read handler. */
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int read_index;
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#endif
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#if WITH_PARALLEL_WRITE
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/* Index in IDESC table of writeback handler. */
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int write_index;
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#endif
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};
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/* Entry in semantic function table.
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This information is copied to the insn descriptor table at run-time. */
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struct sem_fn_desc {
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/* Index in IDESC table. */
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int index;
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/* Function to perform the semantics of the insn. */
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SEMANTIC_FN *fn;
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};
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/* Run-time computed instruction descriptor. */
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struct idesc {
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#if WITH_SEM_SWITCH_FAST
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#ifdef __GNUC__
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void *sem_fast_lab;
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#else
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/* nothing needed, switch's on `num' member */
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#endif
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#else
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SEMANTIC_FN *sem_fast;
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#endif
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#if WITH_SEM_SWITCH_FULL
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#ifdef __GNUC__
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void *sem_full_lab;
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#else
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/* nothing needed, switch's on `num' member */
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#endif
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#else
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SEMANTIC_FN *sem_full;
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#endif
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/* Parallel support. */
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#if HAVE_PARALLEL_INSNS && (! WITH_PARALLEL_ONLY || (WITH_PARALLEL_ONLY && ! WITH_PARALLEL_GENWRITE))
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/* Pointer to parallel handler if serial insn.
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Pointer to readahead/writeback handler if parallel insn. */
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struct idesc *par_idesc;
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#endif
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/* Instruction number (index in IDESC table, profile table).
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Also used to switch on in non-gcc semantic switches. */
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int num;
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/* Semantic format id. */
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int sfmt;
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/* instruction data (name, attributes, size, etc.) */
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const CGEN_INSN *idata;
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/* instruction attributes, copied from `idata' for speed */
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const CGEN_INSN_ATTR_TYPE *attrs;
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/* instruction length in bytes, copied from `idata' for speed */
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int length;
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/* profiling/modelling support */
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const INSN_TIMING *timing;
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};
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/* Tracing/profiling. */
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/* Return non-zero if a before/after handler is needed.
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When tracing/profiling a selected range there's no need to slow
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down simulation of the other insns (except to get more accurate data!).
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??? May wish to profile all insns if doing insn tracing, or to
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get more accurate cycle data.
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First test ANY_P so we avoid a potentially expensive HIT_P call
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[if there are lots of address ranges]. */
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#define PC_IN_TRACE_RANGE_P(cpu, pc) \
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(TRACE_ANY_P (cpu) \
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&& ADDR_RANGE_HIT_P (TRACE_RANGE (CPU_TRACE_DATA (cpu)), (pc)))
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#define PC_IN_PROFILE_RANGE_P(cpu, pc) \
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(PROFILE_ANY_P (cpu) \
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&& ADDR_RANGE_HIT_P (PROFILE_RANGE (CPU_PROFILE_DATA (cpu)), (pc)))
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#endif /* CGEN_ENGINE_H */
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