245 lines
9 KiB
Text
245 lines
9 KiB
Text
Thu Oct 24 12:26:35 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c (OP_500): Fix displacement handling for sld.w.
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(OP_501): Similarly for sst.w.
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* simops.c (trace_input): Remove all references to SEXT7.
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(OP_300, OP_400, OP_500, OP_380, OP_480, OP_501): Displacement
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is zero extended for sst/sld instructions.
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* v850_sim.h (SEX7): Delete. It's no longer needed (and it
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was incorrect anyway).
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Thu Oct 24 10:33:33 1996 Stu Grossman (grossman@critters.cygnus.com)
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* Makefile.in: Get rid of srcroot. Set all INSTALL macros via
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autoconf.
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* gencode.c (write_opcodes): Pad operands field to account for
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MSVC braindamage.
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* simops.c: Include errno.h. Exclude SYS_chown, since MSVC
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doesn't support it. (Why is this here in the first place?!?)
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* v850_sim.h: Get rid of 64 bit defs. Also, get rid of #elif's.
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Change number of operands in struct simops from 9 to 6. Define
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SIGTRAP and SIGQUIT for MSVC.
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Tue Oct 15 16:19:51 1996 Stu Grossman (grossman@critters.cygnus.com)
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* interp.c (MEM_SIZE): It's now bytes, not a power of 2.
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* (map): Add support for external mem in the 1->2 meg range.
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Also, abort() when memory access is way out of bounds. (Better to
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die than to give wrong result. (This will be fixed later.))
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* (sim_size): MEM_SIZE is now bytes, not shift factor.
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Tue Oct 1 15:53:24 1996 Gavin Koch <gavin@cygnus.com>
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* simops.c (trace_input): Swapped order of operands for output
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output of OP_IMM_REG. Changed the fetching of the operands for
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OP_LOAD32, and OP_STORE32 to work like op-function.
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Mon Sep 30 15:46:33 1996 Stu Grossman (grossman@critters.cygnus.com)
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* interp.c: Move includes of remote-sim.h and callback.h to
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v850-sim.h.
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* (lookup_hash): Add PC to report of hash failure.
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* (map load_mem store_mem): New memory subsystem. Models V851
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memory system.
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* (sim_write sim_read): Use new memory subsystem.
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* (sim_resume): Don't load and save PC into EIPC anymore. Needed
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to make user-defined traps work right.
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* simops.c (OP_*): Use new memory subsystem.
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* (OP_14007E0 (reti)): Implement reti.
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* (OP_14996E0 (trap)): Implement user-defined traps. Move I/O to
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trap 31. Use new memory subsystem.
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* v850_sim.h: Prototypes for load_mem, store_mem and map. Use
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load_mem in RLW macro.
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Fri Sep 27 18:34:09 1996 Stu Grossman (grossman@critters.cygnus.com)
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* gencode.c (write_opcodes): Output hex values for opcode mask
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and patterns.
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* interp.c (sim_resume): Save and restore PC from the appropriate
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register.
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* (sim_fetch_register sim_store_register): Fix byte-order problem
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with reading and writing registers.
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* simops.c (OP_FFFF): Implement pseudo-breakpoint insn.
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Fri Sep 27 17:42:37 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c (trace_input): Fix thinko.
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Wed Sep 18 09:54:12 1996 Michael Meissner <meissner@tiktok.cygnus.com>
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* simops.c (exec_bfd): Rename from sim_bfd.
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(trace_input): Ditto.
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Thu Sep 12 12:03:05 1996 Michael Meissner <meissner@tiktok.cygnus.com>
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* simops.c (trace_input): Use find_nearest_line to print line
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number, function name or file name of PC.
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Wed Sep 11 16:44:37 1996 Michael Meissner <meissner@tiktok.cygnus.com>
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* simops.c: Add tracing support. Use SEXTxx macros instead of
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doing hardwired shifts.
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* configure.in (--enable-sim-cflags): Add switch to add additional
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flags to simulator buld. If --enable-sim-cflags=trace, turn on
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tracing.
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* configure: Regenerate.
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* Makefile.in: Don't require a VPATH capable make if configuring
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in the same directory. Don't use CFLAGS for configuration flags.
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Add flags from --enable-sim-cflags. Support canadian cross
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builds. Rebuild whole simulator if include files change.
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* interp.c (v850_debug): New global for debugging.
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(lookup_hash,sim_size,sim_set_profile): Use
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printf_filtered callback, instead of calling printf directly.
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(sim_{open,trace}): Enable tracing if -t and compiled for tracing.
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* v850_sim.h: Use limits.h to set the various sized types.
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(SEXT{5,7,16,22}): New macros.
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Mon Sep 9 20:50:46 1996 Jeffrey A Law (law@cygnus.com)
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* interp.c (hash): Make this an inline function
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when compiling with GCC. Simplify.
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* simpos.c: Explicitly include "sys/syscall.h". Remove
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some #if 0'd code. Enable more emulated syscalls.
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Wed Sep 4 01:48:55 1996 Jeffrey A Law (law@cygnus.com)
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* interp.c: Fix sign bit handling for add and sub instructions.
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Tue Sep 3 10:20:30 1996 Jeffrey A Law (law@cygnus.com)
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* gencode.c: Fix various indention & style problems.
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Remove test code. Remove #if 0 code.
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* interp.c: Provide prototypes for all static functions.
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Fix minor indention problems.
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(sim_open, sim_resume): Remove unused variables.
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(sim_read): Return type is "int".
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* simops.c: Remove unused variables.
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(divh): Make result of divide-by-zero zero.
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(setf): Initialize result to keep compiler quiet.
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(sar instructions): These just clear the overflow bit.
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* v850_sim.h: Provide prototypes for put_byte, put_half
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and put_word.
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* interp.c: OP should be an array of 32bit operands!
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(v850_callback): Declare.
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(do_format_5): Fix extraction of OP[0].
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(sim_size): Remove debugging printf.
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(sim_set_callbacks): Do something useful.
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(sim_stop_reason): Gross hacks to get c-torture running.
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* simops.c: Simplify code for computing targets of bCC
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insns. Invert 's' bit if 'ov' bit is set for some
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instructions. Fix 'cy' bit handling for numerous
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instructions. Make the simulator stop when a halt
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instruction is encountered. Very crude support for
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emulated syscalls (trap 0).
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* v850_sim.h: Include "callback.h" and declare
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v850_callback. Items in the operand array are 32bits.
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Sun Sep 1 22:35:35 1996 Jeffrey A Law (law@cygnus.com)
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* interp.c (sim_resume): Fix code to check for a format 3
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opcode.
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* simops.c: bCC insns only argument is a constant, not a
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register value (duh...)
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Fri Aug 30 10:33:49 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: Fix "not1" and "set1".
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* simops.c: Don't forget to initialize temp for
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"ld.h" and "ld.w"
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* interp.c: Remove various debugging printfs.
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* simops.c: Fix satadd, satsub boundary case handling.
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* interp.c (hash): Fix.
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* interp.c (do_format_8): Get operands correctly and
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call the target function.
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* simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
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Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com)
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* interp.c (do_format_4): Get operands correctly and
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call the target function.
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* simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
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"sst.h", and "sst.w".
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* v850_sim.h: The V850 doesn't have split I&D spaces. Change
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accordingly. Remove many unused definitions.
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* interp.c: The V850 doesn't have split I&D spaces. Change
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accordingly.
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(get_longlong, get_longword, get_word): Deleted.
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(write_longlong, write_longword, write_word): Deleted.
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(get_operands): Deleted.
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(get_byte, get_half, get_word): New functions.
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(put_byte, put_half, put_word): New functions.
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* simops.c: Remove unused functions. Rough cut at
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"ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
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* v850_sim.h (struct _state): Remove "psw" field. Add
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"sregs" field.
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(PSW): Remove bogus definition.
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* simops.c: Change condition code handling to use the psw
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register within the sregs array. Handle "ldsr" and "stsr".
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* simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
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* interp.c (do_format_5): Get operands correctly and
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call the target function.
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(sim_resume): Don't do a PC update for format 5 instructions.
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* simops.c: Handle "jarl" and "jmp" instructions.
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* simops.c: Fix minor typos. Handle "cmp", "setf", "tst"
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"di", and "ei" instructions correctly.
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* interp.c (do_format_3): Get operands correctly and call
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the target function.
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* simops.c: Handle bCC instructions.
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* simops.c: Add condition code handling to shift insns.
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Fix minor typos in condition code handling for other insns.
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* Makefile.in: Fix typo.
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* simops.c: Add condition code handling to "sub" "subr" and
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"divh" instructions.
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* interp.c (hash): Update to be more accurate.
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(lookup_hash): Call hash rather than computing the hash
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code here.
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(do_format_1_2): Handle format 1 and format 2 instructions.
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Get operands correctly and call the target function.
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(do_format_6): Get operands correctly and call the target
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function.
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(do_formats_9_10): Rough cut so shift ops will work.
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(sim_resume): Tweak to deal with format 1 and format 2
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handling in a single funtion. Don't update the PC
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for format 3 insns. Fix typos.
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* simops.c: Slightly reorganize. Add condition code handling
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to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
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and "not" instructions.
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* v850_sim.h (reg_t): Registers are 32bits.
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(_state): The V850 has 32 general registers. Add a 32bit
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psw and pc register too. Add accessor macros
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* Makefile.in, interp.c, v850_sim.h: Bring over endianness
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changes from the d10v simulator.
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* simops.c: Add shift support.
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* simops.c: Add multiply & divide support. Abort for system
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instructions.
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* simops.c: Add logicals, mov, movhi, movea, add, addi, sub
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and subr. No condition codes yet.
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Wed Aug 28 13:53:22 1996 Jeffrey A Law (law@cygnus.com)
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* ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
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gencode.c, interp.c, simops.c: Created.
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