old-cross-binutils/opcodes
Ian Lance Taylor 547998d2c8 * mips-opc.c: Change div machine instruction to be z,s,t rather
than s,t.  Change div macro to be d,v,t rather than d,s,t.
	Likewise for divu, ddiv, ddivu.  Added z,s,t case for drem, dremu,
	rem and remu which generates only the corresponding div
	instruction.  This is for compatibility with the MIPS assembler,
	which only generates the simple machine instruction when an
	explicit destination of $0 is used.
	* mips-dis.c (print_insn_arg): Handle 'z' (always register zero).
1993-09-02 17:14:10 +00:00
..
.Sanitize Remove '.Sanitize' from explicit list of Things-to-lose. It is now implicitly 1993-08-02 23:29:32 +00:00
a29k-dis.c
alpha-opc.h
ChangeLog * mips-opc.c: Change div machine instruction to be z,s,t rather 1993-09-02 17:14:10 +00:00
configure.in
dis-buf.c
h8300-dis.c
h8500-dis.c
h8500-opc.h
hppa-dis.c * hppa-dis.c: Move floating registers from reg_names to fp_reg_names. 1993-07-21 18:54:49 +00:00
i386-dis.c
m68k-dis.c
m88k-dis.c
m68881-ext.c
Makefile.in
mips-dis.c * mips-opc.c: Change div machine instruction to be z,s,t rather 1993-09-02 17:14:10 +00:00
mips-opc.c * mips-opc.c: Change div machine instruction to be z,s,t rather 1993-09-02 17:14:10 +00:00
sparc-dis.c
sparc-opc.c Rename sigm insn to sir. 1993-08-04 05:12:50 +00:00
z8k-dis.c
z8k-opc.h
z8kgen.c