b11dcf4e7f
* cgen-asm.in (@arch@_cgen_assemble_insn): CGEN_INSN_RELAX renamed to CGEN_INSN_RELAXED. * fr30-asm.c,fr30-desc.c,fr30-desc.h: Regenerate. * frv-asm.c,frv-desc.c,frv-desc.h: Regenerate. * ip2k-asm.c,ip2k-desc.c,ip2k-desc.h: Regenerate. * iq2000-asm.c,iq2000-desc.c,iq2000-desc.h: Regenerate. * m32r-asm.c,m32r-desc.c,m32r-desc.h,m32r-opc.c: Regenerate. * openrisc-asm.c,openrisc-desc.c,openrisc-desc.h: Regenerate. * xstormy16-asm.c,xstormy16-desc.c,xstormy16-desc.h: Regenerate. gas: * cgen.c (gas_cgen_finish_insn): CGEN_INSN_RELAX renamed to CGEN_INSN_RELAXED. * config/tc-fr30.c (md_estimate_size_before_relax): Ditto. * config/tc-m32r.c (md_estimate_size_before_relax): Ditto. * config/tc-openrisc.c (md_estimate_size_before_relax): Ditto.
251 lines
9.9 KiB
C
251 lines
9.9 KiB
C
/* CPU data header for ip2k.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef IP2K_CPU_H
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#define IP2K_CPU_H
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#define CGEN_ARCH ip2k
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/* Given symbol S, return ip2k_cgen_<S>. */
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#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
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#define CGEN_SYM(s) ip2k##_cgen_##s
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#else
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#define CGEN_SYM(s) ip2k/**/_cgen_/**/s
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#endif
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/* Selected cpu families. */
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#define HAVE_CPU_IP2KBF
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#define CGEN_INSN_LSB0_P 1
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/* Minimum size of any insn (in bytes). */
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#define CGEN_MIN_INSN_SIZE 2
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/* Maximum size of any insn (in bytes). */
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#define CGEN_MAX_INSN_SIZE 2
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#define CGEN_INT_INSN_P 1
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/* Maximum number of syntax elements in an instruction. */
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#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 12
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/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
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e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
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we can't hash on everything up to the space. */
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#define CGEN_MNEMONIC_OPERANDS
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/* Maximum number of fields in an instruction. */
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#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 3
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/* Enums. */
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/* Enum declaration for op6 enums. */
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typedef enum insn_op6 {
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OP6_OTHER1, OP6_OTHER2, OP6_SUB, OP6_DEC
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, OP6_OR, OP6_AND, OP6_XOR, OP6_ADD
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, OP6_TEST, OP6_NOT, OP6_INC, OP6_DECSZ
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, OP6_RR, OP6_RL, OP6_SWAP, OP6_INCSZ
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, OP6_CSE, OP6_POP, OP6_SUBC, OP6_DECSNZ
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, OP6_MULU, OP6_MULS, OP6_INCSNZ, OP6_ADDC
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} INSN_OP6;
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/* Enum declaration for dir enums. */
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typedef enum insn_dir {
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DIR_TO_W, DIR_NOTTO_W
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} INSN_DIR;
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/* Enum declaration for op4 enums. */
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typedef enum insn_op4 {
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OP4_LITERAL = 7, OP4_CLRB = 8, OP4_SETB = 9, OP4_SNB = 10
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, OP4_SB = 11
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} INSN_OP4;
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/* Enum declaration for op4mid enums. */
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typedef enum insn_op4mid {
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OP4MID_LOADH_L = 0, OP4MID_LOADL_L = 1, OP4MID_MULU_L = 2, OP4MID_MULS_L = 3
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, OP4MID_PUSH_L = 4, OP4MID_CSNE_L = 6, OP4MID_CSE_L = 7, OP4MID_RETW_L = 8
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, OP4MID_CMP_L = 9, OP4MID_SUB_L = 10, OP4MID_ADD_L = 11, OP4MID_MOV_L = 12
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, OP4MID_OR_L = 13, OP4MID_AND_L = 14, OP4MID_XOR_L = 15
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} INSN_OP4MID;
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/* Enum declaration for op3 enums. */
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typedef enum insn_op3 {
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OP3_CALL = 6, OP3_JMP = 7
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} INSN_OP3;
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/* Enum declaration for . */
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typedef enum register_names {
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H_REGISTERS_ADDRSEL = 2, H_REGISTERS_ADDRX = 3, H_REGISTERS_IPH = 4, H_REGISTERS_IPL = 5
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, H_REGISTERS_SPH = 6, H_REGISTERS_SPL = 7, H_REGISTERS_PCH = 8, H_REGISTERS_PCL = 9
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, H_REGISTERS_WREG = 10, H_REGISTERS_STATUS = 11, H_REGISTERS_DPH = 12, H_REGISTERS_DPL = 13
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, H_REGISTERS_SPDREG = 14, H_REGISTERS_MULH = 15, H_REGISTERS_ADDRH = 16, H_REGISTERS_ADDRL = 17
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, H_REGISTERS_DATAH = 18, H_REGISTERS_DATAL = 19, H_REGISTERS_INTVECH = 20, H_REGISTERS_INTVECL = 21
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, H_REGISTERS_INTSPD = 22, H_REGISTERS_INTF = 23, H_REGISTERS_INTE = 24, H_REGISTERS_INTED = 25
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, H_REGISTERS_FCFG = 26, H_REGISTERS_TCTRL = 27, H_REGISTERS_XCFG = 28, H_REGISTERS_EMCFG = 29
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, H_REGISTERS_IPCH = 30, H_REGISTERS_IPCL = 31, H_REGISTERS_RAIN = 32, H_REGISTERS_RAOUT = 33
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, H_REGISTERS_RADIR = 34, H_REGISTERS_LFSRH = 35, H_REGISTERS_RBIN = 36, H_REGISTERS_RBOUT = 37
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, H_REGISTERS_RBDIR = 38, H_REGISTERS_LFSRL = 39, H_REGISTERS_RCIN = 40, H_REGISTERS_RCOUT = 41
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, H_REGISTERS_RCDIR = 42, H_REGISTERS_LFSRA = 43, H_REGISTERS_RDIN = 44, H_REGISTERS_RDOUT = 45
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, H_REGISTERS_RDDIR = 46, H_REGISTERS_REIN = 48, H_REGISTERS_REOUT = 49, H_REGISTERS_REDIR = 50
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, H_REGISTERS_RFIN = 52, H_REGISTERS_RFOUT = 53, H_REGISTERS_RFDIR = 54, H_REGISTERS_RGOUT = 57
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, H_REGISTERS_RGDIR = 58, H_REGISTERS_RTTMR = 64, H_REGISTERS_RTCFG = 65, H_REGISTERS_T0TMR = 66
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, H_REGISTERS_T0CFG = 67, H_REGISTERS_T1CNTH = 68, H_REGISTERS_T1CNTL = 69, H_REGISTERS_T1CAP1H = 70
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, H_REGISTERS_T1CAP1L = 71, H_REGISTERS_T1CAP2H = 72, H_REGISTERS_T1CMP2H = 72, H_REGISTERS_T1CAP2L = 73
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, H_REGISTERS_T1CMP2L = 73, H_REGISTERS_T1CMP1H = 74, H_REGISTERS_T1CMP1L = 75, H_REGISTERS_T1CFG1H = 76
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, H_REGISTERS_T1CFG1L = 77, H_REGISTERS_T1CFG2H = 78, H_REGISTERS_T1CFG2L = 79, H_REGISTERS_ADCH = 80
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, H_REGISTERS_ADCL = 81, H_REGISTERS_ADCCFG = 82, H_REGISTERS_ADCTMR = 83, H_REGISTERS_T2CNTH = 84
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, H_REGISTERS_T2CNTL = 85, H_REGISTERS_T2CAP1H = 86, H_REGISTERS_T2CAP1L = 87, H_REGISTERS_T2CAP2H = 88
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, H_REGISTERS_T2CMP2H = 88, H_REGISTERS_T2CAP2L = 89, H_REGISTERS_T2CMP2L = 89, H_REGISTERS_T2CMP1H = 90
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, H_REGISTERS_T2CMP1L = 91, H_REGISTERS_T2CFG1H = 92, H_REGISTERS_T2CFG1L = 93, H_REGISTERS_T2CFG2H = 94
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, H_REGISTERS_T2CFG2L = 95, H_REGISTERS_S1TMRH = 96, H_REGISTERS_S1TMRL = 97, H_REGISTERS_S1TBUFH = 98
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, H_REGISTERS_S1TBUFL = 99, H_REGISTERS_S1TCFG = 100, H_REGISTERS_S1RCNT = 101, H_REGISTERS_S1RBUFH = 102
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, H_REGISTERS_S1RBUFL = 103, H_REGISTERS_S1RCFG = 104, H_REGISTERS_S1RSYNC = 105, H_REGISTERS_S1INTF = 106
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, H_REGISTERS_S1INTE = 107, H_REGISTERS_S1MODE = 108, H_REGISTERS_S1SMASK = 109, H_REGISTERS_PSPCFG = 110
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, H_REGISTERS_CMPCFG = 111, H_REGISTERS_S2TMRH = 112, H_REGISTERS_S2TMRL = 113, H_REGISTERS_S2TBUFH = 114
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, H_REGISTERS_S2TBUFL = 115, H_REGISTERS_S2TCFG = 116, H_REGISTERS_S2RCNT = 117, H_REGISTERS_S2RBUFH = 118
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, H_REGISTERS_S2RBUFL = 119, H_REGISTERS_S2RCFG = 120, H_REGISTERS_S2RSYNC = 121, H_REGISTERS_S2INTF = 122
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, H_REGISTERS_S2INTE = 123, H_REGISTERS_S2MODE = 124, H_REGISTERS_S2SMASK = 125, H_REGISTERS_CALLH = 126
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, H_REGISTERS_CALLL = 127
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} REGISTER_NAMES;
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/* Attributes. */
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/* Enum declaration for machine type selection. */
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typedef enum mach_attr {
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MACH_BASE, MACH_IP2022, MACH_IP2022EXT, MACH_MAX
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} MACH_ATTR;
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/* Enum declaration for instruction set selection. */
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typedef enum isa_attr {
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ISA_IP2K, ISA_MAX
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} ISA_ATTR;
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/* Number of architecture variants. */
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#define MAX_ISAS 1
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#define MAX_MACHS ((int) MACH_MAX)
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/* Ifield support. */
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extern const struct cgen_ifld ip2k_cgen_ifld_table[];
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/* Ifield attribute indices. */
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/* Enum declaration for cgen_ifld attrs. */
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typedef enum cgen_ifld_attr {
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CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
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, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
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, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
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} CGEN_IFLD_ATTR;
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/* Number of non-boolean elements in cgen_ifld_attr. */
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#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
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/* Enum declaration for ip2k ifield types. */
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typedef enum ifield_type {
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IP2K_F_NIL, IP2K_F_ANYOF, IP2K_F_IMM8, IP2K_F_REG
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, IP2K_F_ADDR16CJP, IP2K_F_DIR, IP2K_F_BITNO, IP2K_F_OP3
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, IP2K_F_OP4, IP2K_F_OP4MID, IP2K_F_OP6, IP2K_F_OP8
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, IP2K_F_OP6_10LOW, IP2K_F_OP6_7LOW, IP2K_F_RETI3, IP2K_F_SKIPB
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, IP2K_F_PAGE3, IP2K_F_MAX
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} IFIELD_TYPE;
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#define MAX_IFLD ((int) IP2K_F_MAX)
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/* Hardware attribute indices. */
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/* Enum declaration for cgen_hw attrs. */
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typedef enum cgen_hw_attr {
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CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
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, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
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} CGEN_HW_ATTR;
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/* Number of non-boolean elements in cgen_hw_attr. */
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#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
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/* Enum declaration for ip2k hardware types. */
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typedef enum cgen_hw_type {
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HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
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, HW_H_IADDR, HW_H_SPR, HW_H_REGISTERS, HW_H_STACK
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, HW_H_PABITS, HW_H_ZBIT, HW_H_CBIT, HW_H_DCBIT
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, HW_H_PC, HW_MAX
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} CGEN_HW_TYPE;
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#define MAX_HW ((int) HW_MAX)
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/* Operand attribute indices. */
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/* Enum declaration for cgen_operand attrs. */
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typedef enum cgen_operand_attr {
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CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
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, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
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, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
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} CGEN_OPERAND_ATTR;
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/* Number of non-boolean elements in cgen_operand_attr. */
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#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
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/* Enum declaration for ip2k operand types. */
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typedef enum cgen_operand_type {
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IP2K_OPERAND_PC, IP2K_OPERAND_ADDR16CJP, IP2K_OPERAND_FR, IP2K_OPERAND_LIT8
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, IP2K_OPERAND_BITNO, IP2K_OPERAND_ADDR16P, IP2K_OPERAND_ADDR16H, IP2K_OPERAND_ADDR16L
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, IP2K_OPERAND_RETI3, IP2K_OPERAND_PABITS, IP2K_OPERAND_ZBIT, IP2K_OPERAND_CBIT
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, IP2K_OPERAND_DCBIT, IP2K_OPERAND_MAX
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} CGEN_OPERAND_TYPE;
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/* Number of operands types. */
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#define MAX_OPERANDS 13
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/* Maximum number of operands referenced by any insn. */
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#define MAX_OPERAND_INSTANCES 8
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/* Insn attribute indices. */
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/* Enum declaration for cgen_insn attrs. */
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typedef enum cgen_insn_attr {
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CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
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, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
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, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_EXT_SKIP_INSN, CGEN_INSN_SKIPA
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, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
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} CGEN_INSN_ATTR;
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/* Number of non-boolean elements in cgen_insn_attr. */
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#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
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/* cgen.h uses things we just defined. */
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#include "opcode/cgen.h"
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/* Attributes. */
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extern const CGEN_ATTR_TABLE ip2k_cgen_hardware_attr_table[];
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extern const CGEN_ATTR_TABLE ip2k_cgen_ifield_attr_table[];
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extern const CGEN_ATTR_TABLE ip2k_cgen_operand_attr_table[];
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extern const CGEN_ATTR_TABLE ip2k_cgen_insn_attr_table[];
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/* Hardware decls. */
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#endif /* IP2K_CPU_H */
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