d70b4d426b
* Makefile.in, d10v_sim.h, interp.c: Fix byte-order problems.
126 lines
3.1 KiB
C
126 lines
3.1 KiB
C
#include <stdio.h>
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#include <ctype.h>
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#include "ansidecl.h"
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#include "opcode/d10v.h"
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/* FIXME: host defines */
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typedef unsigned char uint8;
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typedef unsigned short uint16;
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typedef unsigned int uint32;
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typedef signed char int8;
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typedef signed short int16;
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typedef signed int int32;
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typedef signed long long int64;
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/* FIXME: D10V defines */
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typedef uint16 reg_t;
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struct simops
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{
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long opcode;
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long mask;
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int format;
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int cycles;
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int unit;
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int exec_type;
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void (*func)();
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int numops;
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int operands[9];
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};
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struct _state
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{
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reg_t regs[16]; /* general-purpose registers */
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reg_t cregs[16]; /* control registers */
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int64 a[2]; /* accumulators */
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uint8 SM;
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uint8 EA;
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uint8 DB;
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uint8 IE;
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uint8 RP;
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uint8 MD;
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uint8 FX;
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uint8 ST;
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uint8 F0;
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uint8 F1;
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uint8 C;
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uint8 exe;
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uint8 *imem;
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uint8 *dmem;
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int exception;
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} State;
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extern uint16 OP[4];
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extern struct simops Simops[];
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#define PC (State.cregs[2])
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#define PSW (State.cregs[0])
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#define BPSW (State.cregs[1])
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#define BPC (State.cregs[3])
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#define RPT_C (State.cregs[7])
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#define RPT_S (State.cregs[8])
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#define RPT_E (State.cregs[9])
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#define MOD_S (State.cregs[10])
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#define MOD_E (State.cregs[11])
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#define IBA (State.cregs[14])
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#define SEXT3(x) ((((x)&0x7)^(~3))+4)
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/* sign-extend a 4-bit number */
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#define SEXT4(x) ((((x)&0xf)^(~7))+8)
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/* sign-extend an 8-bit number */
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#define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
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/* sign-extend a 16-bit number */
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#define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
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/* sign-extend a 32-bit number */
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#define SEXT32(x) ((((x)&0xffffffffLL)^(~0x7fffffffLL))+0x80000000LL)
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/* sign extend a 40 bit number */
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#define SEXT40(x) ((((x)&0xffffffffffLL)^(~0x7fffffffffLL))+0x8000000000LL)
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/* sign extend a 44 bit number */
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#define SEXT44(x) ((((x)&0xfffffffffffLL)^(~0x7ffffffffffLL))+0x80000000000LL)
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/* sign extend a 60 bit number */
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#define SEXT60(x) ((((x)&0xfffffffffffffffLL)^(~0x7ffffffffffffffLL))+0x800000000000000LL)
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#define MAX32 0x7fffffffLL
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#define MIN32 0xff80000000LL
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#define MASK32 0xffffffffLL
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#define MASK40 0xffffffffffLL
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#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
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#define RB(x) (*((uint8 *)((x)+State.imem)))
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#define SB(addr,data) ( RB(addr) = (data & 0xff))
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#ifdef WORDS_BIGENDIAN
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#define RW(x) (*((uint16 *)((x)+State.imem)))
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#define RLW(x) (*((uint32 *)((x)+State.imem)))
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#define SW(addr,data) RW(addr)=data
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#define READ_16(x) (*((int16 *)(x)))
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#define WRITE_16(addr,data) (*(int16 *)(addr)=data)
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#define READ_64(x) (*((int64 *)(x)))
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#define WRITE_64(addr,data) (*(int64 *)(addr)=data)
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#else
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uint32 get_longword PARAMS ((uint8 *));
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uint16 get_word PARAMS ((uint8 *));
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int64 get_longlong PARAMS ((uint8 *));
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void write_word PARAMS ((uint8 *addr, uint16 data));
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void write_longlong PARAMS ((uint8 *addr, int64 data));
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#define SW(addr,data) write_word((long)(addr)+State.imem,data)
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#define RW(x) get_word((long)(x)+State.imem)
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#define RLW(x) get_longword((long)(x)+State.imem)
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#define READ_16(x) get_word(x)
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#define WRITE_16(addr,data) write_word(addr,data)
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#define READ_64(x) get_longlong(x)
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#define WRITE_64(addr,data) write_longlong(addr,data)
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#endif /* not WORDS_BIGENDIAN */
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