13761a1136
* config.bfd (msp430): Define targ_selvecs. * configure.in: Add bfd_elf32_msp430_ti_vec. * cpu-msp430.c: Add some more MSP430 machine numbers. * elf32-msp430.c Add support for MSP430X relocations. Add support for TI compiler generated relocations. Add support for sym_diff relocations. Add support for relaxing out of range short branches into long branches. Add support for MSP430 attribute section. * reloc.c: Add MSP430X relocations. * targets.c: Add bfd_elf32_msp430_ti_vec. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * readelf.c: Add support for MSP430X architecture. * readelf.exp: Expect -wi test to fail for the MSP430. * config/tc-msp430.c: Add support for the MSP430X architecture. Add code to insert a NOP instruction after any instruction that might change the interrupt state. Add support for the LARGE memory model. Add code to initialise the .MSP430.attributes section. * config/tc-msp430.h: Add support for the MSP430X architecture. * doc/c-msp430.texi: Document the new -mL and -mN command line options. * NEWS: Mention support for the MSP430X architecture. * gas/all/gas.exp: Skip the DIFF1 test for the MSP430. Expect the FORWARD test to pass for the MSP430. Skip the REDEF tests for the MSP430. Expect the 930509A test to fail for the MSP430. * gas/all/sleb128-4.d: Skip for the MSP430. * gas/elf/elf.exp: Set target_machine to msp430 for the MSP430. Skip the EHOPT0 test for the MSP430. Skip the REDEF and EQU-RELOC tests for the MSP430. * gas/elf/section2.e-msp430: New file. * gas/lns/lns-big-delta.d: Remove expectation of 20-bit addresses. * gas/lns/lns.exp: Use alternate LNS COMMON test for the MSP430. * gas/msp430/msp430x.s: New test. * gas/msp430/msp430x.d: Expected disassembly. * gas/msp430/msp430.exp: Run new test. * gas/msp430/opcode.d: Update expected disassembly. * msp430.h: Add MSP430X relocs. Add some more MSP430 machine numbers. Add values used by .MSP430.attributes section. * msp430.h: Add patterns for MSP430X instructions. * Makefile.am: Add emsp430X.c * Makefine.in: Regenerate. * configure.tgt (msp430): Add msp430X emulation. * ldmain.c (multiple_definition): Only disable relaxation if it was enabled by the user. * ldmain.h (RELAXATION_ENABLED_BY_USER): New macro. * emulparams/msp430all.sh: Add support for MSP430X. * emultempl/generic.em: (before_parse): Enable relaxation for the MSP430. * scripttempl/msp430.sc: Reorganize sections. Add .rodata section. * scripttempl/msp430_3.sc: Likewise. * NEWS: Mention support for MSP430X. * ld-elf/flags1.d: Expect this test to pass on the MSP430. * ld-elf/init-fini-arrays.d: Expect this test to fail on the MSP430. * ld-elf/merge.d: Expect this test to pass on the MSP430. * ld-elf/sec64k.exp: Skip these tests for the MSP430. * ld-gc/pr13683.d: Expect this test to fail on the MSP430. * ld-srec/srec.exp: Expect these tests to fail on the MSP430. * ld-undefined/undefined.exp: Expect the UNDEFINED LINE test to fail on the MSP430. * msp430-dis.c: Add support for MSP430X instructions.
1229 lines
26 KiB
C
1229 lines
26 KiB
C
/* Disassemble MSP430 instructions.
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Copyright (C) 2002-2013 Free Software Foundation, Inc.
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Contributed by Dmitry Diky <diwil@mail.ru>
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include <ctype.h>
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#include <sys/types.h>
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#include "dis-asm.h"
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#include "opintl.h"
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#include "libiberty.h"
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#define DASM_SECTION
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#include "opcode/msp430.h"
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#undef DASM_SECTION
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#define PS(x) (0xffff & (x))
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static unsigned short
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msp430dis_opcode (bfd_vma addr, disassemble_info *info)
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{
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bfd_byte buffer[2];
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int status;
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status = info->read_memory_func (addr, buffer, 2, info);
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if (status != 0)
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{
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info->memory_error_func (status, addr, info);
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return -1;
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}
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return bfd_getl16 (buffer);
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}
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static int
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msp430_nooperands (struct msp430_opcode_s *opcode,
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bfd_vma addr ATTRIBUTE_UNUSED,
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unsigned short insn ATTRIBUTE_UNUSED,
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char *comm,
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int *cycles)
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{
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/* Pop with constant. */
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if (insn == 0x43b2)
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return 0;
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if (insn == opcode->bin_opcode)
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return 2;
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if (opcode->fmt == 0)
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{
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if ((insn & 0x0f00) != 3 || (insn & 0x0f00) != 2)
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return 0;
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strcpy (comm, "emulated...");
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*cycles = 1;
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}
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else
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{
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strcpy (comm, "return from interupt");
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*cycles = 5;
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}
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return 2;
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}
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static int
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print_as2_reg_name (int regno, char * op1, char * comm1,
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int c2, int c3, int cd)
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{
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switch (regno)
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{
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case 2:
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sprintf (op1, "#4");
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sprintf (comm1, "r2 As==10");
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return c2;
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case 3:
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sprintf (op1, "#2");
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sprintf (comm1, "r3 As==10");
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return c3;
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default:
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/* Indexed register mode @Rn. */
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sprintf (op1, "@r%d", regno);
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return cd;
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}
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}
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static int
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print_as3_reg_name (int regno, char * op1, char * comm1,
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int c2, int c3, int cd)
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{
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switch (regno)
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{
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case 2:
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sprintf (op1, "#8");
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sprintf (comm1, "r2 As==11");
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return c2;
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case 3:
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sprintf (op1, "#-1");
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sprintf (comm1, "r3 As==11");
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return c3;
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default:
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/* Post incremented @Rn+. */
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sprintf (op1, "@r%d+", regno);
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return cd;
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}
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}
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static int
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msp430_singleoperand (disassemble_info *info,
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struct msp430_opcode_s *opcode,
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bfd_vma addr,
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unsigned short insn,
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char *op,
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char *comm,
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unsigned short extension_word,
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int *cycles)
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{
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int regs = 0, regd = 0;
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int ad = 0, as = 0;
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int where = 0;
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int cmd_len = 2;
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int dst = 0;
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int fmt;
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int extended_dst = extension_word & 0xf;
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regd = insn & 0x0f;
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regs = (insn & 0x0f00) >> 8;
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as = (insn & 0x0030) >> 4;
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ad = (insn & 0x0080) >> 7;
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if (opcode->fmt < 0)
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fmt = (- opcode->fmt) - 1;
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else
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fmt = opcode->fmt;
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switch (fmt)
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{
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case 0: /* Emulated work with dst register. */
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if (regs != 2 && regs != 3 && regs != 1)
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return 0;
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/* Check if not clr insn. */
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if (opcode->bin_opcode == 0x4300 && (ad || as))
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return 0;
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/* Check if really inc, incd insns. */
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if ((opcode->bin_opcode & 0xff00) == 0x5300 && as == 3)
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return 0;
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if (ad == 0)
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{
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*cycles = 1;
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/* Register. */
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if (regd == 0)
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{
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*cycles += 1;
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sprintf (op, "r0");
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}
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else if (regd == 1)
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sprintf (op, "r1");
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else if (regd == 2)
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sprintf (op, "r2");
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else
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sprintf (op, "r%d", regd);
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}
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else /* ad == 1 msp430dis_opcode. */
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{
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if (regd == 0)
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{
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/* PC relative. */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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*cycles = 4;
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sprintf (op, "0x%04x", dst);
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sprintf (comm, "PC rel. abs addr 0x%04x",
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PS ((short) (addr + 2) + dst));
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if (extended_dst)
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{
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dst |= extended_dst << 16;
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sprintf (op, "0x%05x", dst);
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sprintf (comm, "PC rel. abs addr 0x%05lx",
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(long)((addr + 2 + dst) & 0xfffff));
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}
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}
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else if (regd == 2)
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{
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/* Absolute. */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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*cycles = 4;
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sprintf (op, "&0x%04x", PS (dst));
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if (extended_dst)
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{
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dst |= extended_dst << 16;
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sprintf (op, "&0x%05x", dst & 0xfffff);
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}
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}
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else
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{
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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*cycles = 4;
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if (extended_dst)
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{
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dst |= extended_dst << 16;
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if (dst & 0x80000)
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dst |= -1 << 20;
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}
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else if (dst & 0x8000)
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dst |= -1 << 16;
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sprintf (op, "%d(r%d)", dst, regd);
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}
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}
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break;
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case 2: /* rrc, push, call, swpb, rra, sxt, push, call, reti etc... */
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if (as == 0)
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{
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if (regd == 3)
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{
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/* Constsnts. */
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sprintf (op, "#0");
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sprintf (comm, "r3 As==00");
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}
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else
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{
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/* Register. */
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sprintf (op, "r%d", regd);
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}
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*cycles = 1;
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}
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else if (as == 2)
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{
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* cycles = print_as2_reg_name (regd, op, comm, 1, 1, 3);
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}
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else if (as == 3)
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{
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if (regd == 0)
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{
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*cycles = 3;
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/* absolute. @pc+ */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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sprintf (op, "#%d", dst);
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if (dst > 9 || dst < 0)
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sprintf (comm, "#0x%04x", PS (dst));
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if (extended_dst)
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{
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dst |= extended_dst << 16;
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if (dst & 0x80000)
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dst |= -1 << 20;
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sprintf (op, "#%d", dst);
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if (dst > 9 || dst < 0)
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sprintf (comm, "#0x%05x", dst);
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}
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}
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else
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* cycles = print_as3_reg_name (regd, op, comm, 1, 1, 3);
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}
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else if (as == 1)
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{
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*cycles = 4;
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if (regd == 0)
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{
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/* PC relative. */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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sprintf (op, "0x%04x", PS (dst));
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sprintf (comm, "PC rel. 0x%04x",
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PS ((short) addr + 2 + dst));
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if (extended_dst)
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{
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dst |= extended_dst << 16;
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sprintf (op, "0x%05x", dst & 0xffff);
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sprintf (comm, "PC rel. 0x%05lx",
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(long)((addr + 2 + dst) & 0xfffff));
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}
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}
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else if (regd == 2)
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{
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/* Absolute. */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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sprintf (op, "&0x%04x", PS (dst));
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if (extended_dst)
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{
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dst |= extended_dst << 16;
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sprintf (op, "&0x%05x", dst & 0xfffff);
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}
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}
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else if (regd == 3)
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{
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*cycles = 1;
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sprintf (op, "#1");
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sprintf (comm, "r3 As==01");
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}
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else
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{
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/* Indexed. */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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if (extended_dst)
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{
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dst |= extended_dst << 16;
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if (dst & 0x80000)
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dst |= -1 << 20;
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}
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else if (dst & 0x8000)
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dst |= -1 << 16;
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sprintf (op, "%d(r%d)", dst, regd);
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if (dst > 9 || dst < 0)
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sprintf (comm, "%05x", dst);
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}
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}
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break;
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case 3: /* Jumps. */
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where = insn & 0x03ff;
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if (where & 0x200)
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where |= ~0x03ff;
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if (where > 512 || where < -511)
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return 0;
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where *= 2;
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sprintf (op, "$%+-8d", where + 2);
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sprintf (comm, "abs 0x%lx", (long) (addr + 2 + where));
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*cycles = 2;
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return 2;
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break;
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default:
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cmd_len = 0;
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}
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return cmd_len;
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}
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static int
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msp430_doubleoperand (disassemble_info *info,
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struct msp430_opcode_s *opcode,
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bfd_vma addr,
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unsigned short insn,
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char *op1,
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char *op2,
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char *comm1,
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char *comm2,
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unsigned short extension_word,
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int *cycles)
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{
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int regs = 0, regd = 0;
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int ad = 0, as = 0;
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int cmd_len = 2;
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int dst = 0;
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int fmt;
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int extended_dst = extension_word & 0xf;
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int extended_src = (extension_word >> 7) & 0xf;
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regd = insn & 0x0f;
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regs = (insn & 0x0f00) >> 8;
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as = (insn & 0x0030) >> 4;
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ad = (insn & 0x0080) >> 7;
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if (opcode->fmt < 0)
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fmt = (- opcode->fmt) - 1;
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else
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fmt = opcode->fmt;
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if (fmt == 0)
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{
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/* Special case: rla and rlc are the only 2 emulated instructions that
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fall into two operand instructions. */
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/* With dst, there are only:
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Rm Register,
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x(Rm) Indexed,
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0xXXXX Relative,
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&0xXXXX Absolute
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emulated_ins dst
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basic_ins dst, dst. */
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if (regd != regs || as != ad)
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return 0; /* May be 'data' section. */
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if (ad == 0)
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{
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/* Register mode. */
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if (regd == 3)
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{
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strcpy (comm1, _("Illegal as emulation instr"));
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return -1;
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}
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sprintf (op1, "r%d", regd);
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*cycles = 1;
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}
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else /* ad == 1 */
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{
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if (regd == 0)
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{
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/* PC relative, Symbolic. */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 4;
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*cycles = 6;
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sprintf (op1, "0x%04x", PS (dst));
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sprintf (comm1, "PC rel. 0x%04x",
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PS ((short) addr + 2 + dst));
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if (extended_dst)
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{
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dst |= extended_dst << 16;
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if (dst & 0x80000)
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dst |= -1 << 20;
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sprintf (op1, "0x%05x", dst & 0xfffff);
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sprintf (comm1, "PC rel. 0x%05lx",
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(long)((addr + 2 + dst) & 0xfffff));
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}
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}
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else if (regd == 2)
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{
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/* Absolute. */
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dst = msp430dis_opcode (addr + 2, info);
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/* If the 'src' field is not the same as the dst
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then this is not an rla instruction. */
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if (dst != msp430dis_opcode (addr + 4, info))
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return 0;
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cmd_len += 4;
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*cycles = 6;
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sprintf (op1, "&0x%04x", PS (dst));
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if (extended_dst)
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{
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dst |= extended_dst << 16;
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sprintf (op1, "&0x%05x", dst & 0xfffff);
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}
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}
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else
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{
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/* Indexed. */
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dst = msp430dis_opcode (addr + 2, info);
|
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if (extended_dst)
|
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{
|
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dst |= extended_dst << 16;
|
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if (dst & 0x80000)
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dst |= -1 << 20;
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}
|
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else if (dst & 0x8000)
|
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dst |= -1 << 16;
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cmd_len += 4;
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*cycles = 6;
|
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sprintf (op1, "%d(r%d)", dst, regd);
|
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if (dst > 9 || dst < -9)
|
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sprintf (comm1, "#0x%05x", dst);
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}
|
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}
|
|
|
|
*op2 = 0;
|
|
*comm2 = 0;
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|
|
return cmd_len;
|
|
}
|
|
|
|
/* Two operands exactly. */
|
|
if (ad == 0 && regd == 3)
|
|
{
|
|
/* R2/R3 are illegal as dest: may be data section. */
|
|
strcpy (comm1, _("Illegal as 2-op instr"));
|
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return -1;
|
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}
|
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|
|
/* Source. */
|
|
if (as == 0)
|
|
{
|
|
*cycles = 1;
|
|
if (regs == 3)
|
|
{
|
|
/* Constants. */
|
|
sprintf (op1, "#0");
|
|
sprintf (comm1, "r3 As==00");
|
|
}
|
|
else
|
|
{
|
|
/* Register. */
|
|
sprintf (op1, "r%d", regs);
|
|
}
|
|
}
|
|
else if (as == 2)
|
|
{
|
|
* cycles = print_as2_reg_name (regs, op1, comm1, 1, 1, regs == 0 ? 3 : 2);
|
|
}
|
|
else if (as == 3)
|
|
{
|
|
if (regs == 0)
|
|
{
|
|
*cycles = 3;
|
|
/* Absolute. @pc+. */
|
|
dst = msp430dis_opcode (addr + 2, info);
|
|
cmd_len += 2;
|
|
sprintf (op1, "#%d", dst);
|
|
if (dst > 9 || dst < 0)
|
|
sprintf (comm1, "#0x%04x", PS (dst));
|
|
if (extended_src)
|
|
{
|
|
dst |= extended_src << 16;
|
|
if (dst & 0x80000)
|
|
dst |= -1 << 20;
|
|
sprintf (op1, "#%d", dst);
|
|
if (dst > 9 || dst < 0)
|
|
sprintf (comm1, "0x%05x", dst & 0xfffff);
|
|
}
|
|
}
|
|
else
|
|
* cycles = print_as3_reg_name (regs, op1, comm1, 1, 1, 2);
|
|
}
|
|
else if (as == 1)
|
|
{
|
|
if (regs == 0)
|
|
{
|
|
*cycles = 4;
|
|
/* PC relative. */
|
|
dst = msp430dis_opcode (addr + 2, info);
|
|
cmd_len += 2;
|
|
sprintf (op1, "0x%04x", PS (dst));
|
|
sprintf (comm1, "PC rel. 0x%04x",
|
|
PS ((short) addr + 2 + dst));
|
|
if (extended_src)
|
|
{
|
|
dst |= extended_src << 16;
|
|
if (dst & 0x80000)
|
|
dst |= -1 << 20;
|
|
sprintf (op1, "0x%05x", dst & 0xfffff);
|
|
sprintf (comm1, "PC rel. 0x%05lx",
|
|
(long) ((addr + 2 + dst) & 0xfffff));
|
|
}
|
|
}
|
|
else if (regs == 2)
|
|
{
|
|
*cycles = 2;
|
|
/* Absolute. */
|
|
dst = msp430dis_opcode (addr + 2, info);
|
|
cmd_len += 2;
|
|
sprintf (op1, "&0x%04x", PS (dst));
|
|
sprintf (comm1, "0x%04x", PS (dst));
|
|
if (extended_src)
|
|
{
|
|
dst |= extended_src << 16;
|
|
sprintf (op1, "&0x%05x", dst & 0xfffff);
|
|
* comm1 = 0;
|
|
}
|
|
}
|
|
else if (regs == 3)
|
|
{
|
|
*cycles = 1;
|
|
sprintf (op1, "#1");
|
|
sprintf (comm1, "r3 As==01");
|
|
}
|
|
else
|
|
{
|
|
*cycles = 3;
|
|
/* Indexed. */
|
|
dst = msp430dis_opcode (addr + 2, info);
|
|
cmd_len += 2;
|
|
if (extended_src)
|
|
{
|
|
dst |= extended_src << 16;
|
|
if (dst & 0x80000)
|
|
dst |= -1 << 20;
|
|
}
|
|
else if (dst & 0x8000)
|
|
dst |= -1 << 16;
|
|
sprintf (op1, "%d(r%d)", dst, regs);
|
|
if (dst > 9 || dst < -9)
|
|
sprintf (comm1, "0x%05x", dst);
|
|
}
|
|
}
|
|
|
|
/* Destination. Special care needed on addr + XXXX. */
|
|
|
|
if (ad == 0)
|
|
{
|
|
/* Register. */
|
|
if (regd == 0)
|
|
{
|
|
*cycles += 1;
|
|
sprintf (op2, "r0");
|
|
}
|
|
else if (regd == 1)
|
|
sprintf (op2, "r1");
|
|
|
|
else if (regd == 2)
|
|
sprintf (op2, "r2");
|
|
|
|
else
|
|
sprintf (op2, "r%d", regd);
|
|
}
|
|
else /* ad == 1. */
|
|
{
|
|
* cycles += 3;
|
|
|
|
if (regd == 0)
|
|
{
|
|
/* PC relative. */
|
|
*cycles += 1;
|
|
dst = msp430dis_opcode (addr + cmd_len, info);
|
|
sprintf (op2, "0x%04x", PS (dst));
|
|
sprintf (comm2, "PC rel. 0x%04x",
|
|
PS ((short) addr + cmd_len + dst));
|
|
if (extended_dst)
|
|
{
|
|
dst |= extended_dst << 16;
|
|
if (dst & 0x80000)
|
|
dst |= -1 << 20;
|
|
sprintf (op2, "0x%05x", dst & 0xfffff);
|
|
sprintf (comm2, "PC rel. 0x%05lx",
|
|
(long)((addr + cmd_len + dst) & 0xfffff));
|
|
}
|
|
cmd_len += 2;
|
|
}
|
|
else if (regd == 2)
|
|
{
|
|
/* Absolute. */
|
|
dst = msp430dis_opcode (addr + cmd_len, info);
|
|
cmd_len += 2;
|
|
sprintf (op2, "&0x%04x", PS (dst));
|
|
if (extended_dst)
|
|
{
|
|
dst |= extended_dst << 16;
|
|
sprintf (op2, "&0x%05x", dst & 0xfffff);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
dst = msp430dis_opcode (addr + cmd_len, info);
|
|
cmd_len += 2;
|
|
if (dst & 0x8000)
|
|
dst |= -1 << 16;
|
|
if (dst > 9 || dst < 0)
|
|
sprintf (comm2, "0x%04x", PS (dst));
|
|
if (extended_dst)
|
|
{
|
|
dst |= extended_dst << 16;
|
|
if (dst & 0x80000)
|
|
dst |= -1 << 20;
|
|
if (dst > 9 || dst < 0)
|
|
sprintf (comm2, "0x%05x", dst & 0xfffff);
|
|
}
|
|
sprintf (op2, "%d(r%d)", dst, regd);
|
|
}
|
|
}
|
|
|
|
return cmd_len;
|
|
}
|
|
|
|
static int
|
|
msp430_branchinstr (disassemble_info *info,
|
|
struct msp430_opcode_s *opcode ATTRIBUTE_UNUSED,
|
|
bfd_vma addr ATTRIBUTE_UNUSED,
|
|
unsigned short insn,
|
|
char *op1,
|
|
char *comm1,
|
|
int *cycles)
|
|
{
|
|
int regs = 0, regd = 0;
|
|
int as = 0;
|
|
int cmd_len = 2;
|
|
short dst = 0;
|
|
|
|
regd = insn & 0x0f;
|
|
regs = (insn & 0x0f00) >> 8;
|
|
as = (insn & 0x0030) >> 4;
|
|
|
|
if (regd != 0) /* Destination register is not a PC. */
|
|
return 0;
|
|
|
|
/* dst is a source register. */
|
|
if (as == 0)
|
|
{
|
|
/* Constants. */
|
|
if (regs == 3)
|
|
{
|
|
*cycles = 1;
|
|
sprintf (op1, "#0");
|
|
sprintf (comm1, "r3 As==00");
|
|
}
|
|
else
|
|
{
|
|
/* Register. */
|
|
*cycles = 1;
|
|
sprintf (op1, "r%d", regs);
|
|
}
|
|
}
|
|
else if (as == 2)
|
|
{
|
|
* cycles = print_as2_reg_name (regs, op1, comm1, 2, 1, 2);
|
|
}
|
|
else if (as == 3)
|
|
{
|
|
if (regs == 0)
|
|
{
|
|
/* Absolute. @pc+ */
|
|
*cycles = 3;
|
|
dst = msp430dis_opcode (addr + 2, info);
|
|
cmd_len += 2;
|
|
sprintf (op1, "#0x%04x", PS (dst));
|
|
}
|
|
else
|
|
* cycles = print_as3_reg_name (regs, op1, comm1, 1, 1, 2);
|
|
}
|
|
else if (as == 1)
|
|
{
|
|
* cycles = 3;
|
|
|
|
if (regs == 0)
|
|
{
|
|
/* PC relative. */
|
|
dst = msp430dis_opcode (addr + 2, info);
|
|
cmd_len += 2;
|
|
(*cycles)++;
|
|
sprintf (op1, "0x%04x", PS (dst));
|
|
sprintf (comm1, "PC rel. 0x%04x",
|
|
PS ((short) addr + 2 + dst));
|
|
}
|
|
else if (regs == 2)
|
|
{
|
|
/* Absolute. */
|
|
dst = msp430dis_opcode (addr + 2, info);
|
|
cmd_len += 2;
|
|
sprintf (op1, "&0x%04x", PS (dst));
|
|
}
|
|
else if (regs == 3)
|
|
{
|
|
(*cycles)--;
|
|
sprintf (op1, "#1");
|
|
sprintf (comm1, "r3 As==01");
|
|
}
|
|
else
|
|
{
|
|
/* Indexed. */
|
|
dst = msp430dis_opcode (addr + 2, info);
|
|
cmd_len += 2;
|
|
if (dst & 0x8000)
|
|
dst |= -1 << 16;
|
|
sprintf (op1, "%d(r%d)", dst, regs);
|
|
}
|
|
}
|
|
|
|
return cmd_len;
|
|
}
|
|
|
|
static int
|
|
msp430x_calla_instr (disassemble_info * info,
|
|
bfd_vma addr,
|
|
unsigned short insn,
|
|
char * op1,
|
|
char * comm1,
|
|
int * cycles)
|
|
{
|
|
unsigned int ureg = insn & 0xf;
|
|
int reg = insn & 0xf;
|
|
int am = (insn & 0xf0) >> 4;
|
|
int cmd_len = 2;
|
|
unsigned short udst = 0;
|
|
short dst = 0;
|
|
|
|
switch (am)
|
|
{
|
|
case 4: /* CALLA Rdst */
|
|
*cycles = 1;
|
|
sprintf (op1, "r%d", reg);
|
|
break;
|
|
|
|
case 5: /* CALLA x(Rdst) */
|
|
*cycles = 3;
|
|
dst = msp430dis_opcode (addr + 2, info);
|
|
cmd_len += 2;
|
|
sprintf (op1, "%d(r%d)", dst, reg);
|
|
if (reg == 0)
|
|
sprintf (comm1, "PC rel. 0x%05lx", (long) (addr + 2 + dst));
|
|
else
|
|
sprintf (comm1, "0x%05x", dst);
|
|
break;
|
|
|
|
case 6: /* CALLA @Rdst */
|
|
*cycles = 2;
|
|
sprintf (op1, "@r%d", reg);
|
|
break;
|
|
|
|
case 7: /* CALLA @Rdst+ */
|
|
*cycles = 2;
|
|
sprintf (op1, "@r%d+", reg);
|
|
break;
|
|
|
|
case 8: /* CALLA &abs20 */
|
|
udst = msp430dis_opcode (addr + 2, info);
|
|
cmd_len += 2;
|
|
*cycles = 4;
|
|
sprintf (op1, "&%d", (ureg << 16) + udst);
|
|
sprintf (comm1, "0x%05x", (ureg << 16) + udst);
|
|
break;
|
|
|
|
case 9: /* CALLA pcrel-sym */
|
|
dst = msp430dis_opcode (addr + 2, info);
|
|
cmd_len += 2;
|
|
*cycles = 4;
|
|
sprintf (op1, "%d(PC)", (reg << 16) + dst);
|
|
sprintf (comm1, "PC rel. 0x%05lx",
|
|
(long) (addr + 2 + dst + (reg << 16)));
|
|
break;
|
|
|
|
case 11: /* CALLA #imm20 */
|
|
udst = msp430dis_opcode (addr + 2, info);
|
|
cmd_len += 2;
|
|
*cycles = 4;
|
|
sprintf (op1, "#%d", (ureg << 16) + udst);
|
|
sprintf (comm1, "0x%05x", (ureg << 16) + udst);
|
|
break;
|
|
|
|
default:
|
|
strcpy (comm1, _("unercognised CALLA addressing mode"));
|
|
return -1;
|
|
}
|
|
|
|
return cmd_len;
|
|
}
|
|
|
|
int
|
|
print_insn_msp430 (bfd_vma addr, disassemble_info *info)
|
|
{
|
|
void *stream = info->stream;
|
|
fprintf_ftype prin = info->fprintf_func;
|
|
struct msp430_opcode_s *opcode;
|
|
char op1[32], op2[32], comm1[64], comm2[64];
|
|
int cmd_len = 0;
|
|
unsigned short insn;
|
|
int cycles = 0;
|
|
char *bc = "";
|
|
unsigned short extension_word = 0;
|
|
|
|
insn = msp430dis_opcode (addr, info);
|
|
if (insn == (unsigned short) -1)
|
|
{
|
|
prin (stream, ".word 0xffff; ????");
|
|
return 2;
|
|
}
|
|
|
|
if (((int) addr & 0xffff) > 0xffdf)
|
|
{
|
|
(*prin) (stream, "interrupt service routine at 0x%04x", 0xffff & insn);
|
|
return 2;
|
|
}
|
|
|
|
*comm1 = 0;
|
|
*comm2 = 0;
|
|
|
|
/* Check for an extension word. */
|
|
if ((insn & 0xf800) == 0x1800)
|
|
{
|
|
extension_word = insn;
|
|
addr += 2;
|
|
insn = msp430dis_opcode (addr, info);
|
|
if (insn == (unsigned short) -1)
|
|
{
|
|
prin (stream, ".word 0x%04x, 0xffff; ????",
|
|
extension_word);
|
|
return 4;
|
|
}
|
|
}
|
|
|
|
for (opcode = msp430_opcodes; opcode->name; opcode++)
|
|
{
|
|
if ((insn & opcode->bin_mask) == opcode->bin_opcode
|
|
&& opcode->bin_opcode != 0x9300)
|
|
{
|
|
*op1 = 0;
|
|
*op2 = 0;
|
|
*comm1 = 0;
|
|
*comm2 = 0;
|
|
|
|
/* r0 as destination. Ad should be zero. */
|
|
if (opcode->insn_opnumb == 3
|
|
&& (insn & 0x000f) == 0
|
|
&& (insn & 0x0080) == 0)
|
|
{
|
|
cmd_len +=
|
|
msp430_branchinstr (info, opcode, addr, insn, op1, comm1,
|
|
&cycles);
|
|
if (cmd_len)
|
|
break;
|
|
}
|
|
|
|
switch (opcode->insn_opnumb)
|
|
{
|
|
int n;
|
|
int reg;
|
|
|
|
case 4:
|
|
cmd_len += msp430x_calla_instr (info, addr, insn,
|
|
op1, comm1, & cycles);
|
|
break;
|
|
|
|
case 5: /* PUSHM/POPM */
|
|
n = (insn & 0xf0) >> 4;
|
|
reg = (insn & 0xf);
|
|
|
|
sprintf (op1, "#%d", n + 1);
|
|
if (opcode->bin_opcode == 0x1400)
|
|
/* PUSHM */
|
|
sprintf (op2, "r%d", reg);
|
|
else
|
|
/* POPM */
|
|
sprintf (op2, "r%d", reg + n);
|
|
if (insn & 0x100)
|
|
sprintf (comm1, "16-bit words");
|
|
else
|
|
{
|
|
sprintf (comm1, "20-bit words");
|
|
bc =".a";
|
|
}
|
|
|
|
cycles = 2; /*FIXME*/
|
|
cmd_len = 2;
|
|
break;
|
|
|
|
case 6: /* RRAM, RRCM, RRUM, RLAM. */
|
|
n = ((insn >> 10) & 0x3) + 1;
|
|
reg = (insn & 0xf);
|
|
if ((insn & 0x10) == 0)
|
|
bc =".a";
|
|
sprintf (op1, "#%d", n);
|
|
sprintf (op2, "r%d", reg);
|
|
cycles = 2; /*FIXME*/
|
|
cmd_len = 2;
|
|
break;
|
|
|
|
case 8: /* ADDA, CMPA, SUBA. */
|
|
reg = (insn & 0xf);
|
|
n = (insn >> 8) & 0xf;
|
|
if (insn & 0x40)
|
|
{
|
|
sprintf (op1, "r%d", n);
|
|
cmd_len = 2;
|
|
}
|
|
else
|
|
{
|
|
n <<= 16;
|
|
n |= msp430dis_opcode (addr + 2, info);
|
|
sprintf (op1, "#%d", n);
|
|
if (n > 9 || n < 0)
|
|
sprintf (comm1, "0x%05x", n);
|
|
cmd_len = 4;
|
|
}
|
|
sprintf (op2, "r%d", reg);
|
|
cycles = 2; /*FIXME*/
|
|
break;
|
|
|
|
case 9: /* MOVA */
|
|
reg = (insn & 0xf);
|
|
n = (insn >> 8) & 0xf;
|
|
switch ((insn >> 4) & 0xf)
|
|
{
|
|
case 0: /* MOVA @Rsrc, Rdst */
|
|
cmd_len = 2;
|
|
sprintf (op1, "@r%d", n);
|
|
if (strcmp (opcode->name, "bra") != 0)
|
|
sprintf (op2, "r%d", reg);
|
|
break;
|
|
|
|
case 1: /* MOVA @Rsrc+, Rdst */
|
|
cmd_len = 2;
|
|
if (strcmp (opcode->name, "reta") != 0)
|
|
{
|
|
sprintf (op1, "@r%d+", n);
|
|
if (strcmp (opcode->name, "bra") != 0)
|
|
sprintf (op2, "r%d", reg);
|
|
}
|
|
break;
|
|
|
|
case 2: /* MOVA &abs20, Rdst */
|
|
cmd_len = 4;
|
|
n <<= 16;
|
|
n |= msp430dis_opcode (addr + 2, info);
|
|
sprintf (op1, "&%d", n);
|
|
if (n > 9 || n < 0)
|
|
sprintf (comm1, "0x%05x", n);
|
|
if (strcmp (opcode->name, "bra") != 0)
|
|
sprintf (op2, "r%d", reg);
|
|
break;
|
|
|
|
case 3: /* MOVA x(Rsrc), Rdst */
|
|
cmd_len = 4;
|
|
if (strcmp (opcode->name, "bra") != 0)
|
|
sprintf (op2, "r%d", reg);
|
|
reg = n;
|
|
n = msp430dis_opcode (addr + 2, info);
|
|
if (n & 0x8000)
|
|
n |= -1 << 16;
|
|
sprintf (op1, "%d(r%d)", n, reg);
|
|
if (n > 9 || n < 0)
|
|
{
|
|
if (reg == 0)
|
|
sprintf (comm1, "PC rel. 0x%05lx",
|
|
(long) (addr + 2 + n));
|
|
else
|
|
sprintf (comm1, "0x%05x", n);
|
|
}
|
|
break;
|
|
|
|
case 6: /* MOVA Rsrc, &abs20 */
|
|
cmd_len = 4;
|
|
reg <<= 16;
|
|
reg |= msp430dis_opcode (addr + 2, info);
|
|
sprintf (op1, "r%d", n);
|
|
sprintf (op2, "&%d", reg);
|
|
if (reg > 9 || reg < 0)
|
|
sprintf (comm2, "0x%05x", reg);
|
|
break;
|
|
|
|
case 7: /* MOVA Rsrc, x(Rdst) */
|
|
cmd_len = 4;
|
|
sprintf (op1, "r%d", n);
|
|
n = msp430dis_opcode (addr + 2, info);
|
|
if (n & 0x8000)
|
|
n |= -1 << 16;
|
|
sprintf (op2, "%d(r%d)", n, reg);
|
|
if (n > 9 || n < 0)
|
|
{
|
|
if (reg == 0)
|
|
sprintf (comm2, "PC rel. 0x%05lx",
|
|
(long) (addr + 2 + n));
|
|
else
|
|
sprintf (comm2, "0x%05x", n);
|
|
}
|
|
break;
|
|
|
|
case 8: /* MOVA #imm20, Rdst */
|
|
cmd_len = 4;
|
|
n <<= 16;
|
|
n |= msp430dis_opcode (addr + 2, info);
|
|
if (n & 0x80000)
|
|
n |= -1 << 20;
|
|
sprintf (op1, "#%d", n);
|
|
if (n > 9 || n < 0)
|
|
sprintf (comm1, "0x%05x", n);
|
|
if (strcmp (opcode->name, "bra") != 0)
|
|
sprintf (op2, "r%d", reg);
|
|
break;
|
|
|
|
case 12: /* MOVA Rsrc, Rdst */
|
|
cmd_len = 2;
|
|
sprintf (op1, "r%d", n);
|
|
if (strcmp (opcode->name, "bra") != 0)
|
|
sprintf (op2, "r%d", reg);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
cycles = 2; /* FIXME */
|
|
break;
|
|
}
|
|
|
|
if (cmd_len)
|
|
break;
|
|
|
|
switch (opcode->insn_opnumb)
|
|
{
|
|
case 0:
|
|
cmd_len += msp430_nooperands (opcode, addr, insn, comm1, &cycles);
|
|
break;
|
|
case 2:
|
|
cmd_len +=
|
|
msp430_doubleoperand (info, opcode, addr, insn, op1, op2,
|
|
comm1, comm2,
|
|
extension_word,
|
|
&cycles);
|
|
if (insn & BYTE_OPERATION)
|
|
{
|
|
if (extension_word != 0 && ((extension_word & BYTE_OPERATION) == 0))
|
|
bc = ".a";
|
|
else
|
|
bc = ".b";
|
|
}
|
|
else if (extension_word)
|
|
{
|
|
if (extension_word & (1 << 6))
|
|
bc = ".w";
|
|
else
|
|
{
|
|
bc = ".?";
|
|
sprintf (comm2, _("Reserved use of A/L and B/W bits detected"));
|
|
}
|
|
}
|
|
|
|
break;
|
|
case 1:
|
|
cmd_len +=
|
|
msp430_singleoperand (info, opcode, addr, insn, op1, comm1,
|
|
extension_word,
|
|
&cycles);
|
|
if (extension_word
|
|
&& (strcmp (opcode->name, "swpb") == 0
|
|
|| strcmp (opcode->name, "sxt") == 0))
|
|
{
|
|
if (insn & BYTE_OPERATION)
|
|
{
|
|
bc = ".?";
|
|
sprintf (comm2, _("Reserved use of A/L and B/W bits detected"));
|
|
}
|
|
else if (extension_word & BYTE_OPERATION)
|
|
bc = ".w";
|
|
else
|
|
bc = ".a";
|
|
}
|
|
else if (insn & BYTE_OPERATION && opcode->fmt != 3)
|
|
{
|
|
if (extension_word != 0 && ((extension_word & BYTE_OPERATION) == 0))
|
|
bc = ".a";
|
|
else
|
|
bc = ".b";
|
|
}
|
|
else if (extension_word)
|
|
{
|
|
if (extension_word & (1 << 6))
|
|
bc = ".w";
|
|
else
|
|
{
|
|
bc = ".?";
|
|
sprintf (comm2, _("Reserved use of A/L and B/W bits detected"));
|
|
}
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (cmd_len)
|
|
break;
|
|
}
|
|
|
|
if (cmd_len < 1)
|
|
{
|
|
/* Unknown opcode, or invalid combination of operands. */
|
|
if (extension_word)
|
|
{
|
|
prin (stream, ".word 0x%04x, 0x%04x; ????", extension_word, PS (insn));
|
|
if (*comm1)
|
|
prin (stream, "\t %s", comm1);
|
|
return 4;
|
|
}
|
|
(*prin) (stream, ".word 0x%04x; ????", PS (insn));
|
|
return 2;
|
|
}
|
|
|
|
/* Display the repeat count (if set) for extended register mode. */
|
|
if (cmd_len == 2 && ((extension_word & 0xf) != 0))
|
|
{
|
|
if (extension_word & (1 << 7))
|
|
prin (stream, "rpt r%d { ", extension_word & 0xf);
|
|
else
|
|
prin (stream, "rpt #%d { ", (extension_word & 0xf) + 1);
|
|
}
|
|
|
|
if (extension_word && opcode->name[strlen (opcode->name) - 1] != 'x')
|
|
(*prin) (stream, "%sx%s", opcode->name, bc);
|
|
else
|
|
(*prin) (stream, "%s%s", opcode->name, bc);
|
|
|
|
if (*op1)
|
|
(*prin) (stream, "\t%s", op1);
|
|
if (*op2)
|
|
(*prin) (stream, ",");
|
|
|
|
if (strlen (op1) < 7)
|
|
(*prin) (stream, "\t");
|
|
if (!strlen (op1))
|
|
(*prin) (stream, "\t");
|
|
|
|
if (*op2)
|
|
(*prin) (stream, "%s", op2);
|
|
if (strlen (op2) < 8)
|
|
(*prin) (stream, "\t");
|
|
|
|
if (*comm1 || *comm2)
|
|
(*prin) (stream, ";");
|
|
else if (cycles)
|
|
{
|
|
if (*op2)
|
|
(*prin) (stream, ";");
|
|
else
|
|
{
|
|
if (strlen (op1) < 7)
|
|
(*prin) (stream, ";");
|
|
else
|
|
(*prin) (stream, "\t;");
|
|
}
|
|
}
|
|
if (*comm1)
|
|
(*prin) (stream, "%s", comm1);
|
|
if (*comm1 && *comm2)
|
|
(*prin) (stream, ",");
|
|
if (*comm2)
|
|
(*prin) (stream, " %s", comm2);
|
|
|
|
if (extension_word)
|
|
cmd_len += 2;
|
|
|
|
return cmd_len;
|
|
}
|