f5cdf4989e
These two statements were inverted by mistake in commit "Replace some xmalloc-family functions with XNEW-family ones". It obviously doesn't make sense to have them in this order, which is why I am pushing this as obvious. gdb/ChangeLog: * m88k-tdep.c (m88k_analyze_prologue): Fix inverted allocation statements.
877 lines
24 KiB
C
877 lines
24 KiB
C
/* Target-dependent code for the Motorola 88000 series.
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Copyright (C) 2004-2015 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "arch-utils.h"
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#include "dis-asm.h"
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#include "frame.h"
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#include "frame-base.h"
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#include "frame-unwind.h"
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#include "gdbcore.h"
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#include "gdbtypes.h"
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#include "regcache.h"
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#include "regset.h"
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#include "symtab.h"
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#include "trad-frame.h"
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#include "value.h"
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#include "m88k-tdep.h"
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/* Fetch the instruction at PC. */
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static unsigned long
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m88k_fetch_instruction (CORE_ADDR pc, enum bfd_endian byte_order)
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{
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return read_memory_unsigned_integer (pc, 4, byte_order);
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}
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/* Register information. */
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/* Return the name of register REGNUM. */
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static const char *
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m88k_register_name (struct gdbarch *gdbarch, int regnum)
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{
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static char *register_names[] =
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{
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
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"epsr", "fpsr", "fpcr", "sxip", "snip", "sfip"
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};
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if (regnum >= 0 && regnum < ARRAY_SIZE (register_names))
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return register_names[regnum];
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return NULL;
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}
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/* Return the GDB type object for the "standard" data type of data in
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register REGNUM. */
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static struct type *
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m88k_register_type (struct gdbarch *gdbarch, int regnum)
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{
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/* SXIP, SNIP, SFIP and R1 contain code addresses. */
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if ((regnum >= M88K_SXIP_REGNUM && regnum <= M88K_SFIP_REGNUM)
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|| regnum == M88K_R1_REGNUM)
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return builtin_type (gdbarch)->builtin_func_ptr;
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/* R30 and R31 typically contains data addresses. */
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if (regnum == M88K_R30_REGNUM || regnum == M88K_R31_REGNUM)
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return builtin_type (gdbarch)->builtin_data_ptr;
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return builtin_type (gdbarch)->builtin_int32;
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}
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static CORE_ADDR
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m88k_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
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{
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/* All instructures are 4-byte aligned. The lower 2 bits of SXIP,
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SNIP and SFIP are used for special purposes: bit 0 is the
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exception bit and bit 1 is the valid bit. */
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return addr & ~0x3;
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}
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/* Use the program counter to determine the contents and size of a
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breakpoint instruction. Return a pointer to a string of bytes that
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encode a breakpoint instruction, store the length of the string in
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*LEN and optionally adjust *PC to point to the correct memory
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location for inserting the breakpoint. */
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static const gdb_byte *
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m88k_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
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{
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/* tb 0,r0,511 */
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static gdb_byte break_insn[] = { 0xf0, 0x00, 0xd1, 0xff };
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*len = sizeof (break_insn);
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return break_insn;
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}
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static CORE_ADDR
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m88k_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
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{
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CORE_ADDR pc;
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pc = frame_unwind_register_unsigned (next_frame, M88K_SXIP_REGNUM);
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return m88k_addr_bits_remove (gdbarch, pc);
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}
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static void
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m88k_write_pc (struct regcache *regcache, CORE_ADDR pc)
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{
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/* According to the MC88100 RISC Microprocessor User's Manual,
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section 6.4.3.1.2:
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"... can be made to return to a particular instruction by placing
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a valid instruction address in the SNIP and the next sequential
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instruction address in the SFIP (with V bits set and E bits
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clear). The rte resumes execution at the instruction pointed to
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by the SNIP, then the SFIP."
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The E bit is the least significant bit (bit 0). The V (valid)
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bit is bit 1. This is why we logical or 2 into the values we are
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writing below. It turns out that SXIP plays no role when
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returning from an exception so nothing special has to be done
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with it. We could even (presumably) give it a totally bogus
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value. */
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regcache_cooked_write_unsigned (regcache, M88K_SXIP_REGNUM, pc);
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regcache_cooked_write_unsigned (regcache, M88K_SNIP_REGNUM, pc | 2);
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regcache_cooked_write_unsigned (regcache, M88K_SFIP_REGNUM, (pc + 4) | 2);
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}
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/* The functions on this page are intended to be used to classify
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function arguments. */
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/* Check whether TYPE is "Integral or Pointer". */
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static int
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m88k_integral_or_pointer_p (const struct type *type)
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{
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switch (TYPE_CODE (type))
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{
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case TYPE_CODE_INT:
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case TYPE_CODE_BOOL:
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case TYPE_CODE_CHAR:
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case TYPE_CODE_ENUM:
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case TYPE_CODE_RANGE:
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{
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/* We have byte, half-word, word and extended-word/doubleword
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integral types. */
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int len = TYPE_LENGTH (type);
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return (len == 1 || len == 2 || len == 4 || len == 8);
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}
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return 1;
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case TYPE_CODE_PTR:
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case TYPE_CODE_REF:
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{
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/* Allow only 32-bit pointers. */
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return (TYPE_LENGTH (type) == 4);
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}
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return 1;
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default:
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break;
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}
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return 0;
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}
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/* Check whether TYPE is "Floating". */
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static int
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m88k_floating_p (const struct type *type)
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{
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switch (TYPE_CODE (type))
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{
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case TYPE_CODE_FLT:
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{
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int len = TYPE_LENGTH (type);
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return (len == 4 || len == 8);
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}
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default:
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break;
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}
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return 0;
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}
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/* Check whether TYPE is "Structure or Union". */
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static int
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m88k_structure_or_union_p (const struct type *type)
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{
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switch (TYPE_CODE (type))
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{
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case TYPE_CODE_STRUCT:
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case TYPE_CODE_UNION:
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return 1;
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default:
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break;
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}
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return 0;
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}
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/* Check whether TYPE has 8-byte alignment. */
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static int
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m88k_8_byte_align_p (struct type *type)
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{
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if (m88k_structure_or_union_p (type))
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{
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int i;
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for (i = 0; i < TYPE_NFIELDS (type); i++)
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{
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struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
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if (m88k_8_byte_align_p (subtype))
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return 1;
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}
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}
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if (m88k_integral_or_pointer_p (type) || m88k_floating_p (type))
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return (TYPE_LENGTH (type) == 8);
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return 0;
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}
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/* Check whether TYPE can be passed in a register. */
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static int
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m88k_in_register_p (struct type *type)
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{
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if (m88k_integral_or_pointer_p (type) || m88k_floating_p (type))
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return 1;
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if (m88k_structure_or_union_p (type) && TYPE_LENGTH (type) == 4)
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return 1;
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return 0;
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}
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static CORE_ADDR
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m88k_store_arguments (struct regcache *regcache, int nargs,
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struct value **args, CORE_ADDR sp)
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{
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struct gdbarch *gdbarch = get_regcache_arch (regcache);
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int num_register_words = 0;
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int num_stack_words = 0;
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int i;
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for (i = 0; i < nargs; i++)
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{
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struct type *type = value_type (args[i]);
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int len = TYPE_LENGTH (type);
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if (m88k_integral_or_pointer_p (type) && len < 4)
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{
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args[i] = value_cast (builtin_type (gdbarch)->builtin_int32,
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args[i]);
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type = value_type (args[i]);
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len = TYPE_LENGTH (type);
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}
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if (m88k_in_register_p (type))
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{
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int num_words = 0;
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if (num_register_words % 2 == 1 && m88k_8_byte_align_p (type))
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num_words++;
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num_words += ((len + 3) / 4);
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if (num_register_words + num_words <= 8)
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{
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num_register_words += num_words;
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continue;
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}
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/* We've run out of available registers. Pass the argument
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on the stack. */
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}
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if (num_stack_words % 2 == 1 && m88k_8_byte_align_p (type))
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num_stack_words++;
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num_stack_words += ((len + 3) / 4);
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}
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/* Allocate stack space. */
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sp = align_down (sp - 32 - num_stack_words * 4, 16);
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num_stack_words = num_register_words = 0;
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for (i = 0; i < nargs; i++)
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{
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const bfd_byte *valbuf = value_contents (args[i]);
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struct type *type = value_type (args[i]);
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int len = TYPE_LENGTH (type);
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int stack_word = num_stack_words;
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if (m88k_in_register_p (type))
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{
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int register_word = num_register_words;
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if (register_word % 2 == 1 && m88k_8_byte_align_p (type))
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register_word++;
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gdb_assert (len == 4 || len == 8);
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if (register_word + len / 8 < 8)
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{
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int regnum = M88K_R2_REGNUM + register_word;
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regcache_raw_write (regcache, regnum, valbuf);
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if (len > 4)
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regcache_raw_write (regcache, regnum + 1, valbuf + 4);
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num_register_words = (register_word + len / 4);
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continue;
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}
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}
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if (stack_word % 2 == -1 && m88k_8_byte_align_p (type))
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stack_word++;
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write_memory (sp + stack_word * 4, valbuf, len);
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num_stack_words = (stack_word + (len + 3) / 4);
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}
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return sp;
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}
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static CORE_ADDR
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m88k_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
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struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
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struct value **args, CORE_ADDR sp, int struct_return,
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CORE_ADDR struct_addr)
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{
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/* Set up the function arguments. */
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sp = m88k_store_arguments (regcache, nargs, args, sp);
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gdb_assert (sp % 16 == 0);
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/* Store return value address. */
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if (struct_return)
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regcache_raw_write_unsigned (regcache, M88K_R12_REGNUM, struct_addr);
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/* Store the stack pointer and return address in the appropriate
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registers. */
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regcache_raw_write_unsigned (regcache, M88K_R31_REGNUM, sp);
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regcache_raw_write_unsigned (regcache, M88K_R1_REGNUM, bp_addr);
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/* Return the stack pointer. */
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return sp;
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}
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static struct frame_id
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m88k_dummy_id (struct gdbarch *arch, struct frame_info *this_frame)
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{
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CORE_ADDR sp;
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sp = get_frame_register_unsigned (this_frame, M88K_R31_REGNUM);
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return frame_id_build (sp, get_frame_pc (this_frame));
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}
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/* Determine, for architecture GDBARCH, how a return value of TYPE
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should be returned. If it is supposed to be returned in registers,
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and READBUF is non-zero, read the appropriate value from REGCACHE,
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and copy it into READBUF. If WRITEBUF is non-zero, write the value
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from WRITEBUF into REGCACHE. */
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static enum return_value_convention
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m88k_return_value (struct gdbarch *gdbarch, struct value *function,
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struct type *type, struct regcache *regcache,
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gdb_byte *readbuf, const gdb_byte *writebuf)
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{
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int len = TYPE_LENGTH (type);
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gdb_byte buf[8];
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if (!m88k_integral_or_pointer_p (type) && !m88k_floating_p (type))
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return RETURN_VALUE_STRUCT_CONVENTION;
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if (readbuf)
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{
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/* Read the contents of R2 and (if necessary) R3. */
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regcache_cooked_read (regcache, M88K_R2_REGNUM, buf);
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if (len > 4)
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{
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regcache_cooked_read (regcache, M88K_R3_REGNUM, buf + 4);
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gdb_assert (len == 8);
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memcpy (readbuf, buf, len);
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}
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else
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{
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/* Just stripping off any unused bytes should preserve the
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signed-ness just fine. */
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memcpy (readbuf, buf + 4 - len, len);
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}
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}
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if (writebuf)
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{
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/* Read the contents to R2 and (if necessary) R3. */
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if (len > 4)
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{
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gdb_assert (len == 8);
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memcpy (buf, writebuf, 8);
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regcache_cooked_write (regcache, M88K_R3_REGNUM, buf + 4);
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}
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else
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{
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/* ??? Do we need to do any sign-extension here? */
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memcpy (buf + 4 - len, writebuf, len);
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}
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regcache_cooked_write (regcache, M88K_R2_REGNUM, buf);
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}
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return RETURN_VALUE_REGISTER_CONVENTION;
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}
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/* Default frame unwinder. */
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struct m88k_frame_cache
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{
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/* Base address. */
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CORE_ADDR base;
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CORE_ADDR pc;
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int sp_offset;
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int fp_offset;
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/* Table of saved registers. */
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struct trad_frame_saved_reg *saved_regs;
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};
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/* Prologue analysis. */
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/* Macros for extracting fields from instructions. */
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#define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos))
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#define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width))
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#define SUBU_OFFSET(x) ((unsigned)(x & 0xFFFF))
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#define ST_OFFSET(x) ((unsigned)((x) & 0xFFFF))
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#define ST_SRC(x) EXTRACT_FIELD ((x), 21, 5)
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#define ADDU_OFFSET(x) ((unsigned)(x & 0xFFFF))
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/* Possible actions to be taken by the prologue analyzer for the
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instructions it encounters. */
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enum m88k_prologue_insn_action
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{
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M88K_PIA_SKIP, /* Ignore. */
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M88K_PIA_NOTE_ST, /* Note register store. */
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M88K_PIA_NOTE_STD, /* Note register pair store. */
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M88K_PIA_NOTE_SP_ADJUSTMENT, /* Note stack pointer adjustment. */
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M88K_PIA_NOTE_FP_ASSIGNMENT, /* Note frame pointer assignment. */
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M88K_PIA_NOTE_BRANCH, /* Note branch. */
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M88K_PIA_NOTE_PROLOGUE_END /* Note end of prologue. */
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};
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/* Table of instructions that may comprise a function prologue. */
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struct m88k_prologue_insn
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{
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unsigned long insn;
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unsigned long mask;
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enum m88k_prologue_insn_action action;
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};
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struct m88k_prologue_insn m88k_prologue_insn_table[] =
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{
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/* Various register move instructions. */
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{ 0x58000000, 0xf800ffff, M88K_PIA_SKIP }, /* or/or.u with immed of 0 */
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{ 0xf4005800, 0xfc1fffe0, M88K_PIA_SKIP }, /* or rd,r0,rs */
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{ 0xf4005800, 0xfc00ffff, M88K_PIA_SKIP }, /* or rd,rs,r0 */
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/* Various other instructions. */
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{ 0x58000000, 0xf8000000, M88K_PIA_SKIP }, /* or/or.u */
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/* Stack pointer setup: "subu sp,sp,n" where n is a multiple of 8. */
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{ 0x67ff0000, 0xffff0007, M88K_PIA_NOTE_SP_ADJUSTMENT },
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/* Frame pointer assignment: "addu r30,r31,n". */
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{ 0x63df0000, 0xffff0000, M88K_PIA_NOTE_FP_ASSIGNMENT },
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/* Store to stack instructions; either "st rx,sp,n" or "st.d rx,sp,n". */
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{ 0x241f0000, 0xfc1f0000, M88K_PIA_NOTE_ST }, /* st rx,sp,n */
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{ 0x201f0000, 0xfc1f0000, M88K_PIA_NOTE_STD }, /* st.d rs,sp,n */
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/* Instructions needed for setting up r25 for pic code. */
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{ 0x5f200000, 0xffff0000, M88K_PIA_SKIP }, /* or.u r25,r0,offset_high */
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{ 0xcc000002, 0xffffffff, M88K_PIA_SKIP }, /* bsr.n Lab */
|
||
{ 0x5b390000, 0xffff0000, M88K_PIA_SKIP }, /* or r25,r25,offset_low */
|
||
{ 0xf7396001, 0xffffffff, M88K_PIA_SKIP }, /* Lab: addu r25,r25,r1 */
|
||
|
||
/* Various branch or jump instructions which have a delay slot --
|
||
these do not form part of the prologue, but the instruction in
|
||
the delay slot might be a store instruction which should be
|
||
noted. */
|
||
{ 0xc4000000, 0xe4000000, M88K_PIA_NOTE_BRANCH },
|
||
/* br.n, bsr.n, bb0.n, or bb1.n */
|
||
{ 0xec000000, 0xfc000000, M88K_PIA_NOTE_BRANCH }, /* bcnd.n */
|
||
{ 0xf400c400, 0xfffff7e0, M88K_PIA_NOTE_BRANCH }, /* jmp.n or jsr.n */
|
||
|
||
/* Catch all. Ends prologue analysis. */
|
||
{ 0x00000000, 0x00000000, M88K_PIA_NOTE_PROLOGUE_END }
|
||
};
|
||
|
||
/* Do a full analysis of the function prologue at PC and update CACHE
|
||
accordingly. Bail out early if LIMIT is reached. Return the
|
||
address where the analysis stopped. If LIMIT points beyond the
|
||
function prologue, the return address should be the end of the
|
||
prologue. */
|
||
|
||
static CORE_ADDR
|
||
m88k_analyze_prologue (struct gdbarch *gdbarch,
|
||
CORE_ADDR pc, CORE_ADDR limit,
|
||
struct m88k_frame_cache *cache)
|
||
{
|
||
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
||
CORE_ADDR end = limit;
|
||
|
||
/* Provide a dummy cache if necessary. */
|
||
if (cache == NULL)
|
||
{
|
||
cache = XALLOCA (struct m88k_frame_cache);
|
||
cache->saved_regs =
|
||
XALLOCAVEC (struct trad_frame_saved_reg, M88K_R31_REGNUM + 1);
|
||
|
||
/* We only initialize the members we care about. */
|
||
cache->saved_regs[M88K_R1_REGNUM].addr = -1;
|
||
cache->fp_offset = -1;
|
||
}
|
||
|
||
while (pc < limit)
|
||
{
|
||
struct m88k_prologue_insn *pi = m88k_prologue_insn_table;
|
||
unsigned long insn = m88k_fetch_instruction (pc, byte_order);
|
||
|
||
while ((insn & pi->mask) != pi->insn)
|
||
pi++;
|
||
|
||
switch (pi->action)
|
||
{
|
||
case M88K_PIA_SKIP:
|
||
/* If we have a frame pointer, and R1 has been saved,
|
||
consider this instruction as not being part of the
|
||
prologue. */
|
||
if (cache->fp_offset != -1
|
||
&& cache->saved_regs[M88K_R1_REGNUM].addr != -1)
|
||
return min (pc, end);
|
||
break;
|
||
|
||
case M88K_PIA_NOTE_ST:
|
||
case M88K_PIA_NOTE_STD:
|
||
/* If no frame has been allocated, the stores aren't part of
|
||
the prologue. */
|
||
if (cache->sp_offset == 0)
|
||
return min (pc, end);
|
||
|
||
/* Record location of saved registers. */
|
||
{
|
||
int regnum = ST_SRC (insn) + M88K_R0_REGNUM;
|
||
ULONGEST offset = ST_OFFSET (insn);
|
||
|
||
cache->saved_regs[regnum].addr = offset;
|
||
if (pi->action == M88K_PIA_NOTE_STD && regnum < M88K_R31_REGNUM)
|
||
cache->saved_regs[regnum + 1].addr = offset + 4;
|
||
}
|
||
break;
|
||
|
||
case M88K_PIA_NOTE_SP_ADJUSTMENT:
|
||
/* A second stack pointer adjustment isn't part of the
|
||
prologue. */
|
||
if (cache->sp_offset != 0)
|
||
return min (pc, end);
|
||
|
||
/* Store stack pointer adjustment. */
|
||
cache->sp_offset = -SUBU_OFFSET (insn);
|
||
break;
|
||
|
||
case M88K_PIA_NOTE_FP_ASSIGNMENT:
|
||
/* A second frame pointer assignment isn't part of the
|
||
prologue. */
|
||
if (cache->fp_offset != -1)
|
||
return min (pc, end);
|
||
|
||
/* Record frame pointer assignment. */
|
||
cache->fp_offset = ADDU_OFFSET (insn);
|
||
break;
|
||
|
||
case M88K_PIA_NOTE_BRANCH:
|
||
/* The branch instruction isn't part of the prologue, but
|
||
the instruction in the delay slot might be. Limit the
|
||
prologue analysis to the delay slot and record the branch
|
||
instruction as the end of the prologue. */
|
||
limit = min (limit, pc + 2 * M88K_INSN_SIZE);
|
||
end = pc;
|
||
break;
|
||
|
||
case M88K_PIA_NOTE_PROLOGUE_END:
|
||
return min (pc, end);
|
||
}
|
||
|
||
pc += M88K_INSN_SIZE;
|
||
}
|
||
|
||
return end;
|
||
}
|
||
|
||
/* An upper limit to the size of the prologue. */
|
||
const int m88k_max_prologue_size = 128 * M88K_INSN_SIZE;
|
||
|
||
/* Return the address of first real instruction of the function
|
||
starting at PC. */
|
||
|
||
static CORE_ADDR
|
||
m88k_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
|
||
{
|
||
struct symtab_and_line sal;
|
||
CORE_ADDR func_start, func_end;
|
||
|
||
/* This is the preferred method, find the end of the prologue by
|
||
using the debugging information. */
|
||
if (find_pc_partial_function (pc, NULL, &func_start, &func_end))
|
||
{
|
||
sal = find_pc_line (func_start, 0);
|
||
|
||
if (sal.end < func_end && pc <= sal.end)
|
||
return sal.end;
|
||
}
|
||
|
||
return m88k_analyze_prologue (gdbarch, pc, pc + m88k_max_prologue_size,
|
||
NULL);
|
||
}
|
||
|
||
static struct m88k_frame_cache *
|
||
m88k_frame_cache (struct frame_info *this_frame, void **this_cache)
|
||
{
|
||
struct gdbarch *gdbarch = get_frame_arch (this_frame);
|
||
struct m88k_frame_cache *cache;
|
||
CORE_ADDR frame_sp;
|
||
|
||
if (*this_cache)
|
||
return *this_cache;
|
||
|
||
cache = FRAME_OBSTACK_ZALLOC (struct m88k_frame_cache);
|
||
cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
|
||
cache->fp_offset = -1;
|
||
|
||
cache->pc = get_frame_func (this_frame);
|
||
if (cache->pc != 0)
|
||
m88k_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
|
||
cache);
|
||
|
||
/* Calculate the stack pointer used in the prologue. */
|
||
if (cache->fp_offset != -1)
|
||
{
|
||
CORE_ADDR fp;
|
||
|
||
fp = get_frame_register_unsigned (this_frame, M88K_R30_REGNUM);
|
||
frame_sp = fp - cache->fp_offset;
|
||
}
|
||
else
|
||
{
|
||
/* If we know where the return address is saved, we can take a
|
||
solid guess at what the frame pointer should be. */
|
||
if (cache->saved_regs[M88K_R1_REGNUM].addr != -1)
|
||
cache->fp_offset = cache->saved_regs[M88K_R1_REGNUM].addr - 4;
|
||
frame_sp = get_frame_register_unsigned (this_frame, M88K_R31_REGNUM);
|
||
}
|
||
|
||
/* Now that we know the stack pointer, adjust the location of the
|
||
saved registers. */
|
||
{
|
||
int regnum;
|
||
|
||
for (regnum = M88K_R0_REGNUM; regnum < M88K_R31_REGNUM; regnum ++)
|
||
if (cache->saved_regs[regnum].addr != -1)
|
||
cache->saved_regs[regnum].addr += frame_sp;
|
||
}
|
||
|
||
/* Calculate the frame's base. */
|
||
cache->base = frame_sp - cache->sp_offset;
|
||
trad_frame_set_value (cache->saved_regs, M88K_R31_REGNUM, cache->base);
|
||
|
||
/* Identify SXIP with the return address in R1. */
|
||
cache->saved_regs[M88K_SXIP_REGNUM] = cache->saved_regs[M88K_R1_REGNUM];
|
||
|
||
*this_cache = cache;
|
||
return cache;
|
||
}
|
||
|
||
static void
|
||
m88k_frame_this_id (struct frame_info *this_frame, void **this_cache,
|
||
struct frame_id *this_id)
|
||
{
|
||
struct m88k_frame_cache *cache = m88k_frame_cache (this_frame, this_cache);
|
||
|
||
/* This marks the outermost frame. */
|
||
if (cache->base == 0)
|
||
return;
|
||
|
||
(*this_id) = frame_id_build (cache->base, cache->pc);
|
||
}
|
||
|
||
static struct value *
|
||
m88k_frame_prev_register (struct frame_info *this_frame,
|
||
void **this_cache, int regnum)
|
||
{
|
||
struct m88k_frame_cache *cache = m88k_frame_cache (this_frame, this_cache);
|
||
|
||
if (regnum == M88K_SNIP_REGNUM || regnum == M88K_SFIP_REGNUM)
|
||
{
|
||
struct value *value;
|
||
CORE_ADDR pc;
|
||
|
||
value = trad_frame_get_prev_register (this_frame, cache->saved_regs,
|
||
M88K_SXIP_REGNUM);
|
||
pc = value_as_long (value);
|
||
release_value (value);
|
||
value_free (value);
|
||
|
||
if (regnum == M88K_SFIP_REGNUM)
|
||
pc += 4;
|
||
|
||
return frame_unwind_got_constant (this_frame, regnum, pc + 4);
|
||
}
|
||
|
||
return trad_frame_get_prev_register (this_frame, cache->saved_regs, regnum);
|
||
}
|
||
|
||
static const struct frame_unwind m88k_frame_unwind =
|
||
{
|
||
NORMAL_FRAME,
|
||
default_frame_unwind_stop_reason,
|
||
m88k_frame_this_id,
|
||
m88k_frame_prev_register,
|
||
NULL,
|
||
default_frame_sniffer
|
||
};
|
||
|
||
|
||
static CORE_ADDR
|
||
m88k_frame_base_address (struct frame_info *this_frame, void **this_cache)
|
||
{
|
||
struct m88k_frame_cache *cache = m88k_frame_cache (this_frame, this_cache);
|
||
|
||
if (cache->fp_offset != -1)
|
||
return cache->base + cache->sp_offset + cache->fp_offset;
|
||
|
||
return 0;
|
||
}
|
||
|
||
static const struct frame_base m88k_frame_base =
|
||
{
|
||
&m88k_frame_unwind,
|
||
m88k_frame_base_address,
|
||
m88k_frame_base_address,
|
||
m88k_frame_base_address
|
||
};
|
||
|
||
|
||
/* Core file support. */
|
||
|
||
/* Supply register REGNUM from the buffer specified by GREGS and LEN
|
||
in the general-purpose register set REGSET to register cache
|
||
REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
|
||
|
||
static void
|
||
m88k_supply_gregset (const struct regset *regset,
|
||
struct regcache *regcache,
|
||
int regnum, const void *gregs, size_t len)
|
||
{
|
||
const gdb_byte *regs = gregs;
|
||
int i;
|
||
|
||
for (i = 0; i < M88K_NUM_REGS; i++)
|
||
{
|
||
if (regnum == i || regnum == -1)
|
||
regcache_raw_supply (regcache, i, regs + i * 4);
|
||
}
|
||
}
|
||
|
||
/* Motorola 88000 register set. */
|
||
|
||
static const struct regset m88k_gregset =
|
||
{
|
||
NULL,
|
||
m88k_supply_gregset
|
||
};
|
||
|
||
/* Iterate over supported core file register note sections. */
|
||
|
||
static void
|
||
m88k_iterate_over_regset_sections (struct gdbarch *gdbarch,
|
||
iterate_over_regset_sections_cb *cb,
|
||
void *cb_data,
|
||
const struct regcache *regcache)
|
||
{
|
||
cb (".reg", M88K_NUM_REGS * 4, &m88k_gregset, NULL, cb_data);
|
||
}
|
||
|
||
|
||
static struct gdbarch *
|
||
m88k_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
|
||
{
|
||
struct gdbarch *gdbarch;
|
||
|
||
/* If there is already a candidate, use it. */
|
||
arches = gdbarch_list_lookup_by_info (arches, &info);
|
||
if (arches != NULL)
|
||
return arches->gdbarch;
|
||
|
||
/* Allocate space for the new architecture. */
|
||
gdbarch = gdbarch_alloc (&info, NULL);
|
||
|
||
/* There is no real `long double'. */
|
||
set_gdbarch_long_double_bit (gdbarch, 64);
|
||
set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
|
||
|
||
set_gdbarch_num_regs (gdbarch, M88K_NUM_REGS);
|
||
set_gdbarch_register_name (gdbarch, m88k_register_name);
|
||
set_gdbarch_register_type (gdbarch, m88k_register_type);
|
||
|
||
/* Register numbers of various important registers. */
|
||
set_gdbarch_sp_regnum (gdbarch, M88K_R31_REGNUM);
|
||
set_gdbarch_pc_regnum (gdbarch, M88K_SXIP_REGNUM);
|
||
|
||
/* Core file support. */
|
||
set_gdbarch_iterate_over_regset_sections
|
||
(gdbarch, m88k_iterate_over_regset_sections);
|
||
|
||
set_gdbarch_print_insn (gdbarch, print_insn_m88k);
|
||
|
||
set_gdbarch_skip_prologue (gdbarch, m88k_skip_prologue);
|
||
|
||
/* Stack grows downward. */
|
||
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
|
||
|
||
/* Call dummy code. */
|
||
set_gdbarch_push_dummy_call (gdbarch, m88k_push_dummy_call);
|
||
set_gdbarch_dummy_id (gdbarch, m88k_dummy_id);
|
||
|
||
/* Return value info. */
|
||
set_gdbarch_return_value (gdbarch, m88k_return_value);
|
||
|
||
set_gdbarch_addr_bits_remove (gdbarch, m88k_addr_bits_remove);
|
||
set_gdbarch_breakpoint_from_pc (gdbarch, m88k_breakpoint_from_pc);
|
||
set_gdbarch_unwind_pc (gdbarch, m88k_unwind_pc);
|
||
set_gdbarch_write_pc (gdbarch, m88k_write_pc);
|
||
|
||
frame_base_set_default (gdbarch, &m88k_frame_base);
|
||
frame_unwind_append_unwinder (gdbarch, &m88k_frame_unwind);
|
||
|
||
return gdbarch;
|
||
}
|
||
|
||
|
||
/* Provide a prototype to silence -Wmissing-prototypes. */
|
||
void _initialize_m88k_tdep (void);
|
||
|
||
void
|
||
_initialize_m88k_tdep (void)
|
||
{
|
||
gdbarch_register (bfd_arch_m88k, m88k_gdbarch_init, NULL);
|
||
}
|