6dbaff8f60
Use in d30v and tic80. Make available a generic sim_read, sim_write implementation.
162 lines
No EOL
3.9 KiB
Makefile
162 lines
No EOL
3.9 KiB
Makefile
# Makefile for blah ...
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# Copyright blah ...
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## COMMON_PRE_CONFIG_FRAG
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# These variables are given default values in COMMON_PRE_CONFIG_FRAG.
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# We override the ones we need to here.
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# Not all of these need to be mentioned, only the necessary ones.
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# List of object files, less common parts.
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SIM_OBJS = sim-endian.o sim-bits.o sim-config.o \
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support.o idecode.o semantics.o itable.o misc.o \
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sim-calls.o \
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sim-events.o \
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sim-core.o \
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sim-hload.o \
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sim-hrw.o \
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sim-io.o \
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sim-utils.o \
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sim-load.o \
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sim-memopt.o \
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sim-module.o \
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sim-options.o \
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sim-trace.o \
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sim-profile.o \
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sim-fpu.o \
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sim-engine.o \
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sim-run.o \
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sim-resume.o \
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sim-stop.o \
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sim-reason.o \
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sim-watch.o
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# List of extra dependencies.
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# Generally this consists of simulator specific files included by sim-main.h.
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SIM_EXTRA_DEPS = itable.h idecode.h cpu.h alu.h
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# List of extra libraries to link with
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SIM_EXTRA_LIBS = -lm
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# List of generators
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SIM_GEN=tmp-igen
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# List of flags to always pass to $(CC).
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SIM_WARNINGS=@sim_warnings@
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SIM_ENDIAN=@sim_endian@
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SIM_HOSTENDIAN=@sim_hostendian@
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SIM_INLINE=@sim_inline@
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SIM_RESERVED_BITS=@sim_reserved_bits@
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SIM_ALIGNMENT=@sim_alignment@
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SIM_EXTRA_CFLAGS = \
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$(SIM_WARNINGS) \
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$(SIM_ENDIAN) \
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$(SIM_HOSTENDIAN) \
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$(SIM_INLINE) \
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$(SIM_RESERVED_BITS) \
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-DWITH_TARGET_WORD_MSB=31
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# List of main object files for `run'.
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SIM_RUN_OBJS = nrun.o
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# Dependency of `clean' to clean any extra files.
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SIM_EXTRA_CLEAN = clean-igen
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## COMMON_POST_CONFIG_FRAG
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# Rules need to build $(SIM_OBJS), plus whatever else the target wants.
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# ... target specific rules ...
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BUILT_SRC_FROM_IGEN = \
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icache.h \
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icache.c \
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idecode.h \
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idecode.c \
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semantics.h \
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semantics.c \
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model.h \
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model.c \
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support.h \
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support.c \
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itable.h itable.c
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$(BUILT_SRC_FROM_IGEN): tmp-igen
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#
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.PHONY: clean-igen
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clean-igen:
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rm -f $(BUILT_SRC_FROM_IGEN)
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rm -f tmp-igen tmp-insns
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../igen/igen:
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cd ../igen && $(MAKE)
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tmp-igen: $(srcdir)/dc $(srcdir)/insns $(srcdir)/ic ../igen/igen
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cd ../igen && $(MAKE)
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../igen/igen \
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-F f \
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-G direct-access \
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-G delayed-branch \
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-G zero-r0 \
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-F short,emul \
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-B 32 -H 31 \
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-o $(srcdir)/dc \
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-k $(srcdir)/ic \
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-i $(srcdir)/insns \
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-n icache.h -hc tmp-icache.h \
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-n icache.c -c tmp-icache.c \
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-n semantics.h -hs tmp-semantics.h \
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-n semantics.c -s tmp-semantics.c \
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-n idecode.h -hd tmp-idecode.h \
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-n idecode.c -d tmp-idecode.c \
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-n model.h -hm tmp-model.h \
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-n model.c -m tmp-model.c \
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-n support.h -hf tmp-support.h \
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-n support.c -f tmp-support.c \
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-n itable.h -ht tmp-itable.h \
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-n itable.c -t tmp-itable.c
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$(srcdir)/../../move-if-change tmp-icache.h icache.h
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$(srcdir)/../../move-if-change tmp-icache.c icache.c
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$(srcdir)/../../move-if-change tmp-idecode.h idecode.h
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$(srcdir)/../../move-if-change tmp-idecode.c idecode.c
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$(srcdir)/../../move-if-change tmp-semantics.h semantics.h
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$(srcdir)/../../move-if-change tmp-semantics.c semantics.c
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$(srcdir)/../../move-if-change tmp-model.h model.h
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$(srcdir)/../../move-if-change tmp-model.c model.c
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$(srcdir)/../../move-if-change tmp-support.h support.h
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$(srcdir)/../../move-if-change tmp-support.c support.c
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$(srcdir)/../../move-if-change tmp-itable.h itable.h
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$(srcdir)/../../move-if-change tmp-itable.c itable.c
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touch tmp-igen
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ENGINE_H = \
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sim-main.h \
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$(srcdir)/../common/sim-basics.h \
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config.h \
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$(srcdir)/../common/sim-config.h \
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$(srcdir)/../common/sim-inline.h \
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$(srcdir)/../common/sim-types.h \
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$(srcdir)/../common/sim-bits.h \
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$(srcdir)/../common/sim-endian.h \
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$(srcdir)/../common/sim-options.h \
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itable.h \
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idecode.h \
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cpu.h \
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alu.h \
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$(srcdir)/../common/sim-alu.h \
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$(srcdir)/../common/sim-core.h \
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$(srcdir)/../common/sim-events.h \
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$(srcdir)/../common/sim-fpu.h \
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$(srcdir)/../common/sim-engine.h \
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idecode.o: $(ENGINE_H)
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semantics.o: $(ENGINE_H)
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support.o: $(ENGINE_H)
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interp.o: interp.c $(ENGINE_H)
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sim-calls.o: sim-calls.c $(ENGINE_H)
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cpu.o: cpu.c $(ENGINE_H)
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misc.o: $(ENGINE_H) |