520 lines
15 KiB
Makefile
520 lines
15 KiB
Makefile
# Makefile template for Configure for the MIPS simulator.
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# Written by Cygnus Support.
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## COMMON_PRE_CONFIG_FRAG
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srcdir=@srcdir@
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srcroot=$(srcdir)/../../
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SIM_NO_OBJ =
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# start-sanitize-sky
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SIM_SKY_OBJS = \
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sky-console.o \
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sky-device.o \
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sky-dma.o \
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sky-engine.o \
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sky-interact.o \
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sky-gpuif.o \
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sky-hardware.o \
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sky-indebug.o \
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sky-libvpe.o \
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sky-vif.o \
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sky-psio.o \
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sky-vu.o \
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sky-vudis.o \
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sky-gs.o \
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sky-gdb.o
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# end-sanitize-sky
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SIM_IGEN_OBJ = \
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support.o \
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itable.o \
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semantics.o \
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idecode.o \
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icache.o \
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@mips_igen_engine@ \
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irun.o \
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SIM_M16_OBJ = \
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m16_support.o \
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m16_semantics.o \
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m16_idecode.o \
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m16_icache.o \
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\
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m32_support.o \
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m32_semantics.o \
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m32_idecode.o \
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m32_icache.o \
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\
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itable.o \
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m16run.o \
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MIPS_EXTRA_OBJS = @mips_extra_objs@
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MIPS_EXTRA_LIBS = @mips_extra_libs@
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SIM_OBJS = \
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$(SIM_@sim_gen@_OBJ) \
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$(SIM_NEW_COMMON_OBJS) \
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$(MIPS_EXTRA_OBJS) \
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interp.o \
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sim-main.o \
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sim-hload.o \
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sim-engine.o \
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sim-stop.o \
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sim-resume.o \
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sim-reason.o \
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# List of flags to always pass to $(CC).
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SIM_SUBTARGET=@SIM_SUBTARGET@
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# FIXME: Hack to find syscall.h? Better support for syscall.h
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# is in progress.
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SIM_EXTRA_CFLAGS = \
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$(SIM_SUBTARGET) \
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-I$(srcdir)/../../newlib/libc/sys/idt
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SIM_EXTRA_CLEAN = clean-extra
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SIM_EXTRA_ALL = $(SIM_@sim_gen@_ALL)
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SIM_EXTRA_LIBS = $(MIPS_EXTRA_LIBS)
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# List of main object files for `run'.
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SIM_RUN_OBJS = nrun.o
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## COMMON_POST_CONFIG_FRAG
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SIM_NO_INTERP = oengine.c
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interp.o: $(srcdir)/interp.c config.h sim-main.h $(SIM_@sim_gen@_INTERP)
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../igen/igen:
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cd ../igen && $(MAKE)
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IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
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IGEN_INSN=$(srcdir)/mips.igen
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IGEN_DC=$(srcdir)/mips.dc
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M16_DC=$(srcdir)/m16.dc
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IGEN_INCLUDE=\
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$(start-sanitize-r5900) \
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$(srcdir)/r5900.igen \
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$(end-sanitize-r5900) \
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$(start-sanitize-cygnus) \
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$(srcdir)/mdmx.igen \
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$(end-sanitize-cygnus) \
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$(srcdir)/m16.igen \
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$(srcdir)/tx.igen \
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$(srcdir)/vr.igen \
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SIM_IGEN_ALL = tmp-igen
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BUILT_SRC_FROM_IGEN = \
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icache.h \
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icache.c \
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idecode.h \
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idecode.c \
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semantics.h \
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semantics.c \
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model.h \
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model.c \
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support.h \
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support.c \
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engine.h \
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engine.c \
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irun.c \
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# NB: Since these can be built by either tmp-igen or tmp-m16
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# they are explicitly marked as being dependant on the
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# dependant on the selected generator.
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BUILT_SRC_FROM_GEN = \
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itable.h \
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itable.c \
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$(BUILT_SRC_FROM_GEN): $(SIM_@sim_gen@_ALL)
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$(BUILT_SRC_FROM_IGEN): tmp-igen
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tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
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cd ../igen && $(MAKE)
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../igen/igen \
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$(IGEN_TRACE) \
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-I $(srcdir) \
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-Werror \
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-Wnodiscard \
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@sim_igen_flags@ \
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-G gen-direct-access \
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-G gen-zero-r0 \
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-B 32 \
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-H 31 \
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-i $(IGEN_INSN) \
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-o $(IGEN_DC) \
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-x \
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-n icache.h -hc tmp-icache.h \
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-n icache.c -c tmp-icache.c \
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-n semantics.h -hs tmp-semantics.h \
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-n semantics.c -s tmp-semantics.c \
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-n idecode.h -hd tmp-idecode.h \
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-n idecode.c -d tmp-idecode.c \
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-n model.h -hm tmp-model.h \
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-n model.c -m tmp-model.c \
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-n support.h -hf tmp-support.h \
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-n support.c -f tmp-support.c \
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-n itable.h -ht tmp-itable.h \
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-n itable.c -t tmp-itable.c \
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-n engine.h -he tmp-engine.h \
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-n engine.c -e tmp-engine.c \
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-n irun.c -r tmp-irun.c
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$(srcdir)/../../move-if-change tmp-icache.h icache.h
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$(srcdir)/../../move-if-change tmp-icache.c icache.c
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$(srcdir)/../../move-if-change tmp-idecode.h idecode.h
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$(srcdir)/../../move-if-change tmp-idecode.c idecode.c
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$(srcdir)/../../move-if-change tmp-semantics.h semantics.h
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$(srcdir)/../../move-if-change tmp-semantics.c semantics.c
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$(srcdir)/../../move-if-change tmp-model.h model.h
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$(srcdir)/../../move-if-change tmp-model.c model.c
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$(srcdir)/../../move-if-change tmp-support.h support.h
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$(srcdir)/../../move-if-change tmp-support.c support.c
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$(srcdir)/../../move-if-change tmp-itable.h itable.h
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$(srcdir)/../../move-if-change tmp-itable.c itable.c
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$(srcdir)/../../move-if-change tmp-engine.h engine.h
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$(srcdir)/../../move-if-change tmp-engine.c engine.c
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$(srcdir)/../../move-if-change tmp-irun.c irun.c
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touch tmp-igen
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semantics.o: sim-main.h semantics.c $(SIM_EXTRA_DEPS)
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engine.o: sim-main.h engine.c $(SIM_EXTRA_DEPS)
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support.o: sim-main.h support.c $(SIM_EXTRA_DEPS)
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idecode.o: sim-main.h idecode.c $(SIM_EXTRA_DEPS)
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itable.o: sim-main.h itable.c $(SIM_EXTRA_DEPS)
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SIM_M16_ALL = tmp-m16
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BUILT_SRC_FROM_M16 = \
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m16_icache.h \
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m16_icache.c \
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m16_idecode.h \
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m16_idecode.c \
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m16_semantics.h \
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m16_semantics.c \
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m16_model.h \
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m16_model.c \
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m16_support.h \
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m16_support.c \
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\
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m32_icache.h \
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m32_icache.c \
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m32_idecode.h \
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m32_idecode.c \
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m32_semantics.h \
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m32_semantics.c \
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m32_model.h \
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m32_model.c \
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m32_support.h \
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m32_support.c \
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$(BUILT_SRC_FROM_M16): tmp-m16
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tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
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cd ../igen && $(MAKE)
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../igen/igen \
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$(IGEN_TRACE) \
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-I $(srcdir) \
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-Werror \
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-Wnodiscard \
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@sim_m16_flags@ \
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-G gen-direct-access \
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-G gen-zero-r0 \
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-B 16 \
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-H 15 \
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-i $(IGEN_INSN) \
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-o $(M16_DC) \
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-P m16_ \
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-x \
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-n m16_icache.h -hc tmp-icache.h \
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-n m16_icache.c -c tmp-icache.c \
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-n m16_semantics.h -hs tmp-semantics.h \
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-n m16_semantics.c -s tmp-semantics.c \
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-n m16_idecode.h -hd tmp-idecode.h \
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-n m16_idecode.c -d tmp-idecode.c \
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-n m16_model.h -hm tmp-model.h \
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-n m16_model.c -m tmp-model.c \
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-n m16_support.h -hf tmp-support.h \
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-n m16_support.c -f tmp-support.c \
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#
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$(srcdir)/../../move-if-change tmp-icache.h m16_icache.h
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$(srcdir)/../../move-if-change tmp-icache.c m16_icache.c
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$(srcdir)/../../move-if-change tmp-idecode.h m16_idecode.h
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$(srcdir)/../../move-if-change tmp-idecode.c m16_idecode.c
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$(srcdir)/../../move-if-change tmp-semantics.h m16_semantics.h
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$(srcdir)/../../move-if-change tmp-semantics.c m16_semantics.c
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$(srcdir)/../../move-if-change tmp-model.h m16_model.h
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$(srcdir)/../../move-if-change tmp-model.c m16_model.c
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$(srcdir)/../../move-if-change tmp-support.h m16_support.h
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$(srcdir)/../../move-if-change tmp-support.c m16_support.c
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../igen/igen \
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$(IGEN_TRACE) \
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-I $(srcdir) \
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-Werror \
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-Wnodiscard \
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@sim_igen_flags@ \
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-G gen-direct-access \
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-G gen-zero-r0 \
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-B 32 \
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-H 31 \
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-i $(IGEN_INSN) \
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-o $(IGEN_DC) \
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-P m32_ \
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-x \
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-n m32_icache.h -hc tmp-icache.h \
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-n m32_icache.c -c tmp-icache.c \
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-n m32_semantics.h -hs tmp-semantics.h \
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-n m32_semantics.c -s tmp-semantics.c \
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-n m32_idecode.h -hd tmp-idecode.h \
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-n m32_idecode.c -d tmp-idecode.c \
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-n m32_model.h -hm tmp-model.h \
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-n m32_model.c -m tmp-model.c \
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-n m32_support.h -hf tmp-support.h \
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-n m32_support.c -f tmp-support.c \
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#
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$(srcdir)/../../move-if-change tmp-icache.h m32_icache.h
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$(srcdir)/../../move-if-change tmp-icache.c m32_icache.c
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$(srcdir)/../../move-if-change tmp-idecode.h m32_idecode.h
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$(srcdir)/../../move-if-change tmp-idecode.c m32_idecode.c
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$(srcdir)/../../move-if-change tmp-semantics.h m32_semantics.h
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$(srcdir)/../../move-if-change tmp-semantics.c m32_semantics.c
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$(srcdir)/../../move-if-change tmp-model.h m32_model.h
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$(srcdir)/../../move-if-change tmp-model.c m32_model.c
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$(srcdir)/../../move-if-change tmp-support.h m32_support.h
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$(srcdir)/../../move-if-change tmp-support.c m32_support.c
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../igen/igen \
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$(IGEN_TRACE) \
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-I $(srcdir) \
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-Werror \
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-Wnodiscard \
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-Wnowidth \
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@sim_igen_flags@ @sim_m16_flags@ \
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-G gen-direct-access \
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-G gen-zero-r0 \
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-i $(IGEN_INSN) \
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-n itable.h -ht tmp-itable.h \
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-n itable.c -t tmp-itable.c \
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#
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$(srcdir)/../../move-if-change tmp-itable.h itable.h
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$(srcdir)/../../move-if-change tmp-itable.c itable.c
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touch tmp-m16
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clean-extra:
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rm -f gencode oengine.c tmp.igen
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rm -f $(BUILT_SRC_FROM_GEN)
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rm -f $(BUILT_SRC_FROM_IGEN)
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rm -f $(BUILT_SRC_FROM_M16)
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rm -f tmp-*
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rm -f libhack.a hack
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rm -f m16* m32* itable*
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# start-sanitize-vr4xxx
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# HACK ....
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SIM_HACK_OBJ = \
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itable.o \
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m16vr4111_icache.o m16vr4111_idecode.o m16vr4111_model.o \
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m16vr4111_run.o m16vr4111_semantics.o m16vr4111_support.o \
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m16vr4121_icache.o m16vr4121_idecode.o m16vr4121_model.o \
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m16vr4121_run.o m16vr4121_semantics.o m16vr4121_support.o \
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m32mipsIV_engine.o m32mipsIV_icache.o m32mipsIV_idecode.o \
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m32mipsIV_model.o m32mipsIV_semantics.o m32mipsIV_support.o \
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m32vr4100_engine.o m32vr4100_icache.o m32vr4100_idecode.o \
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m32vr4100_model.o m32vr4100_semantics.o m32vr4100_support.o \
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m32vr4111_engine.o m32vr4111_icache.o m32vr4111_idecode.o \
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m32vr4111_model.o m32vr4111_semantics.o m32vr4111_support.o \
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m32vr4320_engine.o m32vr4320_icache.o m32vr4320_idecode.o \
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m32vr4320_model.o m32vr4320_semantics.o m32vr4320_support.o \
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m32vr4121_engine.o m32vr4121_icache.o m32vr4121_idecode.o \
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m32vr4121_model.o m32vr4121_semantics.o m32vr4121_support.o \
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vr4run.o
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HACK_OBJS = \
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itable.o m16vr4111_icache.o m16vr4111_idecode.o \
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m16vr4111_model.o m16vr4111_run.o m16vr4111_semantics.o \
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m16vr4111_support.o m16vr4121_icache.o m16vr4121_idecode.o \
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m16vr4121_model.o m16vr4121_run.o m16vr4121_semantics.o \
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m16vr4121_support.o m32mipsIV_engine.o m32mipsIV_icache.o \
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m32mipsIV_idecode.o m32mipsIV_model.o m32mipsIV_semantics.o \
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m32mipsIV_support.o m32vr4100_engine.o m32vr4100_icache.o \
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m32vr4100_idecode.o m32vr4100_model.o m32vr4100_semantics.o \
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m32vr4100_support.o m32vr4111_engine.o m32vr4111_icache.o \
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m32vr4111_idecode.o m32vr4111_model.o m32vr4111_semantics.o \
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m32vr4111_support.o m32vr4320_engine.o m32vr4320_icache.o \
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m32vr4320_idecode.o m32vr4320_model.o m32vr4320_semantics.o \
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m32vr4320_support.o m32vr4121_engine.o m32vr4121_icache.o \
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m32vr4121_idecode.o m32vr4121_model.o m32vr4121_semantics.o \
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m32vr4121_support.o \
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$(SIM_NEW_COMMON_OBJS) \
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$(MIPS_EXTRA_OBJS) \
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interp.o \
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sim-main.o \
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sim-hload.o \
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sim-engine.o \
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sim-stop.o \
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sim-resume.o \
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sim-reason.o \
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callback.o syscall.o targ-map.o \
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vr4run.o
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HACK_GEN_SRCS = \
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itable.c \
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m16vr4111_icache.c m16vr4111_idecode.c m16vr4111_model.c \
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m16vr4111_run.c m16vr4111_semantics.c m16vr4111_support.c \
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m16vr4121_icache.c m16vr4121_idecode.c m16vr4121_model.c \
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m16vr4121_run.c m16vr4121_semantics.c m16vr4121_support.c \
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m32mipsIV_engine.c m32mipsIV_icache.c m32mipsIV_idecode.c \
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m32mipsIV_model.c m32mipsIV_semantics.c m32mipsIV_support.c \
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m32vr4100_engine.c m32vr4100_icache.c m32vr4100_idecode.c \
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m32vr4100_model.c m32vr4100_semantics.c m32vr4100_support.c \
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m32vr4111_engine.c m32vr4111_icache.c m32vr4111_idecode.c \
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m32vr4111_model.c m32vr4111_semantics.c m32vr4111_support.c \
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m32vr4320_engine.c m32vr4320_icache.c m32vr4320_idecode.c \
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m32vr4320_model.c m32vr4320_semantics.c m32vr4320_support.c \
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m32vr4121_engine.c m32vr4121_icache.c m32vr4121_idecode.c \
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m32vr4121_model.c m32vr4121_semantics.c m32vr4121_support.c
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$(HACK_GEN_SRCS): tmp-hack
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libhack.a: $(HACK_OBJS)
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rm -f libhack.a
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$(AR) $(AR_FLAGS) libhack.a $(HACK_OBJS)
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$(RANLIB) libhack.a
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hack: tmp-hack $(SIM_RUN_OBJS) libhack.a
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$(CC) $(ALL_CFLAGS) -o hack$(EXEEXT) \
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$(SIM_RUN_OBJS) libhack.a $(EXTRA_LIBS)
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tmp-hack: tmp-m16-hack tmp-m32-hack tmp-itable-hack tmp-run-hack targ-vals.h
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tmp-m32-hack: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
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for t in m32mipsIV:mipsIV m32vr4100:vr4100 m32vr4111:vr4100 m32vr4320:vr4320 m32vr4121:vr4121 ; \
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do \
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p=`echo $${t} | sed -e 's/:.*//'` ; \
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m=`echo $${t} | sed -e 's/.*://'` ; \
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../igen/igen \
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$(IGEN_TRACE) \
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-I $(srcdir) \
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-Werror \
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-Wnodiscard \
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-N 0 \
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-M $${m} -F 32,64,f \
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-G gen-direct-access \
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-G gen-zero-r0 \
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-B 32 \
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-H 31 \
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-i $(IGEN_INSN) \
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-o $(IGEN_DC) \
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-P $${p}_ \
|
|
-x \
|
|
-n $${p}_icache.h -hc tmp-icache.h \
|
|
-n $${p}_icache.c -c tmp-icache.c \
|
|
-n $${p}_semantics.h -hs tmp-semantics.h \
|
|
-n $${p}_semantics.c -s tmp-semantics.c \
|
|
-n $${p}_idecode.h -hd tmp-idecode.h \
|
|
-n $${p}_idecode.c -d tmp-idecode.c \
|
|
-n $${p}_model.h -hm tmp-model.h \
|
|
-n $${p}_model.c -m tmp-model.c \
|
|
-n $${p}_support.h -hf tmp-support.h \
|
|
-n $${p}_support.c -f tmp-support.c \
|
|
-n $${p}_engine.h -he tmp-engine.h \
|
|
-n $${p}_engine.c -e tmp-engine.c \
|
|
; \
|
|
$(srcdir)/../../move-if-change tmp-icache.h $${p}_icache.h ; \
|
|
$(srcdir)/../../move-if-change tmp-icache.c $${p}_icache.c ; \
|
|
$(srcdir)/../../move-if-change tmp-idecode.h $${p}_idecode.h ; \
|
|
$(srcdir)/../../move-if-change tmp-idecode.c $${p}_idecode.c ; \
|
|
$(srcdir)/../../move-if-change tmp-semantics.h $${p}_semantics.h ; \
|
|
$(srcdir)/../../move-if-change tmp-semantics.c $${p}_semantics.c ; \
|
|
$(srcdir)/../../move-if-change tmp-model.h $${p}_model.h ; \
|
|
$(srcdir)/../../move-if-change tmp-model.c $${p}_model.c ; \
|
|
$(srcdir)/../../move-if-change tmp-support.h $${p}_support.h ; \
|
|
$(srcdir)/../../move-if-change tmp-support.c $${p}_support.c ; \
|
|
$(srcdir)/../../move-if-change tmp-engine.h $${p}_engine.h ; \
|
|
$(srcdir)/../../move-if-change tmp-engine.c $${p}_engine.c ; \
|
|
done
|
|
touch tmp-m32-hack
|
|
tmp-m16-hack: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
|
|
for t in m16vr4111:vr4100 m16vr4121:vr4121 ; \
|
|
do \
|
|
p=`echo $${t} | sed -e 's/:.*//'` ; \
|
|
m=`echo $${t} | sed -e 's/.*://'` ; \
|
|
../igen/igen \
|
|
$(IGEN_TRACE) \
|
|
-I $(srcdir) \
|
|
-Werror \
|
|
-Wnodiscard \
|
|
-N 0 \
|
|
-M $${m},mips16 -F 16 \
|
|
-G gen-direct-access \
|
|
-G gen-zero-r0 \
|
|
-B 16 \
|
|
-H 15 \
|
|
-i $(IGEN_INSN) \
|
|
-o $(M16_DC) \
|
|
-P $${p}_ \
|
|
-x \
|
|
-n $${p}_icache.h -hc tmp-icache.h \
|
|
-n $${p}_icache.c -c tmp-icache.c \
|
|
-n $${p}_semantics.h -hs tmp-semantics.h \
|
|
-n $${p}_semantics.c -s tmp-semantics.c \
|
|
-n $${p}_idecode.h -hd tmp-idecode.h \
|
|
-n $${p}_idecode.c -d tmp-idecode.c \
|
|
-n $${p}_model.h -hm tmp-model.h \
|
|
-n $${p}_model.c -m tmp-model.c \
|
|
-n $${p}_support.h -hf tmp-support.h \
|
|
-n $${p}_support.c -f tmp-support.c \
|
|
-n $${p}_engine.h -he tmp-engine.h \
|
|
; \
|
|
$(srcdir)/../../move-if-change tmp-icache.h $${p}_icache.h ; \
|
|
$(srcdir)/../../move-if-change tmp-icache.c $${p}_icache.c ; \
|
|
$(srcdir)/../../move-if-change tmp-idecode.h $${p}_idecode.h ; \
|
|
$(srcdir)/../../move-if-change tmp-idecode.c $${p}_idecode.c ; \
|
|
$(srcdir)/../../move-if-change tmp-semantics.h $${p}_semantics.h ; \
|
|
$(srcdir)/../../move-if-change tmp-semantics.c $${p}_semantics.c ; \
|
|
$(srcdir)/../../move-if-change tmp-model.h $${p}_model.h ; \
|
|
$(srcdir)/../../move-if-change tmp-model.c $${p}_model.c ; \
|
|
$(srcdir)/../../move-if-change tmp-support.h $${p}_support.h ; \
|
|
$(srcdir)/../../move-if-change tmp-support.c $${p}_support.c ; \
|
|
$(srcdir)/../../move-if-change tmp-engine.h $${p}_engine.h ; \
|
|
done
|
|
touch tmp-m16-hack
|
|
tmp-itable-hack: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
|
|
../igen/igen \
|
|
$(IGEN_TRACE) \
|
|
-I $(srcdir) \
|
|
-Werror \
|
|
-Wnodiscard \
|
|
-Wnowidth \
|
|
-N 0 \
|
|
-F 32,64,f -M vr4100,vr4320,mipsIV,vr4121 -F 16 -M mips16 \
|
|
-G gen-direct-access \
|
|
-G gen-zero-r0 \
|
|
-i $(IGEN_INSN) \
|
|
-n itable.h -ht tmp-itable.h \
|
|
-n itable.c -t tmp-itable.c \
|
|
#
|
|
$(srcdir)/../../move-if-change tmp-itable.h itable.h
|
|
$(srcdir)/../../move-if-change tmp-itable.c itable.c
|
|
touch tmp-itable-hack
|
|
tmp-run-hack: $(srcdir)/m16run.c
|
|
for m in vr4111 vr4121 ; \
|
|
do \
|
|
sed < $(srcdir)/m16run.c > tmp-run \
|
|
-e "s/^sim_/m16$${m}_/" \
|
|
-e "s/m16_/m16$${m}_/" \
|
|
-e "s/m32_/m32$${m}_/" ; \
|
|
$(srcdir)/../../move-if-change tmp-run m16$${m}_run.c ; \
|
|
done
|
|
touch tmp-run-hack
|
|
|
|
# end-sanitize-vr4xxx
|