7d5e4556a3
2008-01-12 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * gas/i386/i386.s: Add tests for fnstsw and fstsw. * gas/i386/inval.s: Likewise. * gas/i386/x86_64.s: Likewise. * gas/i386/intel.s: Use word instead of dword on ss. * gas/i386/x86-64-inval.s: Add tests for fnstsw, fstsw, in and out. * gas/i386/prefix.s: Remove invalid fstsw. * gas/i386/inval.l: Updated. * gas/i386/intelbad.l: Likewise. * gas/i386/i386.d: Likewise. * gas/i386/x86_64.d: Likewise. * gas/i386/x86-64-inval.l: Likewise. * gas/i386/prefix.d: Updated. gas/ 2008-01-12 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * config/tc-i386.c (_i386_insn): Update comment. (operand_type_match): Also clear unspecified. (operand_type_register_match): Likewise. (parse_operands): Initialize unspecified. (i386_intel_operand): Likewise. (match_template): Check memory and accumulator operand size. (i386_att_operand): Clear unspecified on register operand. (intel_e11): Likewise. (intel_e09): Set operand size and clean unspecified for "XXX PTR". opcodes/ 2008-01-12 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * i386-gen.c (operand_type_init): Add Dword to OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64. (opcode_modifiers): Remove CheckSize, Byte, Word, Dword, Qword and Xmmword. (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte, Xmmword, Unspecified and Anysize. (set_bitfield): Make Mmword an alias of Qword. Make Oword an alias of Xmmword. * i386-opc.h (CheckSize): Removed. (Byte): Updated. (Word): Likewise. (Dword): Likewise. (Qword): Likewise. (Xmmword): Likewise. (FWait): Updated. (OTMax): Likewise. (i386_opcode_modifier): Remove checksize, byte, word, dword, qword and xmmword. (Fword): New. (TBYTE): Likewise. (Unspecified): Likewise. (Anysize): Likewise. (i386_operand_type): Add byte, word, dword, fword, qword, tbyte xmmword, unspecified and anysize. * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword, Tbyte, Xmmword, Unspecified and Anysize. * i386-reg.tbl: Add size for accumulator. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
206 lines
5.1 KiB
Text
206 lines
5.1 KiB
Text
// i386 register table.
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// Copyright 2007
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// Free Software Foundation, Inc.
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//
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// This file is part of the GNU opcodes library.
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//
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// This library is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 3, or (at your option)
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// any later version.
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//
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// It is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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// License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with GAS; see the file COPYING. If not, write to the Free
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// Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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// 02110-1301, USA.
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// Make %st first as we test for it.
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st, FloatReg|FloatAcc, 0, 0
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// 8 bit regs
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al, Reg8|Acc|Byte, 0, 0
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cl, Reg8|ShiftCount, 0, 1
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dl, Reg8, 0, 2
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bl, Reg8, 0, 3
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ah, Reg8, 0, 4
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ch, Reg8, 0, 5
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dh, Reg8, 0, 6
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bh, Reg8, 0, 7
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axl, Reg8|Acc|Byte, RegRex64, 0
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cxl, Reg8, RegRex64, 1
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dxl, Reg8, RegRex64, 2
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bxl, Reg8, RegRex64, 3
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spl, Reg8, RegRex64, 4
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bpl, Reg8, RegRex64, 5
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sil, Reg8, RegRex64, 6
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dil, Reg8, RegRex64, 7
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r8b, Reg8, RegRex|RegRex64, 0
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r9b, Reg8, RegRex|RegRex64, 1
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r10b, Reg8, RegRex|RegRex64, 2
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r11b, Reg8, RegRex|RegRex64, 3
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r12b, Reg8, RegRex|RegRex64, 4
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r13b, Reg8, RegRex|RegRex64, 5
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r14b, Reg8, RegRex|RegRex64, 6
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r15b, Reg8, RegRex|RegRex64, 7
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// 16 bit regs
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ax, Reg16|Acc|Word, 0, 0
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cx, Reg16, 0, 1
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dx, Reg16|InOutPortReg, 0, 2
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bx, Reg16|BaseIndex, 0, 3
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sp, Reg16, 0, 4
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bp, Reg16|BaseIndex, 0, 5
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si, Reg16|BaseIndex, 0, 6
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di, Reg16|BaseIndex, 0, 7
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r8w, Reg16, RegRex, 0
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r9w, Reg16, RegRex, 1
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r10w, Reg16, RegRex, 2
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r11w, Reg16, RegRex, 3
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r12w, Reg16, RegRex, 4
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r13w, Reg16, RegRex, 5
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r14w, Reg16, RegRex, 6
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r15w, Reg16, RegRex, 7
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// 32 bit regs
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eax, Reg32|BaseIndex|Acc|Dword, 0, 0
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ecx, Reg32|BaseIndex, 0, 1
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edx, Reg32|BaseIndex, 0, 2
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ebx, Reg32|BaseIndex, 0, 3
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esp, Reg32, 0, 4
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ebp, Reg32|BaseIndex, 0, 5
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esi, Reg32|BaseIndex, 0, 6
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edi, Reg32|BaseIndex, 0, 7
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r8d, Reg32|BaseIndex, RegRex, 0
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r9d, Reg32|BaseIndex, RegRex, 1
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r10d, Reg32|BaseIndex, RegRex, 2
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r11d, Reg32|BaseIndex, RegRex, 3
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r12d, Reg32|BaseIndex, RegRex, 4
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r13d, Reg32|BaseIndex, RegRex, 5
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r14d, Reg32|BaseIndex, RegRex, 6
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r15d, Reg32|BaseIndex, RegRex, 7
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rax, Reg64|BaseIndex|Acc|Qword, 0, 0
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rcx, Reg64|BaseIndex, 0, 1
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rdx, Reg64|BaseIndex, 0, 2
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rbx, Reg64|BaseIndex, 0, 3
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rsp, Reg64, 0, 4
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rbp, Reg64|BaseIndex, 0, 5
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rsi, Reg64|BaseIndex, 0, 6
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rdi, Reg64|BaseIndex, 0, 7
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r8, Reg64|BaseIndex, RegRex, 0
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r9, Reg64|BaseIndex, RegRex, 1
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r10, Reg64|BaseIndex, RegRex, 2
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r11, Reg64|BaseIndex, RegRex, 3
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r12, Reg64|BaseIndex, RegRex, 4
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r13, Reg64|BaseIndex, RegRex, 5
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r14, Reg64|BaseIndex, RegRex, 6
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r15, Reg64|BaseIndex, RegRex, 7
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// Segment registers.
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es, SReg2, 0, 0
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cs, SReg2, 0, 1
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ss, SReg2, 0, 2
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ds, SReg2, 0, 3
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fs, SReg3, 0, 4
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gs, SReg3, 0, 5
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// Control registers.
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cr0, Control, 0, 0
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cr1, Control, 0, 1
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cr2, Control, 0, 2
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cr3, Control, 0, 3
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cr4, Control, 0, 4
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cr5, Control, 0, 5
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cr6, Control, 0, 6
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cr7, Control, 0, 7
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cr8, Control, RegRex, 0
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cr9, Control, RegRex, 1
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cr10, Control, RegRex, 2
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cr11, Control, RegRex, 3
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cr12, Control, RegRex, 4
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cr13, Control, RegRex, 5
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cr14, Control, RegRex, 6
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cr15, Control, RegRex, 7
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// Debug registers.
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db0, Debug, 0, 0
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db1, Debug, 0, 1
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db2, Debug, 0, 2
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db3, Debug, 0, 3
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db4, Debug, 0, 4
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db5, Debug, 0, 5
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db6, Debug, 0, 6
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db7, Debug, 0, 7
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db8, Debug, RegRex, 0
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db9, Debug, RegRex, 1
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db10, Debug, RegRex, 2
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db11, Debug, RegRex, 3
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db12, Debug, RegRex, 4
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db13, Debug, RegRex, 5
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db14, Debug, RegRex, 6
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db15, Debug, RegRex, 7
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dr0, Debug, 0, 0
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dr1, Debug, 0, 1
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dr2, Debug, 0, 2
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dr3, Debug, 0, 3
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dr4, Debug, 0, 4
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dr5, Debug, 0, 5
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dr6, Debug, 0, 6
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dr7, Debug, 0, 7
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dr8, Debug, RegRex, 0
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dr9, Debug, RegRex, 1
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dr10, Debug, RegRex, 2
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dr11, Debug, RegRex, 3
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dr12, Debug, RegRex, 4
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dr13, Debug, RegRex, 5
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dr14, Debug, RegRex, 6
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dr15, Debug, RegRex, 7
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// Test registers.
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tr0, Test, 0, 0
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tr1, Test, 0, 1
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tr2, Test, 0, 2
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tr3, Test, 0, 3
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tr4, Test, 0, 4
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tr5, Test, 0, 5
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tr6, Test, 0, 6
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tr7, Test, 0, 7
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// MMX and simd registers.
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mm0, RegMMX, 0, 0
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mm1, RegMMX, 0, 1
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mm2, RegMMX, 0, 2
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mm3, RegMMX, 0, 3
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mm4, RegMMX, 0, 4
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mm5, RegMMX, 0, 5
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mm6, RegMMX, 0, 6
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mm7, RegMMX, 0, 7
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xmm0, RegXMM, 0, 0
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xmm1, RegXMM, 0, 1
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xmm2, RegXMM, 0, 2
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xmm3, RegXMM, 0, 3
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xmm4, RegXMM, 0, 4
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xmm5, RegXMM, 0, 5
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xmm6, RegXMM, 0, 6
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xmm7, RegXMM, 0, 7
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xmm8, RegXMM, RegRex, 0
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xmm9, RegXMM, RegRex, 1
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xmm10, RegXMM, RegRex, 2
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xmm11, RegXMM, RegRex, 3
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xmm12, RegXMM, RegRex, 4
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xmm13, RegXMM, RegRex, 5
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xmm14, RegXMM, RegRex, 6
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xmm15, RegXMM, RegRex, 7
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// No type will make these registers rejected for all purposes except
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// for addressing. This saves creating one extra type for RIP/EIP.
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rip, BaseIndex, RegRex64, RegRip
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eip, BaseIndex, RegRex64, RegEip
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// No type will make these registers rejected for all purposes except
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// for addressing.
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eiz, BaseIndex, 0, RegEiz
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riz, BaseIndex, 0, RegRiz
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// fp regs.
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st(0), FloatReg|FloatAcc, 0, 0
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st(1), FloatReg, 0, 1
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st(2), FloatReg, 0, 2
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st(3), FloatReg, 0, 3
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st(4), FloatReg, 0, 4
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st(5), FloatReg, 0, 5
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st(6), FloatReg, 0, 6
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st(7), FloatReg, 0, 7
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