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old-cross-binutils/ld/testsuite/ld-x86-64/tlsgdesc.dd
H.J. Lu 5db04b0965 Support AMD64/Intel ISAs in assembler/disassembler 
AMD64 spec and Intel64 spec differ in direct unconditional branches in
64-bit mode.  AMD64 supports direct unconditional branches with 16-bit
offset via the data size prefix, which truncates RIP to 16 bits, while
the data size prefix is ignored by Intel64.

This patch adds -mamd64/-mintel64 option to x86-64 assembler and
-Mamd64/-Mintel64 option to x86-64 disassembler.  The most permissive
ISA, which is AMD64, is the default.

GDB can add an option, similar to

(gdb) help set disassembly-flavor
Set the disassembly flavor.
The valid values are "att" and "intel", and the default value is "att".

to select which ISA to disassemble.

binutils/

	PR binutis/18386
	* doc/binutils.texi: Document -Mamd64 and -Mintel64.

gas/

	PR binutis/18386
	* config/tc-i386.c (OPTION_MAMD64): New.
	(OPTION_MINTEL64): Likewise.
	(md_longopts): Add -mamd64 and -mintel64.
	(md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64.
	(md_show_usage): Add -mamd64 and -mintel64.
	* doc/c-i386.texi: Document -mamd64 and -mintel64.

gas/testsuite/

	PR binutis/18386
	* gas/i386/i386.exp: Run x86-64-branch-2 and x86-64-branch-3.
	* gas/i386/x86-64-branch.d: Also pass -Mintel64 to objdump.
	* gas/i386/ilp32/x86-64-branch.d: Likewise.
	* gas/i386/x86-64-branch-2.d: New file.
	* gas/i386/x86-64-branch-2.s: Likewise.
	* gas/i386/x86-64-branch-3.l: Likewise.
	* gas/i386/x86-64-branch-3.s: Likewise.

ld/testsuite/

	PR binutis/18386
	* ld-x86-64/tlsgdesc.dd: Also pass -Mintel64 to objdump.
	* ld-x86-64/tlspic.dd: Likewise.
	* ld-x86-64/x86-64.exp (x86_64tests): Also pass -Mintel64 to
	objdump for tlspic.dd and tlsgdesc.dd.

opcodes/

	PR binutis/18386
	* i386-dis.c: Add comments for '@'.
	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	(enum x86_64_isa): New.
	(isa64): Likewise.
	(print_i386_disassembler_options): Add amd64 and intel64.
	(print_insn): Handle amd64 and intel64.
	(putop): Handle '@'.
	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	* i386-opc.h (AMD64): New.
	(CpuIntel64): Likewise.
	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
	Mark direct call/jmp without Disp16|Disp32 as Intel64.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2015-05-15 09:48:10 -07:00

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#source: tlsgdesc.s
#as: --64
#ld: -shared -melf_x86_64 --no-ld-generated-unwind-info
#objdump: -drj.text -Mintel64
#target: x86_64-*-*
.*: +file format elf64-x86-64.*
Disassembly of section .text:
0+[0-9a-f]+ <fc1>:
+[0-9a-f]+: 55[ ]+push %rbp
+[0-9a-f]+: 48 89 e5[ ]+mov %rsp,%rbp
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
# IE
+[0-9a-f]+: 64 48 8b 0c 25 00 00[ ]+mov %fs:0x0,%rcx
+[0-9a-f]+: 00 00 *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x150>
# -> R_X86_64_TPOFF64 sG3
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
# IE
+[0-9a-f]+: 64 48 8b 0c 25 00 00[ ]+mov %fs:0x0,%rcx
+[0-9a-f]+: 00 00 *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x170>
# -> R_X86_64_TPOFF64 sG4
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
# GD, gd first
+[0-9a-f]+: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x180>
+[0-9a-f]+: [0-9a-f]{2} *
# -> R_X86_64_DTPMOD64 sG1
+[0-9a-f]+: 66 66 48 e8 ([0-9a-f]{2} ){3}[ ]+data16 data16 rex.W callq [0-9a-f]+ <__tls_get_addr@plt>
+[0-9a-f]+: [0-9a-f]{2} *
# -> R_X86_64_JUMP_SLOT __tls_get_addr
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 48 8d 05 ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x30>
# -> R_X86_64_TLSDESC sG1
+[0-9a-f]+: ff 10[ ]+callq \*\(%rax\)
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
# GD, desc first
+[0-9a-f]+: 48 8d 05 ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x20>
# -> R_X86_64_TLSDESC sG2
+[0-9a-f]+: ff 10[ ]+callq \*\(%rax\)
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x160>
+[0-9a-f]+: [0-9a-f]{2} *
# -> R_X86_64_DTPMOD64 sG2
+[0-9a-f]+: 66 66 48 e8 ([0-9a-f]{2} ){3}[ ]+data16 data16 rex.W callq [0-9a-f]+ <__tls_get_addr@plt>
+[0-9a-f]+: [0-9a-f]{2} *
# -> R_X86_64_JUMP_SLOT __tls_get_addr
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
# GD -> IE, gd first, after IE use
+[0-9a-f]+: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+[0-9a-f]+: 00 00 *
+[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x150>
# -> R_X86_64_TPOFF64 sG3
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x150>
# -> R_X86_64_TPOFF64 sG3
+[0-9a-f]+: 66 90[ ]+xchg %ax,%ax
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
# GD -> IE, desc first, after IE use
+[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x170>
# -> R_X86_64_TPOFF64 sG4
+[0-9a-f]+: 66 90[ ]+xchg %ax,%ax
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+[0-9a-f]+: 00 00 *
+[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x170>
# -> R_X86_64_TPOFF64 sG4
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
# GD -> IE, gd first, before IE use
+[0-9a-f]+: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+[0-9a-f]+: 00 00 *
+[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x158>
# -> R_X86_64_TPOFF64 sG5
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x158>
# -> R_X86_64_TPOFF64 sG5
+[0-9a-f]+: 66 90[ ]+xchg %ax,%ax
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
# GD -> IE, desc first, before IE use
+[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x178>
# -> R_X86_64_TPOFF64 sG6
+[0-9a-f]+: 66 90[ ]+xchg %ax,%ax
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+[0-9a-f]+: 00 00 *
+[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x178>
# -> R_X86_64_TPOFF64 sG6
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
# IE
+[0-9a-f]+: 64 48 8b 0c 25 00 00[ ]+mov %fs:0x0,%rcx
+[0-9a-f]+: 00 00 *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x158>
# -> R_X86_64_TPOFF64 sG5
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
# IE
+[0-9a-f]+: 64 48 8b 0c 25 00 00[ ]+mov %fs:0x0,%rcx
+[0-9a-f]+: 00 00 *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x178>
# -> R_X86_64_TPOFF64 sG6
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: 90[ ]+nop *
+[0-9a-f]+: c9[ ]+leaveq *
+[0-9a-f]+: c3[ ]+retq *
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