a3976a7c56
* sim-main.h (reg64_t): New type. (v850_regs): Add selID_sregs field. (VR, SAT16, SAT32, ABS16, ABS32 ): New macros. * v850-dc: Add fields for v850e3v5 instructions. * v850.igen (cvtf.dl): Use correctly signed local value. (cvtf.dw, cvtf.sw, trncf.dul, trncf.dl, trncf.sul, trncf.sw): Likewise. * interp.c: Fix old style function declarations. * simops.c: Likewise.
768 lines
17 KiB
C
768 lines
17 KiB
C
#ifndef SIM_MAIN_H
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#define SIM_MAIN_H
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/* General config options */
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#define WITH_CORE
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#define WITH_MODULO_MEMORY 1
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#define WITH_WATCHPOINTS 1
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/* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */
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#define WITH_TARGET_WORD_MSB 31
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#include "config.h"
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#include "sim-basics.h"
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#include "sim-signal.h"
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#include "sim-fpu.h"
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typedef address_word sim_cia;
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#include "sim-base.h"
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#include "simops.h"
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#include "bfd.h"
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typedef signed8 int8;
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typedef unsigned8 uint8;
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typedef signed16 int16;
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typedef unsigned16 uint16;
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typedef signed32 int32;
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typedef unsigned32 uint32;
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typedef unsigned32 reg_t;
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typedef unsigned64 reg64_t;
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/* The current state of the processor; registers, memory, etc. */
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typedef struct _v850_regs {
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reg_t regs[32]; /* general-purpose registers */
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reg_t sregs[32]; /* system registers, including psw */
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reg_t pc;
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int dummy_mem; /* where invalid accesses go */
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reg_t mpu0_sregs[28]; /* mpu0 system registers */
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reg_t mpu1_sregs[28]; /* mpu1 system registers */
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reg_t fpu_sregs[28]; /* fpu system registers */
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reg_t selID_sregs[7][32]; /* system registers, selID 1 thru selID 7 */
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reg64_t vregs[32]; /* vector registers. */
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} v850_regs;
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struct _sim_cpu
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{
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/* ... simulator specific members ... */
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v850_regs reg;
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reg_t psw_mask; /* only allow non-reserved bits to be set */
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sim_event *pending_nmi;
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/* ... base type ... */
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sim_cpu_base base;
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};
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#define CIA_GET(CPU) ((CPU)->reg.pc + 0)
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#define CIA_SET(CPU,VAL) ((CPU)->reg.pc = (VAL))
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struct sim_state {
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sim_cpu cpu[MAX_NR_PROCESSORS];
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#if (WITH_SMP)
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#define STATE_CPU(sd,n) (&(sd)->cpu[n])
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#else
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#define STATE_CPU(sd,n) (&(sd)->cpu[0])
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#endif
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#if 0
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SIM_ADDR rom_size;
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SIM_ADDR low_end;
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SIM_ADDR high_start;
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SIM_ADDR high_base;
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void *mem;
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#endif
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sim_state_base base;
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};
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/* For compatibility, until all functions converted to passing
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SIM_DESC as an argument */
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extern SIM_DESC simulator;
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#define V850_ROM_SIZE 0x8000
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#define V850_LOW_END 0x200000
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#define V850_HIGH_START 0xffe000
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/* Because we are still using the old semantic table, provide compat
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macro's that store the instruction where the old simops expects
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it. */
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extern uint32 OP[4];
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#if 0
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OP[0] = inst & 0x1f; /* RRRRR -> reg1 */
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OP[1] = (inst >> 11) & 0x1f; /* rrrrr -> reg2 */
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OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
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OP[3] = inst;
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#endif
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#define SAVE_1 \
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PC = cia; \
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OP[0] = instruction_0 & 0x1f; \
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OP[1] = (instruction_0 >> 11) & 0x1f; \
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OP[2] = 0; \
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OP[3] = instruction_0
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#define COMPAT_1(CALL) \
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SAVE_1; \
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PC += (CALL); \
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nia = PC
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#define SAVE_2 \
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PC = cia; \
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OP[0] = instruction_0 & 0x1f; \
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OP[1] = (instruction_0 >> 11) & 0x1f; \
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OP[2] = instruction_1; \
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OP[3] = (instruction_1 << 16) | instruction_0
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#define COMPAT_2(CALL) \
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SAVE_2; \
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PC += (CALL); \
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nia = PC
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/* new */
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#define GR ((CPU)->reg.regs)
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#define SR ((CPU)->reg.sregs)
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#define VR ((CPU)->reg.vregs)
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#define MPU0_SR ((STATE_CPU (sd, 0))->reg.mpu0_sregs)
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#define MPU1_SR ((STATE_CPU (sd, 0))->reg.mpu1_sregs)
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#define FPU_SR ((STATE_CPU (sd, 0))->reg.fpu_sregs)
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/* old */
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#define State (STATE_CPU (simulator, 0)->reg)
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#define PC (State.pc)
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#define SP_REGNO 3
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#define SP (State.regs[SP_REGNO])
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#define EP (State.regs[30])
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#define EIPC (State.sregs[0])
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#define EIPSW (State.sregs[1])
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#define FEPC (State.sregs[2])
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#define FEPSW (State.sregs[3])
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#define ECR (State.sregs[4])
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#define PSW (State.sregs[5])
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#define PSW_REGNO 5
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#define EIIC (State.sregs[13])
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#define FEIC (State.sregs[14])
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#define DBIC (SR[15])
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#define CTPC (SR[16])
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#define CTPSW (SR[17])
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#define DBPC (State.sregs[18])
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#define DBPSW (State.sregs[19])
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#define CTBP (State.sregs[20])
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#define DIR (SR[21])
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#define EIWR (SR[28])
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#define FEWR (SR[29])
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#define DBWR (SR[30])
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#define BSEL (SR[31])
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#define PSW_US BIT32 (8)
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#define PSW_NP 0x80
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#define PSW_EP 0x40
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#define PSW_ID 0x20
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#define PSW_SAT 0x10
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#define PSW_CY 0x8
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#define PSW_OV 0x4
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#define PSW_S 0x2
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#define PSW_Z 0x1
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#define PSW_NPV (1<<18)
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#define PSW_DMP (1<<17)
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#define PSW_IMP (1<<16)
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#define ECR_EICC 0x0000ffff
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#define ECR_FECC 0xffff0000
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/* FPU */
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#define FPSR (FPU_SR[6])
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#define FPSR_REGNO 6
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#define FPEPC (FPU_SR[7])
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#define FPST (FPU_SR[8])
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#define FPST_REGNO 8
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#define FPCC (FPU_SR[9])
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#define FPCFG (FPU_SR[10])
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#define FPCFG_REGNO 10
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#define FPSR_DEM 0x00200000
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#define FPSR_SEM 0x00100000
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#define FPSR_RM 0x000c0000
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#define FPSR_RN 0x00000000
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#define FPSR_FS 0x00020000
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#define FPSR_PR 0x00010000
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#define FPSR_XC 0x0000fc00
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#define FPSR_XCE 0x00008000
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#define FPSR_XCV 0x00004000
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#define FPSR_XCZ 0x00002000
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#define FPSR_XCO 0x00001000
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#define FPSR_XCU 0x00000800
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#define FPSR_XCI 0x00000400
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#define FPSR_XE 0x000003e0
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#define FPSR_XEV 0x00000200
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#define FPSR_XEZ 0x00000100
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#define FPSR_XEO 0x00000080
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#define FPSR_XEU 0x00000040
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#define FPSR_XEI 0x00000020
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#define FPSR_XP 0x0000001f
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#define FPSR_XPV 0x00000010
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#define FPSR_XPZ 0x00000008
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#define FPSR_XPO 0x00000004
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#define FPSR_XPU 0x00000002
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#define FPSR_XPI 0x00000001
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#define FPST_PR 0x00008000
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#define FPST_XCE 0x00002000
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#define FPST_XCV 0x00001000
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#define FPST_XCZ 0x00000800
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#define FPST_XCO 0x00000400
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#define FPST_XCU 0x00000200
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#define FPST_XCI 0x00000100
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#define FPST_XPV 0x00000010
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#define FPST_XPZ 0x00000008
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#define FPST_XPO 0x00000004
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#define FPST_XPU 0x00000002
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#define FPST_XPI 0x00000001
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#define FPCFG_RM 0x00000180
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#define FPCFG_XEV 0x00000010
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#define FPCFG_XEZ 0x00000008
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#define FPCFG_XEO 0x00000004
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#define FPCFG_XEU 0x00000002
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#define FPCFG_XEI 0x00000001
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#define GET_FPCC()\
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((FPSR >> 24) &0xf)
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#define CLEAR_FPCC(bbb)\
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(FPSR &= ~(1 << (bbb+24)))
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#define SET_FPCC(bbb)\
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(FPSR |= 1 << (bbb+24))
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#define TEST_FPCC(bbb)\
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((FPSR & (1 << (bbb+24))) != 0)
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#define FPSR_GET_ROUND() \
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(((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near \
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: ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up \
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: ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down \
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: sim_fpu_round_zero)
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enum FPU_COMPARE {
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FPU_CMP_F = 0,
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FPU_CMP_UN,
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FPU_CMP_EQ,
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FPU_CMP_UEQ,
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FPU_CMP_OLT,
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FPU_CMP_ULT,
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FPU_CMP_OLE,
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FPU_CMP_ULE,
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FPU_CMP_SF,
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FPU_CMP_NGLE,
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FPU_CMP_SEQ,
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FPU_CMP_NGL,
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FPU_CMP_LT,
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FPU_CMP_NGE,
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FPU_CMP_LE,
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FPU_CMP_NGT
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};
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/* MPU */
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#define MPM (MPU1_SR[0])
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#define MPC (MPU1_SR[1])
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#define MPC_REGNO 1
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#define TID (MPU1_SR[2])
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#define PPA (MPU1_SR[3])
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#define PPM (MPU1_SR[4])
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#define PPC (MPU1_SR[5])
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#define DCC (MPU1_SR[6])
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#define DCV0 (MPU1_SR[7])
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#define DCV1 (MPU1_SR[8])
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#define SPAL (MPU1_SR[10])
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#define SPAU (MPU1_SR[11])
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#define IPA0L (MPU1_SR[12])
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#define IPA0U (MPU1_SR[13])
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#define IPA1L (MPU1_SR[14])
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#define IPA1U (MPU1_SR[15])
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#define IPA2L (MPU1_SR[16])
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#define IPA2U (MPU1_SR[17])
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#define IPA3L (MPU1_SR[18])
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#define IPA3U (MPU1_SR[19])
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#define DPA0L (MPU1_SR[20])
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#define DPA0U (MPU1_SR[21])
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#define DPA1L (MPU1_SR[22])
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#define DPA1U (MPU1_SR[23])
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#define DPA2L (MPU1_SR[24])
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#define DPA2U (MPU1_SR[25])
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#define DPA3L (MPU1_SR[26])
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#define DPA3U (MPU1_SR[27])
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#define PPC_PPE 0x1
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#define SPAL_SPE 0x1
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#define SPAL_SPS 0x10
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#define VIP (MPU0_SR[0])
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#define VMECR (MPU0_SR[4])
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#define VMTID (MPU0_SR[5])
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#define VMADR (MPU0_SR[6])
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#define VPECR (MPU0_SR[8])
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#define VPTID (MPU0_SR[9])
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#define VPADR (MPU0_SR[10])
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#define VDECR (MPU0_SR[12])
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#define VDTID (MPU0_SR[13])
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#define MPM_AUE 0x2
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#define MPM_MPE 0x1
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#define VMECR_VMX 0x2
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#define VMECR_VMR 0x4
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#define VMECR_VMW 0x8
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#define VMECR_VMS 0x10
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#define VMECR_VMRMW 0x20
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#define VMECR_VMMS 0x40
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#define IPA2ADDR(IPA) ((IPA) & 0x1fffff80)
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#define IPA_IPE 0x1
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#define IPA_IPX 0x2
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#define IPA_IPR 0x4
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#define IPE0 (IPA0L & IPA_IPE)
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#define IPE1 (IPA1L & IPA_IPE)
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#define IPE2 (IPA2L & IPA_IPE)
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#define IPE3 (IPA3L & IPA_IPE)
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#define IPX0 (IPA0L & IPA_IPX)
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#define IPX1 (IPA1L & IPA_IPX)
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#define IPX2 (IPA2L & IPA_IPX)
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#define IPX3 (IPA3L & IPA_IPX)
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#define IPR0 (IPA0L & IPA_IPR)
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#define IPR1 (IPA1L & IPA_IPR)
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#define IPR2 (IPA2L & IPA_IPR)
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#define IPR3 (IPA3L & IPA_IPR)
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#define DPA2ADDR(DPA) ((DPA) & 0x1fffff80)
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#define DPA_DPE 0x1
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#define DPA_DPR 0x4
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#define DPA_DPW 0x8
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#define DPE0 (DPA0L & DPA_DPE)
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#define DPE1 (DPA1L & DPA_DPE)
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#define DPE2 (DPA2L & DPA_DPE)
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#define DPE3 (DPA3L & DPA_DPE)
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#define DPR0 (DPA0L & DPA_DPR)
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#define DPR1 (DPA1L & DPA_DPR)
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#define DPR2 (DPA2L & DPA_DPR)
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#define DPR3 (DPA3L & DPA_DPR)
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#define DPW0 (DPA0L & DPA_DPW)
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#define DPW1 (DPA1L & DPA_DPW)
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#define DPW2 (DPA2L & DPA_DPW)
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#define DPW3 (DPA3L & DPA_DPW)
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#define DCC_DCE0 0x1
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#define DCC_DCE1 0x10000
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#define PPA2ADDR(PPA) ((PPA) & 0x1fffff80)
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#define PPC_PPC 0xfffffffe
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#define PPC_PPE 0x1
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#define PPC_PPM 0x0000fff8
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#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
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/* sign-extend a 4-bit number */
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#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
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/* sign-extend a 5-bit number */
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#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
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/* sign-extend a 9-bit number */
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#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
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/* sign-extend a 22-bit number */
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#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
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/* sign extend a 40 bit number */
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#define SEXT40(x) ((((x) & UNSIGNED64 (0xffffffffff)) \
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^ (~UNSIGNED64 (0x7fffffffff))) \
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+ UNSIGNED64 (0x8000000000))
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/* sign extend a 44 bit number */
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#define SEXT44(x) ((((x) & UNSIGNED64 (0xfffffffffff)) \
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^ (~ UNSIGNED64 (0x7ffffffffff))) \
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+ UNSIGNED64 (0x80000000000))
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/* sign extend a 60 bit number */
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#define SEXT60(x) ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
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^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
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+ UNSIGNED64 (0x800000000000000))
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/* No sign extension */
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#define NOP(x) (x)
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#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
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#define RLW(x) load_mem (x, 4)
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/* Function declarations. */
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#define IMEM16(EA) \
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sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
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#define IMEM16_IMMED(EA,N) \
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sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
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PC, exec_map, (EA) + (N) * 2)
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#define load_mem(ADDR,LEN) \
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sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
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PC, read_map, (ADDR))
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#define store_mem(ADDR,LEN,DATA) \
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sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
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PC, write_map, (ADDR), (DATA))
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/* compare cccc field against PSW */
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int condition_met (unsigned code);
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/* Debug/tracing calls */
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enum op_types
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{
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OP_UNKNOWN,
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OP_NONE,
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OP_TRAP,
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OP_REG,
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OP_REG_REG,
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OP_REG_REG_CMP,
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OP_REG_REG_MOVE,
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OP_IMM_REG,
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OP_IMM_REG_CMP,
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OP_IMM_REG_MOVE,
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OP_COND_BR,
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OP_LOAD16,
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OP_STORE16,
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OP_LOAD32,
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OP_STORE32,
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OP_JUMP,
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OP_IMM_REG_REG,
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OP_UIMM_REG_REG,
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OP_IMM16_REG_REG,
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OP_UIMM16_REG_REG,
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OP_BIT,
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OP_EX1,
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OP_EX2,
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OP_LDSR,
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OP_STSR,
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OP_BIT_CHANGE,
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OP_REG_REG_REG,
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OP_REG_REG3,
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OP_IMM_REG_REG_REG,
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OP_PUSHPOP1,
|
|
OP_PUSHPOP2,
|
|
OP_PUSHPOP3,
|
|
};
|
|
|
|
#ifdef DEBUG
|
|
void trace_input (char *name, enum op_types type, int size);
|
|
void trace_output (enum op_types result);
|
|
void trace_result (int has_result, unsigned32 result);
|
|
|
|
extern int trace_num_values;
|
|
extern unsigned32 trace_values[];
|
|
extern unsigned32 trace_pc;
|
|
extern const char *trace_name;
|
|
extern int trace_module;
|
|
|
|
#define TRACE_BRANCH0() \
|
|
do { \
|
|
if (TRACE_BRANCH_P (CPU)) { \
|
|
trace_module = TRACE_BRANCH_IDX; \
|
|
trace_pc = cia; \
|
|
trace_name = itable[MY_INDEX].name; \
|
|
trace_num_values = 0; \
|
|
trace_result (1, (nia)); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define TRACE_BRANCH1(IN1) \
|
|
do { \
|
|
if (TRACE_BRANCH_P (CPU)) { \
|
|
trace_module = TRACE_BRANCH_IDX; \
|
|
trace_pc = cia; \
|
|
trace_name = itable[MY_INDEX].name; \
|
|
trace_values[0] = (IN1); \
|
|
trace_num_values = 1; \
|
|
trace_result (1, (nia)); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define TRACE_BRANCH2(IN1, IN2) \
|
|
do { \
|
|
if (TRACE_BRANCH_P (CPU)) { \
|
|
trace_module = TRACE_BRANCH_IDX; \
|
|
trace_pc = cia; \
|
|
trace_name = itable[MY_INDEX].name; \
|
|
trace_values[0] = (IN1); \
|
|
trace_values[1] = (IN2); \
|
|
trace_num_values = 2; \
|
|
trace_result (1, (nia)); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define TRACE_BRANCH3(IN1, IN2, IN3) \
|
|
do { \
|
|
if (TRACE_BRANCH_P (CPU)) { \
|
|
trace_module = TRACE_BRANCH_IDX; \
|
|
trace_pc = cia; \
|
|
trace_name = itable[MY_INDEX].name; \
|
|
trace_values[0] = (IN1); \
|
|
trace_values[1] = (IN2); \
|
|
trace_values[2] = (IN3); \
|
|
trace_num_values = 3; \
|
|
trace_result (1, (nia)); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define TRACE_LD(ADDR,RESULT) \
|
|
do { \
|
|
if (TRACE_MEMORY_P (CPU)) { \
|
|
trace_module = TRACE_MEMORY_IDX; \
|
|
trace_pc = cia; \
|
|
trace_name = itable[MY_INDEX].name; \
|
|
trace_values[0] = (ADDR); \
|
|
trace_num_values = 1; \
|
|
trace_result (1, (RESULT)); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define TRACE_LD_NAME(NAME, ADDR,RESULT) \
|
|
do { \
|
|
if (TRACE_MEMORY_P (CPU)) { \
|
|
trace_module = TRACE_MEMORY_IDX; \
|
|
trace_pc = cia; \
|
|
trace_name = (NAME); \
|
|
trace_values[0] = (ADDR); \
|
|
trace_num_values = 1; \
|
|
trace_result (1, (RESULT)); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define TRACE_ST(ADDR,RESULT) \
|
|
do { \
|
|
if (TRACE_MEMORY_P (CPU)) { \
|
|
trace_module = TRACE_MEMORY_IDX; \
|
|
trace_pc = cia; \
|
|
trace_name = itable[MY_INDEX].name; \
|
|
trace_values[0] = (ADDR); \
|
|
trace_num_values = 1; \
|
|
trace_result (1, (RESULT)); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define TRACE_FP_INPUT_FPU1(V0) \
|
|
do { \
|
|
if (TRACE_FPU_P (CPU)) \
|
|
{ \
|
|
unsigned64 f0; \
|
|
sim_fpu_to64 (&f0, (V0)); \
|
|
trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define TRACE_FP_INPUT_FPU2(V0, V1) \
|
|
do { \
|
|
if (TRACE_FPU_P (CPU)) \
|
|
{ \
|
|
unsigned64 f0, f1; \
|
|
sim_fpu_to64 (&f0, (V0)); \
|
|
sim_fpu_to64 (&f1, (V1)); \
|
|
trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
|
|
do { \
|
|
if (TRACE_FPU_P (CPU)) \
|
|
{ \
|
|
unsigned64 f0, f1, f2; \
|
|
sim_fpu_to64 (&f0, (V0)); \
|
|
sim_fpu_to64 (&f1, (V1)); \
|
|
sim_fpu_to64 (&f2, (V2)); \
|
|
trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
|
|
do { \
|
|
if (TRACE_FPU_P (CPU)) \
|
|
{ \
|
|
int d0 = (V0); \
|
|
unsigned64 f1, f2; \
|
|
TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
|
|
TRACE_IDX (data) = TRACE_FPU_IDX; \
|
|
sim_fpu_to64 (&f1, (V1)); \
|
|
sim_fpu_to64 (&f2, (V2)); \
|
|
save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
|
|
save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
|
|
save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define TRACE_FP_INPUT_WORD2(V0, V1) \
|
|
do { \
|
|
if (TRACE_FPU_P (CPU)) \
|
|
trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
|
|
} while (0)
|
|
|
|
#define TRACE_FP_RESULT_FPU1(R0) \
|
|
do { \
|
|
if (TRACE_FPU_P (CPU)) \
|
|
{ \
|
|
unsigned64 f0; \
|
|
sim_fpu_to64 (&f0, (R0)); \
|
|
trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)
|
|
|
|
#define TRACE_FP_RESULT_WORD2(R0, R1) \
|
|
do { \
|
|
if (TRACE_FPU_P (CPU)) \
|
|
trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
|
|
} while (0)
|
|
|
|
#else
|
|
#define trace_input(NAME, IN1, IN2)
|
|
#define trace_output(RESULT)
|
|
#define trace_result(HAS_RESULT, RESULT)
|
|
|
|
#define TRACE_ALU_INPUT0()
|
|
#define TRACE_ALU_INPUT1(IN0)
|
|
#define TRACE_ALU_INPUT2(IN0, IN1)
|
|
#define TRACE_ALU_INPUT2(IN0, IN1)
|
|
#define TRACE_ALU_INPUT2(IN0, IN1 INS2)
|
|
#define TRACE_ALU_RESULT(RESULT)
|
|
|
|
#define TRACE_BRANCH0()
|
|
#define TRACE_BRANCH1(IN1)
|
|
#define TRACE_BRANCH2(IN1, IN2)
|
|
#define TRACE_BRANCH2(IN1, IN2, IN3)
|
|
|
|
#define TRACE_LD(ADDR,RESULT)
|
|
#define TRACE_ST(ADDR,RESULT)
|
|
|
|
#endif
|
|
|
|
#define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
|
|
#define GPR_CLEAR(N) (State.regs[(N)] = 0)
|
|
|
|
extern void divun ( unsigned int N,
|
|
unsigned long int als,
|
|
unsigned long int sfi,
|
|
unsigned32 /*unsigned long int*/ * quotient_ptr,
|
|
unsigned32 /*unsigned long int*/ * remainder_ptr,
|
|
int *overflow_ptr
|
|
);
|
|
extern void divn ( unsigned int N,
|
|
unsigned long int als,
|
|
unsigned long int sfi,
|
|
signed32 /*signed long int*/ * quotient_ptr,
|
|
signed32 /*signed long int*/ * remainder_ptr,
|
|
int *overflow_ptr
|
|
);
|
|
extern int type1_regs[];
|
|
extern int type2_regs[];
|
|
extern int type3_regs[];
|
|
|
|
#define SESR_OV (1 << 0)
|
|
#define SESR_SOV (1 << 1)
|
|
|
|
#define SESR (State.sregs[12])
|
|
|
|
#define ROUND_Q62_Q31(X) ((((X) + (1 << 30)) >> 31) & 0xffffffff)
|
|
#define ROUND_Q62_Q15(X) ((((X) + (1 << 30)) >> 47) & 0xffff)
|
|
#define ROUND_Q31_Q15(X) ((((X) + (1 << 15)) >> 15) & 0xffff)
|
|
#define ROUND_Q30_Q15(X) ((((X) + (1 << 14)) >> 15) & 0xffff)
|
|
|
|
#define SAT16(X) \
|
|
do \
|
|
{ \
|
|
signed64 z = (X); \
|
|
if (z > 0x7fff) \
|
|
{ \
|
|
SESR |= SESR_OV | SESR_SOV; \
|
|
z = 0x7fff; \
|
|
} \
|
|
else if (z < -0x8000) \
|
|
{ \
|
|
SESR |= SESR_OV | SESR_SOV; \
|
|
z = - 0x8000; \
|
|
} \
|
|
(X) = z; \
|
|
} \
|
|
while (0)
|
|
|
|
#define SAT32(X) \
|
|
do \
|
|
{ \
|
|
signed64 z = (X); \
|
|
if (z > 0x7fffffff) \
|
|
{ \
|
|
SESR |= SESR_OV | SESR_SOV; \
|
|
z = 0x7fffffff; \
|
|
} \
|
|
else if (z < -0x80000000) \
|
|
{ \
|
|
SESR |= SESR_OV | SESR_SOV; \
|
|
z = - 0x80000000; \
|
|
} \
|
|
(X) = z; \
|
|
} \
|
|
while (0)
|
|
|
|
#define ABS16(X) \
|
|
do \
|
|
{ \
|
|
signed64 z = (X) & 0xffff; \
|
|
if (z == 0x8000) \
|
|
{ \
|
|
SESR |= SESR_OV | SESR_SOV; \
|
|
z = 0x7fff; \
|
|
} \
|
|
else if (z & 0x8000) \
|
|
{ \
|
|
z = (- z) & 0xffff; \
|
|
} \
|
|
(X) = z; \
|
|
} \
|
|
while (0)
|
|
|
|
#define ABS32(X) \
|
|
do \
|
|
{ \
|
|
signed64 z = (X) & 0xffffffff; \
|
|
if (z == 0x80000000) \
|
|
{ \
|
|
SESR |= SESR_OV | SESR_SOV; \
|
|
z = 0x7fffffff; \
|
|
} \
|
|
else if (z & 0x80000000) \
|
|
{ \
|
|
z = (- z) & 0xffffffff; \
|
|
} \
|
|
(X) = z; \
|
|
} \
|
|
while (0)
|
|
|
|
#endif
|