old-cross-binutils/gdb/regformats/s390x-tevx-linux64.dat
Andreas Arnez 446899e472 S390: Add target descriptions for vector register sets
The IBM z13 has new vector registers v0-v31 which are presented by the
Linux kernel as two additional register sets.  This patch adds XML
descriptions and the respective autogenerated .c and .dat files for
S390 targets with this feature.  Note that supported combinations
include targets with and without a transactional execution facility.

gdb/ChangeLog:

	* features/s390-tevx-linux64.xml: New file.
	* features/s390-vx-linux64.xml: New file.
	* features/s390-vx.xml: New file.
	* features/s390x-tevx-linux64.xml: New file.
	* features/s390x-vx-linux64.xml: New file.
	* features/Makefile (WHICH): Add s390-vx-linux64,
	s390x-vx-linux64, s390-tevx-linux64, and s390x-tevx-linux64.
	(s390-vx-linux64-expedite, s390-tevx-linux64-expedite)
	(s390x-vx-linux64-expedite, s390x-tevx-linux64-expedite): New
	macros.
	* features/s390-tevx-linux64.c: New generated file.
	* features/s390-vx-linux64.c: Likewise.
	* features/s390x-tevx-linux64.c: Likewise.
	* features/s390x-vx-linux64.c: Likewise.
	* regformats/s390-tevx-linux64.dat: Likewise.
	* regformats/s390-vx-linux64.dat: Likewise.
	* regformats/s390x-tevx-linux64.dat: Likewise.
	* regformats/s390x-vx-linux64.dat: Likewise.

gdb/doc/ChangeLog:

	* gdb.texinfo (S/390 and System z Features): Describe new feature
	"org.gnu.gdb.s390.vx".
2015-03-02 10:57:39 +01:00

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# THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi :set ro:
# Generated from: s390x-tevx-linux64.xml
name:s390x_tevx_linux64
xmltarget:s390x-tevx-linux64.xml
expedite:r14,r15,pswa
64:pswm
64:pswa
64:r0
64:r1
64:r2
64:r3
64:r4
64:r5
64:r6
64:r7
64:r8
64:r9
64:r10
64:r11
64:r12
64:r13
64:r14
64:r15
32:acr0
32:acr1
32:acr2
32:acr3
32:acr4
32:acr5
32:acr6
32:acr7
32:acr8
32:acr9
32:acr10
32:acr11
32:acr12
32:acr13
32:acr14
32:acr15
32:fpc
64:f0
64:f1
64:f2
64:f3
64:f4
64:f5
64:f6
64:f7
64:f8
64:f9
64:f10
64:f11
64:f12
64:f13
64:f14
64:f15
64:orig_r2
64:last_break
32:system_call
64:tdb0
64:tac
64:tct
64:atia
64:tr0
64:tr1
64:tr2
64:tr3
64:tr4
64:tr5
64:tr6
64:tr7
64:tr8
64:tr9
64:tr10
64:tr11
64:tr12
64:tr13
64:tr14
64:tr15
64:v0l
64:v1l
64:v2l
64:v3l
64:v4l
64:v5l
64:v6l
64:v7l
64:v8l
64:v9l
64:v10l
64:v11l
64:v12l
64:v13l
64:v14l
64:v15l
128:v16
128:v17
128:v18
128:v19
128:v20
128:v21
128:v22
128:v23
128:v24
128:v25
128:v26
128:v27
128:v28
128:v29
128:v30
128:v31