147 lines
5.4 KiB
Text
147 lines
5.4 KiB
Text
Wed Feb 25 11:01:17 1998 Doug Evans <devans@canuck.cygnus.com>
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* Makefile.in (RUNTEST): Fix path to runtest.
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start-sanitize-sky
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Tue Feb 24 19:47:56 1998 Frank Ch. Eigler <fche@cygnus.com>
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* configure.in (testdir): Added sky subdir for mips64r5900-sky-elf
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target.
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* configure: Regenerate.
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end-sanitize-sky
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Fri Feb 20 11:00:02 1998 Nick Clifton <nickc@cygnus.com>
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* sim/m32r/unlock.cgs: Fixed test.
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* sim/m32r/mvfc.cgs: Fixed test.
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* sim/m32r/remu.cgs: Fixed test.
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* sim/m32r/bnc24.cgs: Test long BNC instruction.
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* sim/m32r/bnc8.cgs: Test short BNC instruction.
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* sim/m32r/ld-plus.cgs: Test LD instruction.
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* sim/m32r/macwhi.cgs: Test MACWHI instruction.
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* sim/m32r/macwlo.cgs: Test MACWLO instruction.
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* sim/m32r/mulwhi.cgs: Test MULWHI instruction.
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* sim/m32r/mulwlo.cgs: Test MULWLO instruction.
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* sim/m32r/mvfachi.cgs: Test MVFACHI instruction.
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* sim/m32r/mvfaclo.cgs: Test MVFACLO instruction.
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* sim/m32r/mvtaclo.cgs: Test MVTACLO instruction.
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* sim/m32r/addv.cgs: Test ADDV instruction.
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* sim/m32r/addv3.cgs: Test ADDV3 instruction.
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* sim/m32r/addx.cgs: Test ADDX instruction.
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* sim/m32r/lock.cgs: Test LOCK instruction.
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* sim/m32r/neg.cgs: Test NEG instruction.
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* sim/m32r/not.cgs: Test NOT instruction.
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* sim/m32r/unlock.cgs: Test UNLOCK instruction.
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start-sanitize-m32rx
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* sim/m32r/mvfachi-a.cgs: Test extended MVFACHI instruction.
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* sim/m32r/mvfaclo-a.cgs: Test extended MVFACLO.cgs instruction.
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* sim/m32r/mvtachi-a.cgs: Test extended MVTACHI instruction.
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* sim/m32r/mvtaclo-a.cgs: Test extended MVTACLO instruction.
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end-sanitize-m32rx
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Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com>
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* sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an
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address into a general register.
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* sim/m32r/or3.cgs: Test OR3 instruction.
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* sim/m32r/rach.cgs: Test RACH instruction.
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* sim/m32r/rem.cgs: Test REM instruction.
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* sim/m32r/sub.cgs: Test SUB instruction.
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* sim/m32r/mv.cgs: Test MV instruction.
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* sim/m32r/mul.cgs: Test MUL instruction.
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* sim/m32r/bl24.cgs: Test long BL instruction.
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* sim/m32r/bl8.cgs: Test short BL instruction.
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* sim/m32r/blez.cgs: Test BLEZ instruction.
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* sim/m32r/bltz.cgs: Test BLTZ instruction.
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* sim/m32r/bne.cgs: Test BNE instruction.
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* sim/m32r/bnez.cgs: Test BNEZ instruction.
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* sim/m32r/bra24.cgs: Test long BRA instruction.
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* sim/m32r/bra8.cgs: Test short BRA instruction.
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* sim/m32r/jl.cgs: Test JL instruction.
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* sim/m32r/or.cgs: Test OR instruction.
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* sim/m32r/jmp.cgs: Test JMP instruction.
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* sim/m32r/and.cgs: Test AND instruction.
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* sim/m32r/and3.cgs: Test AND3 instruction.
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* sim/m32r/beq.cgs: Test BEQ instruction.
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* sim/m32r/beqz.cgs: Test BEQZ instruction.
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* sim/m32r/bgez.cgs: Test BGEZ instruction.
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* sim/m32r/bgtz.cgs: Test BGTZ instruction.
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* sim/m32r/cmp.cgs: Test CMP instruction.
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* sim/m32r/cmpi.cgs: Test CMPI instruction.
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* sim/m32r/cmpu.cgs: Test CMPU instruction.
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* sim/m32r/cmpui.cgs: Test CMPUI instruction.
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* sim/m32r/div.cgs: Test DIV instruction.
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* sim/m32r/divu.cgs: Test DIVU instruction.
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* sim/m32r/cmpeq.cgs: Test CMPEQ instruction.
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* sim/m32r/sll.cgs: Test SLL instruction.
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* sim/m32r/sll3.cgs: Test SLL3 instruction.
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* sim/m32r/slli.cgs: Test SLLI instruction.
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* sim/m32r/sra.cgs: Test SRA instruction.
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* sim/m32r/sra3.cgs: Test SRA3 instruction.
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* sim/m32r/srai.cgs: Test SRAI instruction.
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* sim/m32r/srl.cgs: Test SRL instruction.
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* sim/m32r/srl3.cgs: Test SRL3 instruction.
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* sim/m32r/srli.cgs: Test SRLI instruction.
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* sim/m32r/xor3.cgs: Test XOR3 instruction.
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* sim/m32r/xor.cgs: Test XOR instruction.
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start-sanitize-m342rx
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* sim/m32r/jnc.cgs: Test JNC instruction.
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* sim/m32r/jc.cgs: Test JC instruction.
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* sim/m32r/cmpz.cgs: Test CMPZ instruction.
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* sim/m32r/bcl24.cgs: Test long version of BCL instruction
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* sim/m32r/bcl8.cgs: Test short BCL instruction.
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* sim/m32r/bncl24.cgs: Test long BNCL instruction.
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* sim/m32r/bncl8.cgs: Test short BNCL instruction.
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* sim/m32r/divh.cgs: Test DIVH instruction.
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* sim/m32r/rach-dsi.cgs: Test extended RACH instruction.
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end-sanitize-m342rx
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Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com>
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* config/default.exp: New file.
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* lib/sim-defs.exp: New file.
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* sim/m32r/*: m32r dejagnu simulator testsuite.
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* Makefile.in (build_alias): Define.
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(arch): Define.
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(RUNTEST_FOR_TARGET): Delete.
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(RUNTEST): Fix.
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(SCHEME,SCHEMEFLAGS,CGENDIR,CGENFLAGS): Define.
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(check): Depend on site.exp. Run dejagnu.
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(site.exp): New target.
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(cgen): New target.
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* configure.in: Call AC_CHECK_PROG(SCHEME) if using cgen.
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(arch): Define from target_cpu.
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* configure: Regenerate.
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Wed Sep 17 10:21:26 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* common/bits-gen.c (gen_bit): Pass in the full name of the macro.
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(gen_mask): Ditto.
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* common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT.
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(calc): Add support for 8 bit version of macros.
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(main): Add tests for 8 bit versions of macros.
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(check_sext): Check SEXT of zero clears bits.
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* common/bits-gen.c (main): Generate tests for 8 bit versions of
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macros.
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Thu Sep 11 13:04:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* common/Make-common.in: New file, provide generic rules for
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running checks.
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Mon Sep 1 16:43:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* configure.in (configdirs): Test for the target directory instead
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of matching on a target.
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start-sanitize-r5900
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Tue Jul 15 13:43:20 1997 Andrew Cagney <cagney@sendai.cygnus.com>
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* configure.in (configdirs): Configure mips64vr5900el
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directory.
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* configure: Regenerate.
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end-sanitize-r5900
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