f5cd4d758c
(CGEN_MAIN_SCM): Add rtx-funcs.scm.
(cgen-arch): Pass $(mach) to cgen.sh.
* cgen-engine.h (SEM_BRANCH_FINI): New arg pcvar, all uses updated.
(SEM_BRANCH_INIT_EXTRACT): New macro.
(SEM_BRANCH_INIT): Add taken_p.
(TARGET_SEM_BRANCH_FINI): Provide default definition.
(SEM_BRANCH_FINI): Use it.
(SEM_INSN): Update.
* cgen-run.c (sim_resume): Handle tracing of last insn.
* cgen-scache.h (WITH_SCACHE): Define as 0 if not defined.
* cgen-trace.c (current_abuf): New static global.
(trace_insn_init): Initialize it.
(trace_insn_fini): Use it.
(trace_insn): Set it.
* cgen.sh (arch case): Pass -m ${mach} to cgen.
* genmloop.sh (@cpu@_emit_before): Only define if WITH_SCACHE_PBB.
(@cpu@_emit_after): Ditto.
(simple @cpu@_engine_run_full): New local `pc'. Initialize semantic
labels if WITH_SEM_SWITCH_FULL.
* sim-model.c: Include bfd.h.
(sim_model_init): New function.
(sim_model_install): Record init fn.
* sim-model.h (MACH): New member bfd_name.
* sim-module.c (modules): Initialize model before scache.
132 lines
4.2 KiB
C
132 lines
4.2 KiB
C
/* Architecture, machine, and model support.
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Copyright (C) 1997, 1998 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* Nomenclature:
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architecture = one of sparc, mips, sh, etc.
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in the sparc architecture, mach = one of v6, v7, v8, sparclite, etc.
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in the v8 mach, model = one of supersparc, etc.
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*/
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/* This file is intended to be included by sim-basics.h. */
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#ifndef SIM_MODEL_H
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#define SIM_MODEL_H
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/* Function unit and instruction timing support.
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??? This is obviously insufficiently general.
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It's useful but it needs elaborating upon. */
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typedef struct {
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unsigned char name; /* actually a UNIT_TYPE enum */
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unsigned char issue;
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unsigned char done;
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} UNIT;
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#ifndef MAX_UNITS
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#define MAX_UNITS 1
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#endif
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typedef int (MODEL_FN) (sim_cpu *, void *);
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typedef struct {
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/* This is an integer that identifies this insn.
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How this works is up to the target. */
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int num;
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/* Function to handle insn-specific profiling. */
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MODEL_FN *model_fn;
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/* Array of function units used by this insn. */
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UNIT units[MAX_UNITS];
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} INSN_TIMING;
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/* Struct to describe various implementation properties of a cpu.
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When multiple cpu variants are supported, the sizes of some structs
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can vary. */
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typedef struct {
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/* The size of the SIM_CPU struct. */
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int sim_cpu_size;
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#define IMP_PROPS_SIM_CPU_SIZE(cpu_props) ((cpu_props)->sim_cpu_size)
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/* An SCACHE element can vary in size, depending on the selected cpu.
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This is zero if the SCACHE isn't in use for this variant. */
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int scache_elm_size;
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#define IMP_PROPS_SCACHE_ELM_SIZE(cpu_props) ((cpu_props)->scache_elm_size)
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} MACH_IMP_PROPERTIES;
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/* A machine variant. */
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typedef struct {
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const char *name;
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#define MACH_NAME(m) ((m)->name)
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/* This is the argument to bfd_scan_arch. */
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const char *bfd_name;
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#define MACH_BFD_NAME(m) ((m)->bfd_name)
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int word_bitsize;
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#define MACH_WORD_BITSIZE(m) ((m)->word_bitsize)
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int addr_bitsize;
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#define MACH_ADDR_BITSIZE(m) ((m)->addr_bitsize)
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/* Pointer to null-entry terminated table of models of this mach.
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The default is the first one. */
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const struct model *models;
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#define MACH_MODELS(m) ((m)->models)
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/* Pointer to the implementation properties of this mach. */
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const MACH_IMP_PROPERTIES *imp_props;
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#define MACH_IMP_PROPS(m) ((m)->imp_props)
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/* Called by sim_model_set when the model of a cpu is set. */
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void (* init_cpu) (sim_cpu *);
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#define MACH_INIT_CPU(m) ((m)->init_cpu)
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} MACH;
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/* A model (implementation) of a machine. */
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typedef struct model {
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const char *name;
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#define MODEL_NAME(m) ((m)->name)
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const MACH *mach;
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#define MODEL_MACH(m) ((m)->mach)
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/* An enum that distinguished the model. */
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int num;
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#define MODEL_NUM(m) ((m)->num)
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/* Pointer to timing table for this model. */
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const INSN_TIMING *timing;
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#define MODEL_TIMING(m) ((m)->timing)
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void (* init) (sim_cpu *);
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#define MODEL_INIT(m) ((m)->init)
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} MODEL;
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/* Tables of supported machines. */
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/* ??? In a simulator of multiple architectures, will need multiple copies of
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this. Have an `archs' array that contains a pointer to the machs array
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for each (which in turn has a pointer to the models array for each). */
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extern const MACH *sim_machs[];
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/* Model module handlers. */
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extern MODULE_INSTALL_FN sim_model_install;
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/* Support routines. */
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extern void sim_model_set (SIM_DESC sd, sim_cpu *cpu, const MODEL *model);
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extern const MODEL * sim_model_lookup (const char *name);
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extern const MACH * sim_mach_lookup (const char *name);
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#endif /* SIM_MODEL_H */
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