c2009f4a31
opcode table as something that is "opened/closed".
* cgen-asm.c (all fns): New first arg of opcode table descriptor.
(cgen_asm_init): Delete.
(cgen_set_parse_operand_fn): New function.
* cgen-dis.c (all fns): New first arg of opcode table descriptor.
(cgen_dis_init): Delete.
* cgen-opc.c (all fns): New first arg of opcode table descriptor.
(cgen_current_{opcode_table_mach,endian}): Delete.
* cgen-asm.in (all fns): New first arg of opcode table descriptor.
* cgen-dis.in (all fns): Ditto.
* cgen-opc.in (all fns): Ditto.
* m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate.
* cgen-asm.in (parse_insn_normal): Ignore case in mnemonics.
* cgen-dis.in (print_normal): Split into two.
(print_address): New function.
(extract_insn_normal): Clarify insn_value arg.
(print_int_insn): Renamed from print_insn.
(print_insn): New arg.
(print_insn_@arch@): Open opcode table if not already done so.
Move reading of insn into print_insn.
435 lines
12 KiB
C
435 lines
12 KiB
C
/* Instruction description for m32r.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef M32R_OPC_H
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#define M32R_OPC_H
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#define CGEN_ARCH m32r
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/* Given symbol S, return m32r_cgen_<s>. */
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#define CGEN_SYM(s) CONCAT3 (m32r,_cgen_,s)
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/* Selected cpu families. */
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#define HAVE_CPU_M32R
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/* start-sanitize-m32rx */
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#define HAVE_CPU_M32RX
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/* end-sanitize-m32rx */
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#define CGEN_WORD_BITSIZE 32
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#define CGEN_DEFAULT_INSN_BITSIZE 32
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#define CGEN_BASE_INSN_BITSIZE 32
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#define CGEN_MIN_INSN_BITSIZE 16
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#define CGEN_MAX_INSN_BITSIZE 32
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#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
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#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
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#define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8)
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#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
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#define CGEN_INT_INSN
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/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */
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/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
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e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
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we can't hash on everything up to the space. */
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#define CGEN_MNEMONIC_OPERANDS
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/* Maximum number of operands any insn or macro-insn has. */
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#define CGEN_MAX_INSN_OPERANDS 16
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/* Enums. */
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/* Enum declaration for insn format enums. */
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typedef enum insn_op1 {
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OP1_0, OP1_1, OP1_2, OP1_3
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, OP1_4, OP1_5, OP1_6, OP1_7
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, OP1_8, OP1_9, OP1_10, OP1_11
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, OP1_12, OP1_13, OP1_14, OP1_15
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} INSN_OP1;
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/* Enum declaration for op2 enums. */
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typedef enum insn_op2 {
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OP2_0, OP2_1, OP2_2, OP2_3
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, OP2_4, OP2_5, OP2_6, OP2_7
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, OP2_8, OP2_9, OP2_10, OP2_11
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, OP2_12, OP2_13, OP2_14, OP2_15
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} INSN_OP2;
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/* Enum declaration for general registers. */
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typedef enum h_gr {
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H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0
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, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
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, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
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, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
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, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
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} H_GR;
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/* Enum declaration for control registers. */
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typedef enum h_cr {
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H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3
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, H_CR_BPC = 6, H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2
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, H_CR_CR3 = 3, H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6
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, H_CR_CR7 = 7, H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10
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, H_CR_CR11 = 11, H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14
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, H_CR_CR15 = 15
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} H_CR;
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/* start-sanitize-m32rx */
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/* Enum declaration for accumulators. */
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typedef enum h_accums {
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H_ACCUMS_A0, H_ACCUMS_A1
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} H_ACCUMS;
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/* end-sanitize-m32rx */
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/* Enum declaration for m32r operand types. */
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typedef enum cgen_operand_type {
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M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
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, M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
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, M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
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/* start-sanitize-m32rx */
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, M32R_OPERAND_IMM1
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_OPERAND_ACCD
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_OPERAND_ACCS
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_OPERAND_ACC
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/* end-sanitize-m32rx */
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, M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16
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, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24
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, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
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} CGEN_OPERAND_TYPE;
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/* Non-boolean attributes. */
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/* Enum declaration for machine type selection. */
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typedef enum mach_attr {
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MACH_M32R
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/* start-sanitize-m32rx */
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, MACH_M32RX
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/* end-sanitize-m32rx */
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, MACH_MAX
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} MACH_ATTR;
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/* start-sanitize-m32rx */
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/* Enum declaration for parallel execution pipeline selection. */
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typedef enum pipe_attr {
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PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
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} PIPE_ATTR;
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/* end-sanitize-m32rx */
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/* Number of architecture variants. */
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#define MAX_MACHS ((int) MACH_MAX)
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/* Number of operands types. */
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#define MAX_OPERANDS ((int) M32R_OPERAND_MAX)
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/* Maximum number of operands referenced by any insn. */
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#define MAX_OPERAND_INSTANCES 8
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/* Operand and instruction attribute indices. */
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/* Enum declaration for cgen_operand attrs. */
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typedef enum cgen_operand_attr {
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CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_NEGATIVE
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, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC, CGEN_OPERAND_SIGN_OPT
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, CGEN_OPERAND_UNSIGNED
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} CGEN_OPERAND_ATTR;
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/* Number of non-boolean elements in cgen_operand. */
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#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
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/* Enum declaration for cgen_insn attrs. */
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typedef enum cgen_insn_attr {
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CGEN_INSN_MACH
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/* start-sanitize-m32rx */
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, CGEN_INSN_PIPE
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/* end-sanitize-m32rx */
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, CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_NO_DIS
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, CGEN_INSN_PARALLEL, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_SPECIAL
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, CGEN_INSN_UNCOND_CTI
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} CGEN_INSN_ATTR;
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/* Number of non-boolean elements in cgen_insn. */
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#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)
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/* Enum declaration for m32r instruction types. */
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typedef enum cgen_insn_type {
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M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND
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, M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR
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, M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3
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, M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC24, M32R_INSN_BEQ
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, M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ
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, M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL24
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/* start-sanitize-m32rx */
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, M32R_INSN_BCL8
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_INSN_BCL24
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/* end-sanitize-m32rx */
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, M32R_INSN_BNC8, M32R_INSN_BNC24, M32R_INSN_BNE, M32R_INSN_BRA8
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, M32R_INSN_BRA24
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/* start-sanitize-m32rx */
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, M32R_INSN_BNCL8
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_INSN_BNCL24
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/* end-sanitize-m32rx */
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, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU, M32R_INSN_CMPUI
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/* start-sanitize-m32rx */
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, M32R_INSN_CMPEQ
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_INSN_CMPZ
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/* end-sanitize-m32rx */
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, M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU
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/* start-sanitize-m32rx */
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, M32R_INSN_DIVH
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_INSN_JC
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_INSN_JNC
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/* end-sanitize-m32rx */
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, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD, M32R_INSN_LD_D
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, M32R_INSN_LDB, M32R_INSN_LDB_D, M32R_INSN_LDH, M32R_INSN_LDH_D
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, M32R_INSN_LDUB, M32R_INSN_LDUB_D, M32R_INSN_LDUH, M32R_INSN_LDUH_D
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, M32R_INSN_LD_PLUS, M32R_INSN_LD24, M32R_INSN_LDI8, M32R_INSN_LDI16
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, M32R_INSN_LOCK, M32R_INSN_MACHI
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/* start-sanitize-m32rx */
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, M32R_INSN_MACHI_A
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/* end-sanitize-m32rx */
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, M32R_INSN_MACLO
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/* start-sanitize-m32rx */
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, M32R_INSN_MACLO_A
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/* end-sanitize-m32rx */
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, M32R_INSN_MACWHI
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/* start-sanitize-m32rx */
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, M32R_INSN_MACWHI_A
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/* end-sanitize-m32rx */
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, M32R_INSN_MACWLO
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/* start-sanitize-m32rx */
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, M32R_INSN_MACWLO_A
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/* end-sanitize-m32rx */
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, M32R_INSN_MUL, M32R_INSN_MULHI
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/* start-sanitize-m32rx */
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, M32R_INSN_MULHI_A
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/* end-sanitize-m32rx */
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, M32R_INSN_MULLO
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/* start-sanitize-m32rx */
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, M32R_INSN_MULLO_A
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/* end-sanitize-m32rx */
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, M32R_INSN_MULWHI
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/* start-sanitize-m32rx */
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, M32R_INSN_MULWHI_A
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/* end-sanitize-m32rx */
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, M32R_INSN_MULWLO
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/* start-sanitize-m32rx */
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, M32R_INSN_MULWLO_A
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/* end-sanitize-m32rx */
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, M32R_INSN_MV, M32R_INSN_MVFACHI
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/* start-sanitize-m32rx */
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, M32R_INSN_MVFACHI_A
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/* end-sanitize-m32rx */
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, M32R_INSN_MVFACLO
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/* start-sanitize-m32rx */
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, M32R_INSN_MVFACLO_A
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/* end-sanitize-m32rx */
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, M32R_INSN_MVFACMI
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/* start-sanitize-m32rx */
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, M32R_INSN_MVFACMI_A
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/* end-sanitize-m32rx */
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, M32R_INSN_MVFC, M32R_INSN_MVTACHI
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/* start-sanitize-m32rx */
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, M32R_INSN_MVTACHI_A
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/* end-sanitize-m32rx */
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, M32R_INSN_MVTACLO
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/* start-sanitize-m32rx */
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, M32R_INSN_MVTACLO_A
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/* end-sanitize-m32rx */
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, M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT
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, M32R_INSN_RAC
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/* start-sanitize-m32rx */
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, M32R_INSN_RAC_DSI
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/* end-sanitize-m32rx */
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, M32R_INSN_RACH
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/* start-sanitize-m32rx */
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, M32R_INSN_RACH_DSI
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/* end-sanitize-m32rx */
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, M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3
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, M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI
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, M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST
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, M32R_INSN_ST_D, M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH
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, M32R_INSN_STH_D, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS, M32R_INSN_SUB
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, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP, M32R_INSN_UNLOCK
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/* start-sanitize-m32rx */
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, M32R_INSN_SATB
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_INSN_SATH
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_INSN_SAT
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_INSN_PCMPBZ
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_INSN_SADD
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_INSN_MACWU1
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_INSN_MSBLO
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_INSN_MULWU1
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_INSN_MACLH1
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_INSN_SC
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_INSN_SNC
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/* end-sanitize-m32rx */
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, M32R_INSN_MAX
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} CGEN_INSN_TYPE;
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/* Index of `illegal' insn place holder. */
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#define CGEN_INSN_ILLEGAL M32R_INSN_ILLEGAL
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/* Total number of insns in table. */
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#define MAX_INSNS ((int) M32R_INSN_MAX)
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/* cgen.h uses things we just defined. */
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#include "opcode/cgen.h"
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/* This struct records data prior to insertion or after extraction. */
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struct cgen_fields
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{
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long f_nil;
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long f_op1;
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long f_op2;
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long f_cond;
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long f_r1;
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long f_r2;
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long f_simm8;
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long f_simm16;
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long f_shift_op2;
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long f_uimm4;
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long f_uimm5;
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long f_uimm16;
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long f_uimm24;
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long f_hi16;
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long f_disp8;
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long f_disp16;
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long f_disp24;
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/* start-sanitize-m32rx */
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long f_op23;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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long f_op3;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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long f_acc;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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long f_accs;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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long f_accd;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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long f_bits67;
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/* end-sanitize-m32rx */
|
|
/* start-sanitize-m32rx */
|
|
long f_bit14;
|
|
/* end-sanitize-m32rx */
|
|
/* start-sanitize-m32rx */
|
|
long f_imm1;
|
|
/* end-sanitize-m32rx */
|
|
int length;
|
|
};
|
|
|
|
/* Attributes. */
|
|
extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
|
|
extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
|
|
|
|
/* Enum declaration for m32r hardware types. */
|
|
typedef enum hw_type {
|
|
HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
|
|
, HW_H_ADDR, HW_H_IADDR, HW_H_HI16, HW_H_SLO16
|
|
, HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM
|
|
/* start-sanitize-m32rx */
|
|
, HW_H_ACCUMS
|
|
/* end-sanitize-m32rx */
|
|
, HW_H_COND, HW_H_SM, HW_H_BSM, HW_H_IE
|
|
, HW_H_BIE, HW_H_BCOND, HW_H_BPC, HW_H_LOCK
|
|
, HW_MAX
|
|
} HW_TYPE;
|
|
|
|
#define MAX_HW ((int) HW_MAX)
|
|
|
|
/* Hardware decls. */
|
|
|
|
extern CGEN_KEYWORD m32r_cgen_opval_h_gr;
|
|
extern CGEN_KEYWORD m32r_cgen_opval_h_cr;
|
|
/* start-sanitize-m32rx */
|
|
extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
|
|
/* end-sanitize-m32rx */
|
|
|
|
#define CGEN_INIT_PARSE(od) \
|
|
{\
|
|
}
|
|
#define CGEN_INIT_INSERT(od) \
|
|
{\
|
|
}
|
|
#define CGEN_INIT_EXTRACT(od) \
|
|
{\
|
|
}
|
|
#define CGEN_INIT_PRINT(od) \
|
|
{\
|
|
}
|
|
|
|
/* -- opc.h */
|
|
|
|
#undef CGEN_DIS_HASH_SIZE
|
|
#define CGEN_DIS_HASH_SIZE 256
|
|
#undef CGEN_DIS_HASH
|
|
#define X(b) (((unsigned char *) (b))[0] & 0xf0)
|
|
#define CGEN_DIS_HASH(buffer, value) \
|
|
(X (buffer) | \
|
|
(X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
|
|
: X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
|
|
: X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
|
|
: ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
|
|
|
|
/* -- */
|
|
|
|
|
|
#endif /* M32R_OPC_H */
|