03388bb71c
sss-bp-on-user-bp.c has an assumption that write to integer can be compiled to a single instruction, which isn't true on some arch, such as arm. This test requires setting two breakpoints on two consecutive instructions, so this patch is to get the address of the next instruction via disassemble and set the 2nd breakpoint there. This approach is portable. This patch fixes the fails in sss-bp-on-user-bp.exp on arm-none-abi target. There is no change in x86 test results. I also revert the patch to PR breakpoints/17000, and verified that the patched sss-bp-on-user-bp.exp still trigger the fail on x86-with-software-single-step. gdb/testsuite: 2014-06-04 Yao Qi <yao@codesourcery.com> * gdb.base/sss-bp-on-user-bp.c (main): Remove comments. * gdb.base/sss-bp-on-user-bp.exp: Don't set breakpoint on "set bar break here". Get the next instruction address and set breakpoint there. Remove "bar break" from the regexp patterns.
30 lines
893 B
C
30 lines
893 B
C
/* This testcase is part of GDB, the GNU debugger.
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Copyright 2014 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include <signal.h>
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#include <unistd.h>
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int
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main (void)
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{
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volatile int i = 0;
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i = 1; /* set foo break here */
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i = 2;
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return 0;
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}
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