9fde51ed30
This patch fixes various bugs in arm_record_exreg_ld_st_insn, and use gdb.reverse/insn-reverse.c to test more arm instructions. - Set flag SINGLE_REG correctly. In the arch reference manual, SING_REG is true when the bit 8 of instruction is zero. - Record the right D registers for instructions changing S registers. - Fix the order of length and address in record_buf_mem array. - Shift the offset by 2 instead of by 24. This patch also fixes one internal error, (gdb) PASS: gdb.reverse/finish-precsave.exp: BP at end of main continue^M Continuing.^M ../../binutils-gdb/gdb/utils.c:1072: internal-error: virtual memory exhausted.^M A problem internal to GDB has been detected,FAIL: gdb.reverse/finish-precsave.exp: run to end of main (GDB internal error) gdb: 2016-02-26 Yao Qi <yao.qi@linaro.org> * arm-tdep.c (arm_record_exreg_ld_st_insn): Set 'single_reg' per bit 8. Check bit 20 instead of bit 4 for VMOV instruction. Record D registers for instructions changing S registers. Change of the order of length and address in record_buf_mem array. gdb/testsuite: 2016-02-26 Yao Qi <yao.qi@linaro.org> * gdb.reverse/insn-reverse.c [__arm__] (ext_reg_load): New. [__arm__] (ext_reg_mov, ext_reg_push_pop): New. (testcases): Update.
164 lines
3.3 KiB
C
164 lines
3.3 KiB
C
/* This testcase is part of GDB, the GNU debugger.
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Copyright 2015-2016 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#if (defined __aarch64__)
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#include <arm_neon.h>
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#endif
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#if (defined __aarch64__)
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static void
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load (void)
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{
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int buf[8];
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asm ("ld1 { v1.8b }, [%[buf]]\n"
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"ld1 { v2.8b, v3.8b }, [%[buf]]\n"
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"ld1 { v3.8b, v4.8b, v5.8b }, [%[buf]]\n"
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:
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: [buf] "r" (buf)
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: /* No clobbers */);
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}
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static void
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move (void)
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{
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float32x2_t b1_ = vdup_n_f32(123.0f);
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float32_t a1_ = 0;
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float64x1_t b2_ = vdup_n_f64(456.0f);
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float64_t a2_ = 0;
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asm ("ins %0.s[0], %w1\n"
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: "=w"(b1_)
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: "r"(a1_), "0"(b1_)
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: /* No clobbers */);
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asm ("ins %0.d[1], %x1\n"
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: "=w"(b2_)
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: "r"(a2_), "0"(b2_)
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: /* No clobbers */);
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}
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static void
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adv_simd_mod_imm (void)
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{
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float32x2_t a1 = {2.0, 4.0};
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asm ("bic %0.2s, #1\n"
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"bic %0.2s, #1, lsl #8\n"
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: "=w"(a1)
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: "0"(a1)
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: /* No clobbers */);
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}
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static void
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adv_simd_scalar_index (void)
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{
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float64x2_t b_ = {0.0, 0.0};
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float64_t a_ = 1.0;
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float64_t result;
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asm ("fmla %d0,%d1,%2.d[1]"
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: "=w"(result)
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: "w"(a_), "w"(b_)
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: /* No clobbers */);
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}
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static void
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adv_simd_smlal (void)
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{
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asm ("smlal v13.2d, v8.2s, v0.2s");
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}
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static void
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adv_simd_vect_shift (void)
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{
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asm ("fcvtzs s0, s0, #1");
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}
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#elif (defined __arm__)
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static void
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ext_reg_load (void)
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{
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char in[8];
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asm ("vldr d0, [%0]" : : "r" (in));
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asm ("vldr s3, [%0]" : : "r" (in));
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asm ("vldm %0, {d3-d4}" : : "r" (in));
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asm ("vldm %0, {s9-s11}" : : "r" (in));
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}
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static void
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ext_reg_mov (void)
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{
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int i, j;
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double d;
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i = 1;
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j = 2;
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asm ("vmov s4, s5, %0, %1" : "=r" (i), "=r" (j): );
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asm ("vmov s7, s8, %0, %1" : "=r" (i), "=r" (j): );
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asm ("vmov %0, %1, s10, s11" : : "r" (i), "r" (j));
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asm ("vmov %0, %1, s1, s2" : : "r" (i), "r" (j));
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asm ("vmov %P2, %0, %1" : "=r" (i), "=r" (j): "w" (d));
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asm ("vmov %1, %2, %P0" : "=w" (d) : "r" (i), "r" (j));
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}
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static void
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ext_reg_push_pop (void)
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{
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double d;
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asm ("vpush {%P0}" : : "w" (d));
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asm ("vpop {%P0}" : : "w" (d));
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}
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#endif
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typedef void (*testcase_ftype) (void);
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/* Functions testing instruction decodings. GDB will read n_testcases
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to know how many functions to test. */
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static testcase_ftype testcases[] =
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{
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#if (defined __aarch64__)
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load,
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move,
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adv_simd_mod_imm,
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adv_simd_scalar_index,
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adv_simd_smlal,
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adv_simd_vect_shift,
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#elif (defined __arm__)
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ext_reg_load,
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ext_reg_mov,
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ext_reg_push_pop,
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#endif
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};
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static int n_testcases = (sizeof (testcases) / sizeof (testcase_ftype));
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int
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main ()
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{
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int i = 0;
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for (i = 0; i < n_testcases; i++)
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testcases[i] ();
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return 0;
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}
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