6146431a2e
* po/opcodes.pot: Regenerate. * po/POTFILES.in: Regenerate. * fr30-opc.c: Regenerate. * fr30-opc.h: Regenerate.
722 lines
18 KiB
C
722 lines
18 KiB
C
/* Generic opcode table support for targets using CGEN. -*- C -*-
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CGEN: Cpu tools GENerator
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THIS FILE IS USED TO GENERATE fr30-opc.c.
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Copyright (C) 1998 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "ansidecl.h"
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#include "libiberty.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "fr30-opc.h"
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#include "opintl.h"
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/* The hash functions are recorded here to help keep assembler code out of
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the disassembler and vice versa. */
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static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
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static unsigned int asm_hash_insn PARAMS ((const char *));
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static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
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static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
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/* Cover function to read and properly byteswap an insn value. */
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CGEN_INSN_INT
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cgen_get_insn_value (od, buf, length)
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CGEN_OPCODE_DESC od;
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unsigned char *buf;
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int length;
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{
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CGEN_INSN_INT value;
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switch (length)
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{
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case 8:
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value = *buf;
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break;
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case 16:
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if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
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value = bfd_getb16 (buf);
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else
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value = bfd_getl16 (buf);
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break;
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case 32:
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if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
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value = bfd_getb32 (buf);
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else
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value = bfd_getl32 (buf);
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break;
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default:
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abort ();
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}
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return value;
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}
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/* Cover function to store an insn value properly byteswapped. */
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void
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cgen_put_insn_value (od, buf, length, value)
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CGEN_OPCODE_DESC od;
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unsigned char *buf;
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int length;
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CGEN_INSN_INT value;
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{
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switch (length)
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{
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case 8:
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buf[0] = value;
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break;
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case 16:
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if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
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bfd_putb16 (value, buf);
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else
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bfd_putl16 (value, buf);
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break;
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case 32:
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if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
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bfd_putb32 (value, buf);
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else
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bfd_putl32 (value, buf);
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break;
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default:
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abort ();
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}
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}
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/* Look up instruction INSN_VALUE and extract its fields.
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INSN, if non-null, is the insn table entry.
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Otherwise INSN_VALUE is examined to compute it.
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LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
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0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
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If INSN != NULL, LENGTH must be valid.
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ALIAS_P is non-zero if alias insns are to be included in the search.
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The result a pointer to the insn table entry, or NULL if the instruction
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wasn't recognized. */
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const CGEN_INSN *
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fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
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CGEN_OPCODE_DESC od;
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const CGEN_INSN *insn;
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CGEN_INSN_BYTES insn_value;
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int length;
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CGEN_FIELDS *fields;
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int alias_p;
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{
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unsigned char buf[16];
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unsigned char *bufp;
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unsigned int base_insn;
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#if CGEN_INT_INSN_P
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CGEN_EXTRACT_INFO *info = NULL;
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#else
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CGEN_EXTRACT_INFO ex_info;
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CGEN_EXTRACT_INFO *info = &ex_info;
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#endif
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#if ! CGEN_INT_INSN_P
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ex_info.dis_info = NULL;
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ex_info.bytes = insn_value;
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ex_info.valid = -1;
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#endif
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if (!insn)
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{
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const CGEN_INSN_LIST *insn_list;
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#if CGEN_INT_INSN_P
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cgen_put_insn_value (od, buf, length, insn_value);
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bufp = buf;
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base_insn = insn_value; /*???*/
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#else
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base_insn = cgen_get_insn_value (od, buf, length);
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bufp = insn_value;
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#endif
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/* The instructions are stored in hash lists.
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Pick the first one and keep trying until we find the right one. */
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insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
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while (insn_list != NULL)
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{
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insn = insn_list->insn;
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if (alias_p
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|| ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
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{
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/* Basic bit mask must be correct. */
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/* ??? May wish to allow target to defer this check until the
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extract handler. */
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if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
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{
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/* ??? 0 is passed for `pc' */
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int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
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insn_value, fields,
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(bfd_vma) 0);
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if (elength > 0)
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{
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/* sanity check */
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if (length != 0 && length != elength)
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abort ();
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return insn;
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}
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}
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}
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insn_list = CGEN_DIS_NEXT_INSN (insn_list);
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}
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}
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else
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{
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/* Sanity check: can't pass an alias insn if ! alias_p. */
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if (! alias_p
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&& CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
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abort ();
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/* Sanity check: length must be correct. */
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if (length != CGEN_INSN_BITSIZE (insn))
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abort ();
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/* ??? 0 is passed for `pc' */
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length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, insn_value, fields,
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(bfd_vma) 0);
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/* Sanity check: must succeed.
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Could relax this later if it ever proves useful. */
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if (length == 0)
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abort ();
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return insn;
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}
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return NULL;
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}
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/* Fill in the operand instances used by INSN whose operands are FIELDS.
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INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
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in. */
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void
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fr30_cgen_get_insn_operands (od, insn, fields, indices)
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CGEN_OPCODE_DESC od;
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const CGEN_INSN * insn;
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const CGEN_FIELDS * fields;
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int *indices;
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{
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const CGEN_OPERAND_INSTANCE *opinst;
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int i;
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for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
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opinst != NULL
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&& CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
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++i, ++opinst)
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{
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const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
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if (op == NULL)
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indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
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else
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indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
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fields);
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}
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}
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/* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
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isn't known.
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The INSN, INSN_VALUE, and LENGTH arguments are passed to
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fr30_cgen_lookup_insn unchanged.
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The result is the insn table entry or NULL if the instruction wasn't
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recognized. */
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const CGEN_INSN *
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fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
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CGEN_OPCODE_DESC od;
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const CGEN_INSN *insn;
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CGEN_INSN_BYTES insn_value;
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int length;
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int *indices;
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{
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CGEN_FIELDS fields;
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/* Pass non-zero for ALIAS_P only if INSN != NULL.
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If INSN == NULL, we want a real insn. */
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insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
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insn != NULL);
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if (! insn)
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return NULL;
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fr30_cgen_get_insn_operands (od, insn, &fields, indices);
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return insn;
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}
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/* Attributes. */
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static const CGEN_ATTR_ENTRY MACH_attr[] =
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{
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{ "base", MACH_BASE },
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{ "fr30", MACH_FR30 },
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{ "max", MACH_MAX },
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{ 0, 0 }
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};
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const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
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{
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{ "CACHE-ADDR", NULL },
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{ "FUN-ACCESS", NULL },
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{ "PC", NULL },
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{ "PROFILE", NULL },
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{ 0, 0 }
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};
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const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
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{
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{ "ABS-ADDR", NULL },
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{ "FAKE", NULL },
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{ "NEGATIVE", NULL },
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{ "PCREL-ADDR", NULL },
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{ "RELAX", NULL },
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{ "SIGN-OPT", NULL },
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{ "UNSIGNED", NULL },
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{ 0, 0 }
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};
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const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
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{
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{ "ALIAS", NULL },
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{ "COND-CTI", NULL },
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{ "NO-DIS", NULL },
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{ "RELAX", NULL },
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{ "RELAXABLE", NULL },
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{ "SKIP-CTI", NULL },
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{ "UNCOND-CTI", NULL },
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{ "VIRTUAL", NULL },
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{ 0, 0 }
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};
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CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
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{
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{ "ac", 13 },
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{ "fp", 14 },
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{ "sp", 15 },
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{ "r0", 0 },
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{ "r1", 1 },
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{ "r2", 2 },
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{ "r3", 3 },
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{ "r4", 4 },
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{ "r5", 5 },
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{ "r6", 6 },
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{ "r7", 7 },
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{ "r8", 8 },
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{ "r9", 9 },
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{ "r10", 10 },
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{ "r11", 11 },
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{ "r12", 12 },
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{ "r13", 13 },
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{ "r14", 14 },
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{ "r15", 15 }
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};
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CGEN_KEYWORD fr30_cgen_opval_h_gr =
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{
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& fr30_cgen_opval_h_gr_entries[0],
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19
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};
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CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
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{
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{ "tbr", 0 },
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{ "rp", 1 },
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{ "ssp", 2 },
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{ "usp", 3 }
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};
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CGEN_KEYWORD fr30_cgen_opval_h_dr =
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{
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& fr30_cgen_opval_h_dr_entries[0],
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4
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};
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CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_mdr_entries[] =
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{
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{ "mdh", 4 },
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{ "mdl", 5 }
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};
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CGEN_KEYWORD fr30_cgen_opval_h_mdr =
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{
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& fr30_cgen_opval_h_mdr_entries[0],
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2
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};
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CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
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{
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{ "pc", 0 },
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{ "ps", 1 }
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};
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CGEN_KEYWORD fr30_cgen_opval_h_cr =
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{
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& fr30_cgen_opval_h_cr_entries[0],
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2
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};
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/* The hardware table. */
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#define HW_ENT(n) fr30_cgen_hw_entries[n]
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static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
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{
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{ HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
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{ HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
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{ HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
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{ HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
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{ HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
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{ HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
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{ HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
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{ HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0, { 0 } } },
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{ HW_H_MDR, & HW_ENT (HW_H_MDR + 1), "h-mdr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_mdr, { 0, 0, { 0 } } },
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{ HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { 0, 0, { 0 } } },
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{ HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
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{ HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
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{ HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
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{ HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
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{ 0 }
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};
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/* The operand table. */
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#define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
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#define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
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const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
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{
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/* pc: program counter */
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{ "pc", & HW_ENT (HW_H_PC), 0, 0,
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{ 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
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/* Ri: destination register */
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{ "Ri", & HW_ENT (HW_H_GR), 12, 4,
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{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
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/* Rj: source register */
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{ "Rj", & HW_ENT (HW_H_GR), 8, 4,
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{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
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/* nbit: negative bit */
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{ "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
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{ 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
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/* vbit: overflow bit */
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{ "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
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{ 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
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/* zbit: zero bit */
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{ "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
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{ 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
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/* cbit: carry bit */
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{ "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
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{ 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
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};
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/* Operand references. */
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#define INPUT CGEN_OPERAND_INSTANCE_INPUT
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#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
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static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
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{ INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
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{ INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
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{ OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
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{ OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
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{ OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
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{ OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
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{ OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
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{ 0 }
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};
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#undef INPUT
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#undef OUTPUT
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#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
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#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
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#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
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/* The instruction table.
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This is currently non-static because the simulator accesses it
|
|
directly. */
|
|
|
|
const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
|
|
{
|
|
/* Special null first entry.
|
|
A `num' value of zero is thus invalid.
|
|
Also, the special `invalid' insn resides here. */
|
|
{ { 0 }, 0 },
|
|
/* add $Rj,$Ri */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
FR30_INSN_ADD, "add", "add",
|
|
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
|
|
{ 16, 16, 0xff00 }, 0xa600,
|
|
(PTR) & fmt_add_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
};
|
|
|
|
#undef A
|
|
#undef MNEM
|
|
#undef OP
|
|
|
|
static const CGEN_INSN_TABLE insn_table =
|
|
{
|
|
& fr30_cgen_insn_table_entries[0],
|
|
sizeof (CGEN_INSN),
|
|
MAX_INSNS,
|
|
NULL
|
|
};
|
|
|
|
/* Each non-simple macro entry points to an array of expansion possibilities. */
|
|
|
|
#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
|
|
#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
|
|
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
|
|
|
|
/* The macro instruction table. */
|
|
|
|
static const CGEN_INSN macro_insn_table_entries[] =
|
|
{
|
|
};
|
|
|
|
#undef A
|
|
#undef MNEM
|
|
#undef OP
|
|
|
|
static const CGEN_INSN_TABLE macro_insn_table =
|
|
{
|
|
& macro_insn_table_entries[0],
|
|
sizeof (CGEN_INSN),
|
|
(sizeof (macro_insn_table_entries) /
|
|
sizeof (macro_insn_table_entries[0])),
|
|
NULL
|
|
};
|
|
|
|
static void
|
|
init_tables ()
|
|
{
|
|
}
|
|
|
|
/* Return non-zero if INSN is to be added to the hash table.
|
|
Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
|
|
|
|
static int
|
|
asm_hash_insn_p (insn)
|
|
const CGEN_INSN * insn;
|
|
{
|
|
return CGEN_ASM_HASH_P (insn);
|
|
}
|
|
|
|
static int
|
|
dis_hash_insn_p (insn)
|
|
const CGEN_INSN * insn;
|
|
{
|
|
/* If building the hash table and the NO-DIS attribute is present,
|
|
ignore. */
|
|
if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
|
|
return 0;
|
|
return CGEN_DIS_HASH_P (insn);
|
|
}
|
|
|
|
/* The result is the hash value of the insn.
|
|
Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
|
|
|
|
static unsigned int
|
|
asm_hash_insn (mnem)
|
|
const char * mnem;
|
|
{
|
|
return CGEN_ASM_HASH (mnem);
|
|
}
|
|
|
|
/* BUF is a pointer to the insn's bytes in target order.
|
|
VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
|
|
host order. */
|
|
|
|
static unsigned int
|
|
dis_hash_insn (buf, value)
|
|
const char * buf;
|
|
unsigned long value;
|
|
{
|
|
return CGEN_DIS_HASH (buf, value);
|
|
}
|
|
|
|
/* Initialize an opcode table and return a descriptor.
|
|
It's much like opening a file, and must be the first function called. */
|
|
|
|
CGEN_OPCODE_DESC
|
|
fr30_cgen_opcode_open (mach, endian)
|
|
int mach;
|
|
enum cgen_endian endian;
|
|
{
|
|
CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
|
|
static int init_p;
|
|
|
|
if (! init_p)
|
|
{
|
|
init_tables ();
|
|
init_p = 1;
|
|
}
|
|
|
|
memset (table, 0, sizeof (*table));
|
|
|
|
CGEN_OPCODE_MACH (table) = mach;
|
|
CGEN_OPCODE_ENDIAN (table) = endian;
|
|
/* FIXME: for the sparc case we can determine insn-endianness statically.
|
|
The worry here is where both data and insn endian can be independently
|
|
chosen, in which case this function will need another argument.
|
|
Actually, will want to allow for more arguments in the future anyway. */
|
|
CGEN_OPCODE_INSN_ENDIAN (table) = endian;
|
|
|
|
CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
|
|
|
|
CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
|
|
|
|
* CGEN_OPCODE_INSN_TABLE (table) = insn_table;
|
|
|
|
* CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
|
|
|
|
CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
|
|
CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
|
|
CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
|
|
|
|
CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
|
|
CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
|
|
CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
|
|
|
|
return (CGEN_OPCODE_DESC) table;
|
|
}
|
|
|
|
/* Close an opcode table. */
|
|
|
|
void
|
|
fr30_cgen_opcode_close (desc)
|
|
CGEN_OPCODE_DESC desc;
|
|
{
|
|
free (desc);
|
|
}
|
|
|
|
/* Getting values from cgen_fields is handled by a collection of functions.
|
|
They are distinguished by the type of the VALUE argument they return.
|
|
TODO: floating point, inlining support, remove cases where result type
|
|
not appropriate. */
|
|
|
|
int
|
|
fr30_cgen_get_int_operand (opindex, fields)
|
|
int opindex;
|
|
const CGEN_FIELDS * fields;
|
|
{
|
|
int value;
|
|
|
|
switch (opindex)
|
|
{
|
|
case FR30_OPERAND_RI :
|
|
value = fields->f_Ri;
|
|
break;
|
|
case FR30_OPERAND_RJ :
|
|
value = fields->f_Rj;
|
|
break;
|
|
|
|
default :
|
|
/* xgettext:c-format */
|
|
fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
|
|
opindex);
|
|
abort ();
|
|
}
|
|
|
|
return value;
|
|
}
|
|
|
|
bfd_vma
|
|
fr30_cgen_get_vma_operand (opindex, fields)
|
|
int opindex;
|
|
const CGEN_FIELDS * fields;
|
|
{
|
|
bfd_vma value;
|
|
|
|
switch (opindex)
|
|
{
|
|
case FR30_OPERAND_RI :
|
|
value = fields->f_Ri;
|
|
break;
|
|
case FR30_OPERAND_RJ :
|
|
value = fields->f_Rj;
|
|
break;
|
|
|
|
default :
|
|
/* xgettext:c-format */
|
|
fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
|
|
opindex);
|
|
abort ();
|
|
}
|
|
|
|
return value;
|
|
}
|
|
|
|
/* Stuffing values in cgen_fields is handled by a collection of functions.
|
|
They are distinguished by the type of the VALUE argument they accept.
|
|
TODO: floating point, inlining support, remove cases where argument type
|
|
not appropriate. */
|
|
|
|
void
|
|
fr30_cgen_set_int_operand (opindex, fields, value)
|
|
int opindex;
|
|
CGEN_FIELDS * fields;
|
|
int value;
|
|
{
|
|
switch (opindex)
|
|
{
|
|
case FR30_OPERAND_RI :
|
|
fields->f_Ri = value;
|
|
break;
|
|
case FR30_OPERAND_RJ :
|
|
fields->f_Rj = value;
|
|
break;
|
|
|
|
default :
|
|
/* xgettext:c-format */
|
|
fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
|
|
opindex);
|
|
abort ();
|
|
}
|
|
}
|
|
|
|
void
|
|
fr30_cgen_set_vma_operand (opindex, fields, value)
|
|
int opindex;
|
|
CGEN_FIELDS * fields;
|
|
bfd_vma value;
|
|
{
|
|
switch (opindex)
|
|
{
|
|
case FR30_OPERAND_RI :
|
|
fields->f_Ri = value;
|
|
break;
|
|
case FR30_OPERAND_RJ :
|
|
fields->f_Rj = value;
|
|
break;
|
|
|
|
default :
|
|
/* xgettext:c-format */
|
|
fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
|
|
opindex);
|
|
abort ();
|
|
}
|
|
}
|
|
|