411 lines
12 KiB
Makefile
411 lines
12 KiB
Makefile
# Makefile template for Configure for the MIPS simulator.
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# Written by Cygnus Support.
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SHELL = @SHELL@
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## COMMON_PRE_CONFIG_FRAG
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srcdir=@srcdir@
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srcroot=$(srcdir)/../../
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# Object files created by various simulator generators.
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SIM_IGEN_OBJ = \
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support.o \
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itable.o \
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semantics.o \
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idecode.o \
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icache.o \
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@mips_igen_engine@ \
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irun.o \
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SIM_M16_OBJ = \
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m16_support.o \
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m16_semantics.o \
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m16_idecode.o \
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m16_icache.o \
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\
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m32_support.o \
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m32_semantics.o \
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m32_idecode.o \
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m32_icache.o \
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\
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itable.o \
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m16run.o \
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SIM_MULTI_OBJ = itable.o @sim_multi_obj@
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MIPS_EXTRA_OBJS = @mips_extra_objs@
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MIPS_EXTRA_LIBS = @mips_extra_libs@
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SIM_OBJS = \
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$(SIM_@sim_gen@_OBJ) \
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$(SIM_NEW_COMMON_OBJS) \
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$(MIPS_EXTRA_OBJS) \
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cp1.o \
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interp.o \
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mdmx.o \
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dsp.o \
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sim-main.o \
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sim-hload.o \
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sim-engine.o \
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sim-stop.o \
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sim-resume.o \
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sim-reason.o \
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# List of flags to always pass to $(CC).
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SIM_SUBTARGET=@SIM_SUBTARGET@
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SIM_EXTRA_CFLAGS = $(SIM_SUBTARGET)
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SIM_EXTRA_CLEAN = clean-extra
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SIM_EXTRA_DISTCLEAN = distclean-extra
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SIM_EXTRA_ALL = $(SIM_@sim_gen@_ALL)
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SIM_EXTRA_LIBS = $(MIPS_EXTRA_LIBS)
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# List of main object files for `run'.
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SIM_RUN_OBJS = nrun.o
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## COMMON_POST_CONFIG_FRAG
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interp.o: $(srcdir)/interp.c config.h sim-main.h itable.h
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cp1.o: $(srcdir)/cp1.c config.h sim-main.h
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mdmx.o: $(srcdir)/mdmx.c $(srcdir)/sim-main.h
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dsp.o: $(srcdir)/dsp.c $(srcdir)/sim-main.h
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multi-run.o: multi-include.h tmp-mach-multi
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../igen/igen:
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cd ../igen && $(MAKE)
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IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
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IGEN_INSN=$(srcdir)/mips.igen
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IGEN_DC=$(srcdir)/mips.dc
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M16_DC=$(srcdir)/m16.dc
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IGEN_INCLUDE=\
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$(srcdir)/m16.igen \
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$(srcdir)/m16e.igen \
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$(srcdir)/mdmx.igen \
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$(srcdir)/mips3d.igen \
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$(srcdir)/sb1.igen \
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$(srcdir)/tx.igen \
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$(srcdir)/vr.igen \
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$(srcdir)/dsp.igen \
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$(srcdir)/dsp2.igen \
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$(srcdir)/mips3264r2.igen \
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# NB: Since these can be built by a number of generators, care
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# must be taken to ensure that they are only dependant on
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# one of those generators.
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BUILT_SRC_FROM_GEN = \
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itable.h \
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itable.c \
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SIM_IGEN_ALL = tmp-igen
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SIM_M16_ALL = tmp-m16
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SIM_MULTI_ALL = tmp-multi
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$(BUILT_SRC_FROM_GEN): $(SIM_@sim_gen@_ALL)
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BUILT_SRC_FROM_IGEN = \
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icache.h \
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icache.c \
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idecode.h \
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idecode.c \
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semantics.h \
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semantics.c \
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model.h \
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model.c \
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support.h \
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support.c \
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engine.h \
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engine.c \
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irun.c \
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$(BUILT_SRC_FROM_IGEN): tmp-igen
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tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
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cd ../igen && $(MAKE)
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../igen/igen \
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$(IGEN_TRACE) \
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-I $(srcdir) \
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-Werror \
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-Wnodiscard \
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@sim_igen_flags@ \
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-G gen-direct-access \
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-G gen-zero-r0 \
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-B 32 \
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-H 31 \
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-i $(IGEN_INSN) \
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-o $(IGEN_DC) \
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-x \
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-n icache.h -hc tmp-icache.h \
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-n icache.c -c tmp-icache.c \
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-n semantics.h -hs tmp-semantics.h \
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-n semantics.c -s tmp-semantics.c \
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-n idecode.h -hd tmp-idecode.h \
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-n idecode.c -d tmp-idecode.c \
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-n model.h -hm tmp-model.h \
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-n model.c -m tmp-model.c \
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-n support.h -hf tmp-support.h \
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-n support.c -f tmp-support.c \
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-n itable.h -ht tmp-itable.h \
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-n itable.c -t tmp-itable.c \
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-n engine.h -he tmp-engine.h \
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-n engine.c -e tmp-engine.c \
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-n irun.c -r tmp-irun.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h icache.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c icache.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h idecode.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c idecode.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h semantics.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c semantics.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-model.h model.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-model.c model.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-support.h support.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-support.c support.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-engine.h engine.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-engine.c engine.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-irun.c irun.c
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touch tmp-igen
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semantics.o: sim-main.h semantics.c $(SIM_EXTRA_DEPS)
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engine.o: sim-main.h engine.c $(SIM_EXTRA_DEPS)
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support.o: sim-main.h support.c $(SIM_EXTRA_DEPS)
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idecode.o: sim-main.h idecode.c $(SIM_EXTRA_DEPS)
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itable.o: sim-main.h itable.c $(SIM_EXTRA_DEPS)
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m16run.o: sim-main.h m16_idecode.h m32_idecode.h $(SIM_EXTRA_DEPS)
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m16_semantics.o: sim-main.h m16_semantics.c $(SIM_EXTRA_DEPS)
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m16_support.o: sim-main.h m16_support.c $(SIM_EXTRA_DEPS)
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m16_idecode.o: sim-main.h m16_idecode.c $(SIM_EXTRA_DEPS)
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m16_icache.o: sim-main.h m16_icache.c $(SIM_EXTRA_DEPS)
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m32_semantics.o: sim-main.h m32_semantics.c $(SIM_EXTRA_DEPS)
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m32_support.o: sim-main.h m32_support.c $(SIM_EXTRA_DEPS)
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m32_idecode.o: sim-main.h m32_idecode.c $(SIM_EXTRA_DEPS)
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m32_icache.o: sim-main.h m32_icache.c $(SIM_EXTRA_DEPS)
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BUILT_SRC_FROM_M16 = \
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m16_icache.h \
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m16_icache.c \
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m16_idecode.h \
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m16_idecode.c \
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m16_semantics.h \
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m16_semantics.c \
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m16_model.h \
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m16_model.c \
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m16_support.h \
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m16_support.c \
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\
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m32_icache.h \
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m32_icache.c \
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m32_idecode.h \
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m32_idecode.c \
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m32_semantics.h \
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m32_semantics.c \
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m32_model.h \
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m32_model.c \
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m32_support.h \
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m32_support.c \
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$(BUILT_SRC_FROM_M16): tmp-m16
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tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
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cd ../igen && $(MAKE)
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../igen/igen \
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$(IGEN_TRACE) \
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-I $(srcdir) \
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-Werror \
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-Wnodiscard \
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@sim_m16_flags@ \
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-G gen-direct-access \
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-G gen-zero-r0 \
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-B 16 \
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-H 15 \
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-i $(IGEN_INSN) \
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-o $(M16_DC) \
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-P m16_ \
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-x \
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-n m16_icache.h -hc tmp-icache.h \
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-n m16_icache.c -c tmp-icache.c \
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-n m16_semantics.h -hs tmp-semantics.h \
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-n m16_semantics.c -s tmp-semantics.c \
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-n m16_idecode.h -hd tmp-idecode.h \
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-n m16_idecode.c -d tmp-idecode.c \
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-n m16_model.h -hm tmp-model.h \
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-n m16_model.c -m tmp-model.c \
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-n m16_support.h -hf tmp-support.h \
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-n m16_support.c -f tmp-support.c \
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#
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$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h m16_icache.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c m16_icache.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h m16_idecode.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c m16_idecode.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h m16_semantics.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c m16_semantics.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-model.h m16_model.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-model.c m16_model.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-support.h m16_support.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-support.c m16_support.c
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../igen/igen \
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$(IGEN_TRACE) \
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-I $(srcdir) \
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-Werror \
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-Wnodiscard \
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@sim_igen_flags@ \
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-G gen-direct-access \
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-G gen-zero-r0 \
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-B 32 \
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-H 31 \
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-i $(IGEN_INSN) \
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-o $(IGEN_DC) \
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-P m32_ \
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-x \
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-n m32_icache.h -hc tmp-icache.h \
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-n m32_icache.c -c tmp-icache.c \
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-n m32_semantics.h -hs tmp-semantics.h \
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-n m32_semantics.c -s tmp-semantics.c \
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-n m32_idecode.h -hd tmp-idecode.h \
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-n m32_idecode.c -d tmp-idecode.c \
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-n m32_model.h -hm tmp-model.h \
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-n m32_model.c -m tmp-model.c \
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-n m32_support.h -hf tmp-support.h \
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-n m32_support.c -f tmp-support.c \
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#
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$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h m32_icache.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c m32_icache.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h m32_idecode.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c m32_idecode.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h m32_semantics.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c m32_semantics.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-model.h m32_model.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-model.c m32_model.c
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$(SHELL) $(srcdir)/../../move-if-change tmp-support.h m32_support.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-support.c m32_support.c
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../igen/igen \
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$(IGEN_TRACE) \
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-I $(srcdir) \
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-Werror \
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-Wnodiscard \
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-Wnowidth \
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@sim_igen_flags@ @sim_m16_flags@ \
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-G gen-direct-access \
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-G gen-zero-r0 \
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-i $(IGEN_INSN) \
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-n itable.h -ht tmp-itable.h \
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-n itable.c -t tmp-itable.c \
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#
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$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
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touch tmp-m16
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BUILT_SRC_FROM_MULTI = @sim_multi_src@
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SIM_MULTI_IGEN_CONFIGS = @sim_multi_igen_configs@
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$(BUILT_SRC_FROM_MULTI): tmp-multi
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tmp-multi: tmp-mach-multi tmp-itable-multi tmp-run-multi targ-vals.h
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tmp-mach-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
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for t in $(SIM_MULTI_IGEN_CONFIGS); do \
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p=`echo $${t} | sed -e 's/:.*//'` ; \
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m=`echo $${t} | sed -e 's/.*:\(.*\):.*/\1/'` ; \
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f=`echo $${t} | sed -e 's/.*://'` ; \
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case $${p} in \
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m16*) e="-B 16 -H 15 -o $(M16_DC) -F 16" ;; \
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*) e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}" ;; \
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esac; \
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../igen/igen \
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$(IGEN_TRACE) \
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$${e} \
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-I $(srcdir) \
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-Werror \
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-Wnodiscard \
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-N 0 \
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-M $${m} \
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-G gen-direct-access \
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-G gen-zero-r0 \
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-i $(IGEN_INSN) \
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-P $${p}_ \
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-x \
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-n $${p}_icache.h -hc tmp-icache.h \
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-n $${p}_icache.c -c tmp-icache.c \
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-n $${p}_semantics.h -hs tmp-semantics.h \
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-n $${p}_semantics.c -s tmp-semantics.c \
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-n $${p}_idecode.h -hd tmp-idecode.h \
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-n $${p}_idecode.c -d tmp-idecode.c \
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-n $${p}_model.h -hm tmp-model.h \
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-n $${p}_model.c -m tmp-model.c \
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-n $${p}_support.h -hf tmp-support.h \
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-n $${p}_support.c -f tmp-support.c \
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-n $${p}_engine.h -he tmp-engine.h \
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-n $${p}_engine.c -e tmp-engine.c \
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; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h $${p}_icache.h ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c $${p}_icache.c ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h $${p}_idecode.h ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c $${p}_idecode.c ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h $${p}_semantics.h ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c $${p}_semantics.c ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-model.h $${p}_model.h ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-model.c $${p}_model.c ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-support.h $${p}_support.h ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-support.c $${p}_support.c ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-engine.h $${p}_engine.h ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-engine.c $${p}_engine.c ; \
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done
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touch tmp-mach-multi
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tmp-itable-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
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../igen/igen \
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$(IGEN_TRACE) \
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-I $(srcdir) \
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-Werror \
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-Wnodiscard \
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-Wnowidth \
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-N 0 \
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@sim_multi_flags@ \
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-G gen-direct-access \
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-G gen-zero-r0 \
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-i $(IGEN_INSN) \
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-n itable.h -ht tmp-itable.h \
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-n itable.c -t tmp-itable.c \
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#
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$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
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touch tmp-itable-multi
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tmp-run-multi: $(srcdir)/m16run.c
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for t in $(SIM_MULTI_IGEN_CONFIGS); do \
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case $${t} in \
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m16*) \
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m=`echo $${t} | sed -e 's/^m16//' -e 's/:.*//'`; \
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sed < $(srcdir)/m16run.c > tmp-run \
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-e "s/^sim_/m16$${m}_/" \
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-e "s/m16_/m16$${m}_/" \
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-e "s/m32_/m32$${m}_/" ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-run m16$${m}_run.c ; \
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esac \
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done
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touch tmp-run-multi
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clean-extra:
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rm -f $(BUILT_SRC_FROM_GEN)
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rm -f $(BUILT_SRC_FROM_IGEN)
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rm -f $(BUILT_SRC_FROM_M16)
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rm -f $(BUILT_SRC_FROM_MULTI)
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rm -f tmp-*
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rm -f m16*.o m32*.o itable*.o
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distclean-extra:
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rm -f multi-include.h multi-run.c
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