b02c4cfa79
* emultempl/ppc32elf.em (emit_stub_syms): Init to -1.
(ppc_after_open): Set emit_stubs_syms by default when shared.
(OPTION_NO_STUBSYMS): Define.
(PARSE_AND_LIST_LONGOPTS, PARSE_AND_LIST_OPTIONS,
PARSE_AND_LIST_ARGS_CASES): Handle --no-emit-stub-syms.
* emultempl/ppc64elf.em (emit_stub_syms): Init to -1.
(gld${EMULATION_NAME}_finish): Set emit_stubs_syms by default.
(OPTION_NO_STUBSYMS): Define.
(PARSE_AND_LIST_LONGOPTS, PARSE_AND_LIST_OPTIONS,
PARSE_AND_LIST_ARGS_CASES): Handle --no-emit-stub-syms.
ld/testsuite/
* ld-powerpc/tlsexe.d: Update.
* ld-powerpc/tlsexe.r: Update.
* ld-powerpc/tlsexetoc.d: Update.
* ld-powerpc/tlsexetoc.r: Update.
* ld-powerpc/tlsso.d: Update.
* ld-powerpc/tlsso.r: Update.
* ld-powerpc/tlstocso.d: Update.
* ld-powerpc/tlstocso.r: Update.
74 lines
2.1 KiB
Makefile
74 lines
2.1 KiB
Makefile
#source: tlstoc.s
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#as: -a64
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#ld: -melf64ppc tmpdir/libtlslib.so
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#objdump: -dr
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#target: powerpc64*-*-*
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.*: +file format elf64-powerpc
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Disassembly of section \.text:
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.* <00000010\.plt_call\.__tls_get_addr(|_opt)\+0>:
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.* e9 63 00 00 ld r11,0\(r3\)
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.* e9 83 00 08 ld r12,8\(r3\)
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.* 7c 60 1b 78 mr r0,r3
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.* 2c 2b 00 00 cmpdi r11,0
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.* 7c 6c 6a 14 add r3,r12,r13
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.* 4d 82 00 20 beqlr
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.* 7c 03 03 78 mr r3,r0
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.* 7d 68 02 a6 mflr r11
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.* f9 61 00 20 std r11,32\(r1\)
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.* f8 41 00 28 std r2,40\(r1\)
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.* e9 62 80 70 ld r11,-32656\(r2\)
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.* 7d 69 03 a6 mtctr r11
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.* e9 62 80 80 ld r11,-32640\(r2\)
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.* e8 42 80 78 ld r2,-32648\(r2\)
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.* 4e 80 04 21 bctrl
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.* e9 61 00 20 ld r11,32\(r1\)
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.* e8 41 00 28 ld r2,40\(r1\)
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.* 7d 68 03 a6 mtlr r11
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.* 4e 80 00 20 blr
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.* <_start>:
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.* 38 62 80 08 addi r3,r2,-32760
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.* 4b ff ff b1 bl .*
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.* 60 00 00 00 nop
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.* 38 62 80 18 addi r3,r2,-32744
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.* 4b ff ff a5 bl .*
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.* 60 00 00 00 nop
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.* 3c 6d 00 00 addis r3,r13,0
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.* 60 00 00 00 nop
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.* 38 63 90 38 addi r3,r3,-28616
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.* 3c 6d 00 00 addis r3,r13,0
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.* 60 00 00 00 nop
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.* 38 63 10 00 addi r3,r3,4096
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.* 39 23 80 40 addi r9,r3,-32704
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.* 3d 23 00 00 addis r9,r3,0
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.* 81 49 80 48 lwz r10,-32696\(r9\)
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.* e9 22 80 48 ld r9,-32696\(r2\)
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.* 7d 49 18 2a ldx r10,r9,r3
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.* 3d 2d 00 00 addis r9,r13,0
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.* a1 49 90 58 lhz r10,-28584\(r9\)
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.* 89 4d 90 60 lbz r10,-28576\(r13\)
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.* 3d 2d 00 00 addis r9,r13,0
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.* 99 49 90 68 stb r10,-28568\(r9\)
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.* 60 00 00 00 nop
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.* 00 00 00 00 .*
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.* 00 01 02 28 .*
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.* <__glink_PLTresolve>:
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.* 7d 88 02 a6 mflr r12
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.* 42 9f 00 05 bcl- 20,4\*cr7\+so,.*
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.* 7d 68 02 a6 mflr r11
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.* e8 4b ff f0 ld r2,-16\(r11\)
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.* 7d 88 03 a6 mtlr r12
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.* 7d 82 5a 14 add r12,r2,r11
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.* e9 6c 00 00 ld r11,0\(r12\)
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.* e8 4c 00 08 ld r2,8\(r12\)
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.* 7d 69 03 a6 mtctr r11
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.* e9 6c 00 10 ld r11,16\(r12\)
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.* 4e 80 04 20 bctr
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.* 60 00 00 00 nop
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.* 60 00 00 00 nop
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.* 60 00 00 00 nop
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.* 38 00 00 00 li r0,0
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.* 4b ff ff c4 b .*
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