1375 lines
30 KiB
C
1375 lines
30 KiB
C
/* Simulator for the moxie processor
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Copyright (C) 2008-2012 Free Software Foundation, Inc.
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Contributed by Anthony Green
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include <signal.h>
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#include <stdlib.h>
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#include "sysdep.h"
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#include <sys/times.h>
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#include <sys/param.h>
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#include <netinet/in.h> /* for byte ordering macros */
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#include "bfd.h"
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#include "gdb/callback.h"
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#include "libiberty.h"
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#include "gdb/remote-sim.h"
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#include "sim-main.h"
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#include "sim-base.h"
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typedef int word;
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typedef unsigned int uword;
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host_callback * callback;
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FILE *tracefile;
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/* Extract the signed 10-bit offset from a 16-bit branch
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instruction. */
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#define INST2OFFSET(o) ((((signed short)((o & ((1<<10)-1))<<6))>>6)<<1)
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#define EXTRACT_WORD(addr) \
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((sim_core_read_aligned_1 (scpu, cia, read_map, addr) << 24) \
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+ (sim_core_read_aligned_1 (scpu, cia, read_map, addr+1) << 16) \
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+ (sim_core_read_aligned_1 (scpu, cia, read_map, addr+2) << 8) \
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+ (sim_core_read_aligned_1 (scpu, cia, read_map, addr+3)))
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unsigned long
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moxie_extract_unsigned_integer (addr, len)
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unsigned char * addr;
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int len;
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{
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unsigned long retval;
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unsigned char * p;
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unsigned char * startaddr = (unsigned char *)addr;
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unsigned char * endaddr = startaddr + len;
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if (len > (int) sizeof (unsigned long))
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printf ("That operation is not available on integers of more than %d bytes.",
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sizeof (unsigned long));
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/* Start at the most significant end of the integer, and work towards
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the least significant. */
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retval = 0;
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for (p = endaddr; p > startaddr;)
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retval = (retval << 8) | * -- p;
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return retval;
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}
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void
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moxie_store_unsigned_integer (addr, len, val)
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unsigned char * addr;
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int len;
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unsigned long val;
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{
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unsigned char * p;
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unsigned char * startaddr = (unsigned char *)addr;
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unsigned char * endaddr = startaddr + len;
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for (p = endaddr; p > startaddr;)
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{
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* -- p = val & 0xff;
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val >>= 8;
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}
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}
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/* moxie register names. */
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static const char *reg_names[16] =
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{ "$fp", "$sp", "$r0", "$r1", "$r2", "$r3", "$r4", "$r5",
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"$r6", "$r7", "$r8", "$r9", "$r10", "$r11", "$r12", "$r13" };
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/* The machine state.
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This state is maintained in host byte order. The fetch/store
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register functions must translate between host byte order and the
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target processor byte order. Keeping this data in target byte
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order simplifies the register read/write functions. Keeping this
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data in native order improves the performance of the simulator.
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Simulation speed is deemed more important. */
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#define NUM_MOXIE_REGS 17 /* Including PC */
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#define NUM_MOXIE_SREGS 256 /* The special registers */
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#define PC_REGNO 16
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/* The ordering of the moxie_regset structure is matched in the
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gdb/config/moxie/tm-moxie.h file in the REGISTER_NAMES macro. */
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struct moxie_regset
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{
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word regs[NUM_MOXIE_REGS + 1]; /* primary registers */
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word sregs[256]; /* special registers */
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word cc; /* the condition code reg */
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int exception;
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unsigned long long insts; /* instruction counter */
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};
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#define CC_GT 1<<0
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#define CC_LT 1<<1
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#define CC_EQ 1<<2
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#define CC_GTU 1<<3
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#define CC_LTU 1<<4
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union
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{
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struct moxie_regset asregs;
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word asints [1]; /* but accessed larger... */
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} cpu;
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static char *myname;
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static SIM_OPEN_KIND sim_kind;
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static int issue_messages = 0;
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void
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sim_size (int s)
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{
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}
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static void
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set_initial_gprs ()
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{
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int i;
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long space;
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/* Set up machine just out of reset. */
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cpu.asregs.regs[PC_REGNO] = 0;
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/* Clean out the register contents. */
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for (i = 0; i < NUM_MOXIE_REGS; i++)
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cpu.asregs.regs[i] = 0;
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for (i = 0; i < NUM_MOXIE_SREGS; i++)
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cpu.asregs.sregs[i] = 0;
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}
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static void
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interrupt ()
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{
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cpu.asregs.exception = SIGINT;
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}
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/* Write a 1 byte value to memory. */
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static void INLINE
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wbat (sim_cpu *scpu, word pc, word x, word v)
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{
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address_word cia = CIA_GET (scpu);
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sim_core_write_aligned_1 (scpu, cia, write_map, x, v);
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}
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/* Write a 2 byte value to memory. */
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static void INLINE
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wsat (sim_cpu *scpu, word pc, word x, word v)
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{
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address_word cia = CIA_GET (scpu);
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sim_core_write_aligned_2 (scpu, cia, write_map, x, v);
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}
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/* Write a 4 byte value to memory. */
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static void INLINE
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wlat (sim_cpu *scpu, word pc, word x, word v)
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{
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address_word cia = CIA_GET (scpu);
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sim_core_write_aligned_4 (scpu, cia, write_map, x, v);
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}
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/* Read 2 bytes from memory. */
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static int INLINE
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rsat (sim_cpu *scpu, word pc, word x)
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{
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address_word cia = CIA_GET (scpu);
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return (sim_core_read_aligned_2 (scpu, cia, read_map, x));
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}
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/* Read 1 byte from memory. */
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static int INLINE
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rbat (sim_cpu *scpu, word pc, word x)
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{
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address_word cia = CIA_GET (scpu);
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return (sim_core_read_aligned_1 (scpu, cia, read_map, x));
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}
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/* Read 4 bytes from memory. */
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static int INLINE
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rlat (sim_cpu *scpu, word pc, word x)
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{
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address_word cia = CIA_GET (scpu);
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return (sim_core_read_aligned_4 (scpu, cia, read_map, x));
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}
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#define CHECK_FLAG(T,H) if (tflags & T) { hflags |= H; tflags ^= T; }
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unsigned int
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convert_target_flags (unsigned int tflags)
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{
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unsigned int hflags = 0x0;
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CHECK_FLAG(0x0001, O_WRONLY);
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CHECK_FLAG(0x0002, O_RDWR);
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CHECK_FLAG(0x0008, O_APPEND);
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CHECK_FLAG(0x0200, O_CREAT);
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CHECK_FLAG(0x0400, O_TRUNC);
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CHECK_FLAG(0x0800, O_EXCL);
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CHECK_FLAG(0x2000, O_SYNC);
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if (tflags != 0x0)
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fprintf (stderr,
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"Simulator Error: problem converting target open flags for host. 0x%x\n",
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tflags);
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return hflags;
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}
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#define TRACE(str) if (tracing) fprintf(tracefile,"0x%08x, %s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", opc, str, cpu.asregs.regs[0], cpu.asregs.regs[1], cpu.asregs.regs[2], cpu.asregs.regs[3], cpu.asregs.regs[4], cpu.asregs.regs[5], cpu.asregs.regs[6], cpu.asregs.regs[7], cpu.asregs.regs[8], cpu.asregs.regs[9], cpu.asregs.regs[10], cpu.asregs.regs[11], cpu.asregs.regs[12], cpu.asregs.regs[13], cpu.asregs.regs[14], cpu.asregs.regs[15]);
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static int tracing = 0;
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void
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sim_resume (sd, step, siggnal)
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SIM_DESC sd;
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int step, siggnal;
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{
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word pc, opc;
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unsigned long long insts;
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unsigned short inst;
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void (* sigsave)();
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sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
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address_word cia = CIA_GET (scpu);
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sigsave = signal (SIGINT, interrupt);
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cpu.asregs.exception = step ? SIGTRAP: 0;
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pc = cpu.asregs.regs[PC_REGNO];
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insts = cpu.asregs.insts;
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/* Run instructions here. */
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do
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{
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opc = pc;
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/* Fetch the instruction at pc. */
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inst = (sim_core_read_aligned_1 (scpu, cia, read_map, pc) << 8)
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+ sim_core_read_aligned_1 (scpu, cia, read_map, pc+1);
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/* Decode instruction. */
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if (inst & (1 << 15))
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{
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if (inst & (1 << 14))
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{
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/* This is a Form 3 instruction. */
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int opcode = (inst >> 10 & 0xf);
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switch (opcode)
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{
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case 0x00: /* beq */
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{
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TRACE("beq");
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if (cpu.asregs.cc & CC_EQ)
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pc += INST2OFFSET(inst) - 2;
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}
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break;
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case 0x01: /* bne */
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{
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TRACE("bne");
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if (! (cpu.asregs.cc & CC_EQ))
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pc += INST2OFFSET(inst) - 2;
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}
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break;
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case 0x02: /* blt */
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{
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TRACE("blt");
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if (cpu.asregs.cc & CC_LT)
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pc += INST2OFFSET(inst) - 2;
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} break;
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case 0x03: /* bgt */
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{
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TRACE("bgt");
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if (cpu.asregs.cc & CC_GT)
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pc += INST2OFFSET(inst) - 2;
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}
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break;
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case 0x04: /* bltu */
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{
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TRACE("bltu");
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if (cpu.asregs.cc & CC_LTU)
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pc += INST2OFFSET(inst) - 2;
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}
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break;
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case 0x05: /* bgtu */
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{
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TRACE("bgtu");
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if (cpu.asregs.cc & CC_GTU)
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pc += INST2OFFSET(inst) - 2;
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}
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break;
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case 0x06: /* bge */
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{
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TRACE("bge");
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if (cpu.asregs.cc & (CC_GT | CC_EQ))
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pc += INST2OFFSET(inst) - 2;
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}
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break;
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case 0x07: /* ble */
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{
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TRACE("ble");
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if (cpu.asregs.cc & (CC_LT | CC_EQ))
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pc += INST2OFFSET(inst) - 2;
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}
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break;
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case 0x08: /* bgeu */
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{
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TRACE("bgeu");
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if (cpu.asregs.cc & (CC_GTU | CC_EQ))
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pc += INST2OFFSET(inst) - 2;
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}
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break;
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case 0x09: /* bleu */
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{
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TRACE("bleu");
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if (cpu.asregs.cc & (CC_LTU | CC_EQ))
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pc += INST2OFFSET(inst) - 2;
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}
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break;
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default:
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{
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TRACE("SIGILL3");
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cpu.asregs.exception = SIGILL;
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break;
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}
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}
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}
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else
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{
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/* This is a Form 2 instruction. */
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int opcode = (inst >> 12 & 0x3);
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switch (opcode)
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{
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case 0x00: /* inc */
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{
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int a = (inst >> 8) & 0xf;
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unsigned av = cpu.asregs.regs[a];
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unsigned v = (inst & 0xff);
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TRACE("inc");
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cpu.asregs.regs[a] = av + v;
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}
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break;
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case 0x01: /* dec */
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{
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int a = (inst >> 8) & 0xf;
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unsigned av = cpu.asregs.regs[a];
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unsigned v = (inst & 0xff);
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TRACE("dec");
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cpu.asregs.regs[a] = av - v;
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}
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break;
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case 0x02: /* gsr */
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{
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int a = (inst >> 8) & 0xf;
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unsigned v = (inst & 0xff);
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TRACE("gsr");
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cpu.asregs.regs[a] = cpu.asregs.sregs[v];
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}
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break;
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case 0x03: /* ssr */
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{
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int a = (inst >> 8) & 0xf;
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unsigned v = (inst & 0xff);
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TRACE("ssr");
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cpu.asregs.sregs[v] = cpu.asregs.regs[a];
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}
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break;
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default:
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TRACE("SIGILL2");
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cpu.asregs.exception = SIGILL;
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break;
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}
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}
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}
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else
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{
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/* This is a Form 1 instruction. */
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int opcode = inst >> 8;
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switch (opcode)
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{
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case 0x00: /* bad */
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opc = opcode;
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TRACE("SIGILL0");
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cpu.asregs.exception = SIGILL;
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break;
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case 0x01: /* ldi.l (immediate) */
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{
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int reg = (inst >> 4) & 0xf;
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TRACE("ldi.l");
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unsigned int val = EXTRACT_WORD(pc+2);
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cpu.asregs.regs[reg] = val;
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pc += 4;
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}
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break;
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case 0x02: /* mov (register-to-register) */
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{
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int dest = (inst >> 4) & 0xf;
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int src = (inst ) & 0xf;
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TRACE("mov");
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cpu.asregs.regs[dest] = cpu.asregs.regs[src];
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}
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break;
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case 0x03: /* jsra */
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{
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unsigned int fn = EXTRACT_WORD(pc+2);
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unsigned int sp = cpu.asregs.regs[1];
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TRACE("jsra");
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/* Save a slot for the static chain. */
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sp -= 4;
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/* Push the return address. */
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sp -= 4;
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wlat (scpu, opc, sp, pc + 6);
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/* Push the current frame pointer. */
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sp -= 4;
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wlat (scpu, opc, sp, cpu.asregs.regs[0]);
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/* Uncache the stack pointer and set the pc and $fp. */
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cpu.asregs.regs[1] = sp;
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cpu.asregs.regs[0] = sp;
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pc = fn - 2;
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}
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break;
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case 0x04: /* ret */
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{
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unsigned int sp = cpu.asregs.regs[0];
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TRACE("ret");
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/* Pop the frame pointer. */
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cpu.asregs.regs[0] = rlat (scpu, opc, sp);
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sp += 4;
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/* Pop the return address. */
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pc = rlat (scpu, opc, sp) - 2;
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sp += 4;
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/* Skip over the static chain slot. */
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sp += 4;
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/* Uncache the stack pointer. */
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cpu.asregs.regs[1] = sp;
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}
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break;
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case 0x05: /* add.l */
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{
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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unsigned av = cpu.asregs.regs[a];
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unsigned bv = cpu.asregs.regs[b];
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TRACE("add.l");
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cpu.asregs.regs[a] = av + bv;
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}
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break;
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case 0x06: /* push */
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{
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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int sp = cpu.asregs.regs[a] - 4;
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TRACE("push");
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wlat (scpu, opc, sp, cpu.asregs.regs[b]);
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cpu.asregs.regs[a] = sp;
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}
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break;
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case 0x07: /* pop */
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{
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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int sp = cpu.asregs.regs[a];
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TRACE("pop");
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cpu.asregs.regs[b] = rlat (scpu, opc, sp);
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cpu.asregs.regs[a] = sp + 4;
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}
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break;
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case 0x08: /* lda.l */
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{
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int reg = (inst >> 4) & 0xf;
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unsigned int addr = EXTRACT_WORD(pc+2);
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TRACE("lda.l");
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cpu.asregs.regs[reg] = rlat (scpu, opc, addr);
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pc += 4;
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}
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break;
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case 0x09: /* sta.l */
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{
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int reg = (inst >> 4) & 0xf;
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unsigned int addr = EXTRACT_WORD(pc+2);
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TRACE("sta.l");
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wlat (scpu, opc, addr, cpu.asregs.regs[reg]);
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pc += 4;
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}
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break;
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case 0x0a: /* ld.l (register indirect) */
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{
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int src = inst & 0xf;
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int dest = (inst >> 4) & 0xf;
|
|
int xv;
|
|
TRACE("ld.l");
|
|
xv = cpu.asregs.regs[src];
|
|
cpu.asregs.regs[dest] = rlat (scpu, opc, xv);
|
|
}
|
|
break;
|
|
case 0x0b: /* st.l */
|
|
{
|
|
int dest = (inst >> 4) & 0xf;
|
|
int val = inst & 0xf;
|
|
TRACE("st.l");
|
|
wlat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
|
|
}
|
|
break;
|
|
case 0x0c: /* ldo.l */
|
|
{
|
|
unsigned int addr = EXTRACT_WORD(pc+2);
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
TRACE("ldo.l");
|
|
addr += cpu.asregs.regs[b];
|
|
cpu.asregs.regs[a] = rlat (scpu, opc, addr);
|
|
pc += 4;
|
|
}
|
|
break;
|
|
case 0x0d: /* sto.l */
|
|
{
|
|
unsigned int addr = EXTRACT_WORD(pc+2);
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
TRACE("sto.l");
|
|
addr += cpu.asregs.regs[a];
|
|
wlat (scpu, opc, addr, cpu.asregs.regs[b]);
|
|
pc += 4;
|
|
}
|
|
break;
|
|
case 0x0e: /* cmp */
|
|
{
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
int cc = 0;
|
|
int va = cpu.asregs.regs[a];
|
|
int vb = cpu.asregs.regs[b];
|
|
|
|
TRACE("cmp");
|
|
|
|
if (va == vb)
|
|
cc = CC_EQ;
|
|
else
|
|
{
|
|
cc |= (va < vb ? CC_LT : 0);
|
|
cc |= (va > vb ? CC_GT : 0);
|
|
cc |= ((unsigned int) va < (unsigned int) vb ? CC_LTU : 0);
|
|
cc |= ((unsigned int) va > (unsigned int) vb ? CC_GTU : 0);
|
|
}
|
|
|
|
cpu.asregs.cc = cc;
|
|
}
|
|
break;
|
|
case 0x0f: /* nop */
|
|
break;
|
|
case 0x10: /* bad */
|
|
case 0x11: /* bad */
|
|
case 0x12: /* bad */
|
|
case 0x13: /* bad */
|
|
case 0x14: /* bad */
|
|
case 0x15: /* bad */
|
|
case 0x16: /* bad */
|
|
case 0x17: /* bad */
|
|
case 0x18: /* bad */
|
|
{
|
|
opc = opcode;
|
|
TRACE("SIGILL0");
|
|
cpu.asregs.exception = SIGILL;
|
|
break;
|
|
}
|
|
case 0x19: /* jsr */
|
|
{
|
|
unsigned int fn = cpu.asregs.regs[(inst >> 4) & 0xf];
|
|
unsigned int sp = cpu.asregs.regs[1];
|
|
|
|
TRACE("jsr");
|
|
|
|
/* Save a slot for the static chain. */
|
|
sp -= 4;
|
|
|
|
/* Push the return address. */
|
|
sp -= 4;
|
|
wlat (scpu, opc, sp, pc + 2);
|
|
|
|
/* Push the current frame pointer. */
|
|
sp -= 4;
|
|
wlat (scpu, opc, sp, cpu.asregs.regs[0]);
|
|
|
|
/* Uncache the stack pointer and set the fp & pc. */
|
|
cpu.asregs.regs[1] = sp;
|
|
cpu.asregs.regs[0] = sp;
|
|
pc = fn - 2;
|
|
}
|
|
break;
|
|
case 0x1a: /* jmpa */
|
|
{
|
|
unsigned int tgt = EXTRACT_WORD(pc+2);
|
|
TRACE("jmpa");
|
|
pc = tgt - 2;
|
|
}
|
|
break;
|
|
case 0x1b: /* ldi.b (immediate) */
|
|
{
|
|
int reg = (inst >> 4) & 0xf;
|
|
|
|
unsigned int val = EXTRACT_WORD(pc+2);
|
|
TRACE("ldi.b");
|
|
cpu.asregs.regs[reg] = val;
|
|
pc += 4;
|
|
}
|
|
break;
|
|
case 0x1c: /* ld.b (register indirect) */
|
|
{
|
|
int src = inst & 0xf;
|
|
int dest = (inst >> 4) & 0xf;
|
|
int xv;
|
|
TRACE("ld.b");
|
|
xv = cpu.asregs.regs[src];
|
|
cpu.asregs.regs[dest] = rbat (scpu, opc, xv);
|
|
}
|
|
break;
|
|
case 0x1d: /* lda.b */
|
|
{
|
|
int reg = (inst >> 4) & 0xf;
|
|
unsigned int addr = EXTRACT_WORD(pc+2);
|
|
TRACE("lda.b");
|
|
cpu.asregs.regs[reg] = rbat (scpu, opc, addr);
|
|
pc += 4;
|
|
}
|
|
break;
|
|
case 0x1e: /* st.b */
|
|
{
|
|
int dest = (inst >> 4) & 0xf;
|
|
int val = inst & 0xf;
|
|
TRACE("st.b");
|
|
wbat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
|
|
}
|
|
break;
|
|
case 0x1f: /* sta.b */
|
|
{
|
|
int reg = (inst >> 4) & 0xf;
|
|
unsigned int addr = EXTRACT_WORD(pc+2);
|
|
TRACE("sta.b");
|
|
wbat (scpu, opc, addr, cpu.asregs.regs[reg]);
|
|
pc += 4;
|
|
}
|
|
break;
|
|
case 0x20: /* ldi.s (immediate) */
|
|
{
|
|
int reg = (inst >> 4) & 0xf;
|
|
|
|
unsigned int val = EXTRACT_WORD(pc+2);
|
|
TRACE("ldi.s");
|
|
cpu.asregs.regs[reg] = val;
|
|
pc += 4;
|
|
}
|
|
break;
|
|
case 0x21: /* ld.s (register indirect) */
|
|
{
|
|
int src = inst & 0xf;
|
|
int dest = (inst >> 4) & 0xf;
|
|
int xv;
|
|
TRACE("ld.s");
|
|
xv = cpu.asregs.regs[src];
|
|
cpu.asregs.regs[dest] = rsat (scpu, opc, xv);
|
|
}
|
|
break;
|
|
case 0x22: /* lda.s */
|
|
{
|
|
int reg = (inst >> 4) & 0xf;
|
|
unsigned int addr = EXTRACT_WORD(pc+2);
|
|
TRACE("lda.s");
|
|
cpu.asregs.regs[reg] = rsat (scpu, opc, addr);
|
|
pc += 4;
|
|
}
|
|
break;
|
|
case 0x23: /* st.s */
|
|
{
|
|
int dest = (inst >> 4) & 0xf;
|
|
int val = inst & 0xf;
|
|
TRACE("st.s");
|
|
wsat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
|
|
}
|
|
break;
|
|
case 0x24: /* sta.s */
|
|
{
|
|
int reg = (inst >> 4) & 0xf;
|
|
unsigned int addr = EXTRACT_WORD(pc+2);
|
|
TRACE("sta.s");
|
|
wsat (scpu, opc, addr, cpu.asregs.regs[reg]);
|
|
pc += 4;
|
|
}
|
|
break;
|
|
case 0x25: /* jmp */
|
|
{
|
|
int reg = (inst >> 4) & 0xf;
|
|
TRACE("jmp");
|
|
pc = cpu.asregs.regs[reg] - 2;
|
|
}
|
|
break;
|
|
case 0x26: /* and */
|
|
{
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
int av, bv;
|
|
TRACE("and");
|
|
av = cpu.asregs.regs[a];
|
|
bv = cpu.asregs.regs[b];
|
|
cpu.asregs.regs[a] = av & bv;
|
|
}
|
|
break;
|
|
case 0x27: /* lshr */
|
|
{
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
int av = cpu.asregs.regs[a];
|
|
int bv = cpu.asregs.regs[b];
|
|
TRACE("lshr");
|
|
cpu.asregs.regs[a] = (unsigned) ((unsigned) av >> bv);
|
|
}
|
|
break;
|
|
case 0x28: /* ashl */
|
|
{
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
int av = cpu.asregs.regs[a];
|
|
int bv = cpu.asregs.regs[b];
|
|
TRACE("ashl");
|
|
cpu.asregs.regs[a] = av << bv;
|
|
}
|
|
break;
|
|
case 0x29: /* sub.l */
|
|
{
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
unsigned av = cpu.asregs.regs[a];
|
|
unsigned bv = cpu.asregs.regs[b];
|
|
TRACE("sub.l");
|
|
cpu.asregs.regs[a] = av - bv;
|
|
}
|
|
break;
|
|
case 0x2a: /* neg */
|
|
{
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
int bv = cpu.asregs.regs[b];
|
|
TRACE("neg");
|
|
cpu.asregs.regs[a] = - bv;
|
|
}
|
|
break;
|
|
case 0x2b: /* or */
|
|
{
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
int av, bv;
|
|
TRACE("or");
|
|
av = cpu.asregs.regs[a];
|
|
bv = cpu.asregs.regs[b];
|
|
cpu.asregs.regs[a] = av | bv;
|
|
}
|
|
break;
|
|
case 0x2c: /* not */
|
|
{
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
int bv = cpu.asregs.regs[b];
|
|
TRACE("not");
|
|
cpu.asregs.regs[a] = 0xffffffff ^ bv;
|
|
}
|
|
break;
|
|
case 0x2d: /* ashr */
|
|
{
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
int av = cpu.asregs.regs[a];
|
|
int bv = cpu.asregs.regs[b];
|
|
TRACE("ashr");
|
|
cpu.asregs.regs[a] = av >> bv;
|
|
}
|
|
break;
|
|
case 0x2e: /* xor */
|
|
{
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
int av, bv;
|
|
TRACE("xor");
|
|
av = cpu.asregs.regs[a];
|
|
bv = cpu.asregs.regs[b];
|
|
cpu.asregs.regs[a] = av ^ bv;
|
|
}
|
|
break;
|
|
case 0x2f: /* mul.l */
|
|
{
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
unsigned av = cpu.asregs.regs[a];
|
|
unsigned bv = cpu.asregs.regs[b];
|
|
TRACE("mul.l");
|
|
cpu.asregs.regs[a] = av * bv;
|
|
}
|
|
break;
|
|
case 0x30: /* swi */
|
|
{
|
|
unsigned int inum = EXTRACT_WORD(pc+2);
|
|
TRACE("swi");
|
|
/* Set the special registers appropriately. */
|
|
cpu.asregs.sregs[2] = 3; /* MOXIE_EX_SWI */
|
|
cpu.asregs.sregs[3] = inum;
|
|
switch (inum)
|
|
{
|
|
case 0x1: /* SYS_exit */
|
|
{
|
|
cpu.asregs.exception = SIGQUIT;
|
|
break;
|
|
}
|
|
case 0x2: /* SYS_open */
|
|
{
|
|
char fname[1024];
|
|
int mode = (int) convert_target_flags ((unsigned) cpu.asregs.regs[3]);
|
|
int perm = (int) cpu.asregs.regs[4];
|
|
int fd = open (fname, mode, perm);
|
|
sim_core_read_buffer (sd, scpu, read_map, fname,
|
|
cpu.asregs.regs[2], 1024);
|
|
/* FIXME - set errno */
|
|
cpu.asregs.regs[2] = fd;
|
|
break;
|
|
}
|
|
case 0x4: /* SYS_read */
|
|
{
|
|
int fd = cpu.asregs.regs[2];
|
|
unsigned len = (unsigned) cpu.asregs.regs[4];
|
|
char *buf = malloc (len);
|
|
cpu.asregs.regs[2] = read (fd, buf, len);
|
|
sim_core_write_buffer (sd, scpu, write_map, buf,
|
|
cpu.asregs.regs[3], len);
|
|
free (buf);
|
|
break;
|
|
}
|
|
case 0x5: /* SYS_write */
|
|
{
|
|
char *str;
|
|
/* String length is at 0x12($fp) */
|
|
unsigned count, len = (unsigned) cpu.asregs.regs[4];
|
|
str = malloc (len);
|
|
sim_core_read_buffer (sd, scpu, read_map, str,
|
|
cpu.asregs.regs[3], len);
|
|
count = write (cpu.asregs.regs[2], str, len);
|
|
free (str);
|
|
cpu.asregs.regs[2] = count;
|
|
break;
|
|
}
|
|
case 0xffffffff: /* Linux System Call */
|
|
{
|
|
unsigned int handler = cpu.asregs.sregs[1];
|
|
unsigned int sp = cpu.asregs.regs[1];
|
|
|
|
/* Save a slot for the static chain. */
|
|
sp -= 4;
|
|
|
|
/* Push the return address. */
|
|
sp -= 4;
|
|
wlat (scpu, opc, sp, pc + 6);
|
|
|
|
/* Push the current frame pointer. */
|
|
sp -= 4;
|
|
wlat (scpu, opc, sp, cpu.asregs.regs[0]);
|
|
|
|
/* Uncache the stack pointer and set the fp & pc. */
|
|
cpu.asregs.regs[1] = sp;
|
|
cpu.asregs.regs[0] = sp;
|
|
pc = handler - 6;
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
pc += 4;
|
|
}
|
|
break;
|
|
case 0x31: /* div.l */
|
|
{
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
int av = cpu.asregs.regs[a];
|
|
int bv = cpu.asregs.regs[b];
|
|
TRACE("div.l");
|
|
cpu.asregs.regs[a] = av / bv;
|
|
}
|
|
break;
|
|
case 0x32: /* udiv.l */
|
|
{
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
unsigned int av = cpu.asregs.regs[a];
|
|
unsigned int bv = cpu.asregs.regs[b];
|
|
TRACE("udiv.l");
|
|
cpu.asregs.regs[a] = (av / bv);
|
|
}
|
|
break;
|
|
case 0x33: /* mod.l */
|
|
{
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
int av = cpu.asregs.regs[a];
|
|
int bv = cpu.asregs.regs[b];
|
|
TRACE("mod.l");
|
|
cpu.asregs.regs[a] = av % bv;
|
|
}
|
|
break;
|
|
case 0x34: /* umod.l */
|
|
{
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
unsigned int av = cpu.asregs.regs[a];
|
|
unsigned int bv = cpu.asregs.regs[b];
|
|
TRACE("umod.l");
|
|
cpu.asregs.regs[a] = (av % bv);
|
|
}
|
|
break;
|
|
case 0x35: /* brk */
|
|
TRACE("brk");
|
|
cpu.asregs.exception = SIGTRAP;
|
|
pc -= 2; /* Adjust pc */
|
|
break;
|
|
case 0x36: /* ldo.b */
|
|
{
|
|
unsigned int addr = EXTRACT_WORD(pc+2);
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
TRACE("ldo.b");
|
|
addr += cpu.asregs.regs[b];
|
|
cpu.asregs.regs[a] = rbat (scpu, opc, addr);
|
|
pc += 4;
|
|
}
|
|
break;
|
|
case 0x37: /* sto.b */
|
|
{
|
|
unsigned int addr = EXTRACT_WORD(pc+2);
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
TRACE("sto.b");
|
|
addr += cpu.asregs.regs[a];
|
|
wbat (scpu, opc, addr, cpu.asregs.regs[b]);
|
|
pc += 4;
|
|
}
|
|
break;
|
|
case 0x38: /* ldo.s */
|
|
{
|
|
unsigned int addr = EXTRACT_WORD(pc+2);
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
TRACE("ldo.s");
|
|
addr += cpu.asregs.regs[b];
|
|
cpu.asregs.regs[a] = rsat (scpu, opc, addr);
|
|
pc += 4;
|
|
}
|
|
break;
|
|
case 0x39: /* sto.s */
|
|
{
|
|
unsigned int addr = EXTRACT_WORD(pc+2);
|
|
int a = (inst >> 4) & 0xf;
|
|
int b = inst & 0xf;
|
|
TRACE("sto.s");
|
|
addr += cpu.asregs.regs[a];
|
|
wsat (scpu, opc, addr, cpu.asregs.regs[b]);
|
|
pc += 4;
|
|
}
|
|
break;
|
|
default:
|
|
opc = opcode;
|
|
TRACE("SIGILL1");
|
|
cpu.asregs.exception = SIGILL;
|
|
break;
|
|
}
|
|
}
|
|
|
|
insts++;
|
|
pc += 2;
|
|
|
|
} while (!cpu.asregs.exception);
|
|
|
|
/* Hide away the things we've cached while executing. */
|
|
cpu.asregs.regs[PC_REGNO] = pc;
|
|
cpu.asregs.insts += insts; /* instructions done ... */
|
|
|
|
signal (SIGINT, sigsave);
|
|
}
|
|
|
|
int
|
|
sim_write (sd, addr, buffer, size)
|
|
SIM_DESC sd;
|
|
SIM_ADDR addr;
|
|
const unsigned char * buffer;
|
|
int size;
|
|
{
|
|
sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
|
|
|
|
sim_core_write_buffer (sd, scpu, write_map, buffer, addr, size);
|
|
|
|
return size;
|
|
}
|
|
|
|
int
|
|
sim_read (sd, addr, buffer, size)
|
|
SIM_DESC sd;
|
|
SIM_ADDR addr;
|
|
unsigned char * buffer;
|
|
int size;
|
|
{
|
|
sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
|
|
|
|
sim_core_read_buffer (sd, scpu, read_map, buffer, addr, size);
|
|
|
|
return size;
|
|
}
|
|
|
|
|
|
int
|
|
sim_store_register (sd, rn, memory, length)
|
|
SIM_DESC sd;
|
|
int rn;
|
|
unsigned char * memory;
|
|
int length;
|
|
{
|
|
if (rn < NUM_MOXIE_REGS && rn >= 0)
|
|
{
|
|
if (length == 4)
|
|
{
|
|
long ival;
|
|
|
|
/* misalignment safe */
|
|
ival = moxie_extract_unsigned_integer (memory, 4);
|
|
cpu.asints[rn] = ival;
|
|
}
|
|
|
|
return 4;
|
|
}
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
sim_fetch_register (sd, rn, memory, length)
|
|
SIM_DESC sd;
|
|
int rn;
|
|
unsigned char * memory;
|
|
int length;
|
|
{
|
|
if (rn < NUM_MOXIE_REGS && rn >= 0)
|
|
{
|
|
if (length == 4)
|
|
{
|
|
long ival = cpu.asints[rn];
|
|
|
|
/* misalignment-safe */
|
|
moxie_store_unsigned_integer (memory, 4, ival);
|
|
}
|
|
|
|
return 4;
|
|
}
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
|
|
int
|
|
sim_trace (sd)
|
|
SIM_DESC sd;
|
|
{
|
|
if (tracefile == 0)
|
|
tracefile = fopen("trace.csv", "wb");
|
|
|
|
tracing = 1;
|
|
|
|
sim_resume (sd, 0, 0);
|
|
|
|
tracing = 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
void
|
|
sim_stop_reason (sd, reason, sigrc)
|
|
SIM_DESC sd;
|
|
enum sim_stop * reason;
|
|
int * sigrc;
|
|
{
|
|
if (cpu.asregs.exception == SIGQUIT)
|
|
{
|
|
* reason = sim_exited;
|
|
* sigrc = cpu.asregs.regs[2];
|
|
}
|
|
else
|
|
{
|
|
* reason = sim_stopped;
|
|
* sigrc = cpu.asregs.exception;
|
|
}
|
|
}
|
|
|
|
|
|
int
|
|
sim_stop (sd)
|
|
SIM_DESC sd;
|
|
{
|
|
cpu.asregs.exception = SIGINT;
|
|
return 1;
|
|
}
|
|
|
|
|
|
void
|
|
sim_info (sd, verbose)
|
|
SIM_DESC sd;
|
|
int verbose;
|
|
{
|
|
callback->printf_filtered (callback, "\n\n# instructions executed %llu\n",
|
|
cpu.asregs.insts);
|
|
}
|
|
|
|
|
|
SIM_DESC
|
|
sim_open (kind, cb, abfd, argv)
|
|
SIM_OPEN_KIND kind;
|
|
host_callback * cb;
|
|
struct bfd * abfd;
|
|
char ** argv;
|
|
{
|
|
SIM_DESC sd = sim_state_alloc (kind, cb);
|
|
printf ("0x%x 0x%x\n", sd, STATE_MAGIC(sd));
|
|
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
|
|
|
|
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
|
|
return 0;
|
|
|
|
sim_do_command(sd," memory region 0x00000000,0x4000000") ;
|
|
sim_do_command(sd," memory region 0xE0000000,0x10000") ;
|
|
|
|
myname = argv[0];
|
|
callback = cb;
|
|
|
|
if (kind == SIM_OPEN_STANDALONE)
|
|
issue_messages = 1;
|
|
|
|
set_initial_gprs (); /* Reset the GPR registers. */
|
|
|
|
/* Configure/verify the target byte order and other runtime
|
|
configuration options. */
|
|
if (sim_config (sd) != SIM_RC_OK)
|
|
{
|
|
sim_module_uninstall (sd);
|
|
return 0;
|
|
}
|
|
|
|
if (sim_post_argv_init (sd) != SIM_RC_OK)
|
|
{
|
|
/* Uninstall the modules to avoid memory leaks,
|
|
file descriptor leaks, etc. */
|
|
sim_module_uninstall (sd);
|
|
return 0;
|
|
}
|
|
|
|
return sd;
|
|
}
|
|
|
|
void
|
|
sim_close (sd, quitting)
|
|
SIM_DESC sd;
|
|
int quitting;
|
|
{
|
|
/* nothing to do */
|
|
}
|
|
|
|
|
|
/* Load the device tree blob. */
|
|
|
|
static void
|
|
load_dtb (SIM_DESC sd, const char *filename)
|
|
{
|
|
int size = 0;
|
|
FILE *f = fopen (filename, "rb");
|
|
char *buf;
|
|
sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
|
|
if (f == NULL)
|
|
{
|
|
printf ("WARNING: ``%s'' could not be opened.\n", filename);
|
|
return;
|
|
}
|
|
fseek (f, 0, SEEK_END);
|
|
size = ftell(f);
|
|
fseek (f, 0, SEEK_SET);
|
|
buf = alloca (size);
|
|
if (size != fread (buf, 1, size, f))
|
|
{
|
|
printf ("ERROR: error reading ``%s''.\n", filename);
|
|
return;
|
|
}
|
|
sim_core_write_buffer (sd, scpu, write_map, buf, 0xE0000000, size);
|
|
cpu.asregs.sregs[9] = 0xE0000000;
|
|
fclose (f);
|
|
}
|
|
|
|
SIM_RC
|
|
sim_load (sd, prog, abfd, from_tty)
|
|
SIM_DESC sd;
|
|
char * prog;
|
|
bfd * abfd;
|
|
int from_tty;
|
|
{
|
|
|
|
/* Do the right thing for ELF executables; this turns out to be
|
|
just about the right thing for any object format that:
|
|
- we crack using BFD routines
|
|
- follows the traditional UNIX text/data/bss layout
|
|
- calls the bss section ".bss". */
|
|
|
|
extern bfd * sim_load_file (); /* ??? Don't know where this should live. */
|
|
bfd * prog_bfd;
|
|
|
|
{
|
|
bfd * handle;
|
|
handle = bfd_openr (prog, 0); /* could be "moxie" */
|
|
|
|
if (!handle)
|
|
{
|
|
printf("``%s'' could not be opened.\n", prog);
|
|
return SIM_RC_FAIL;
|
|
}
|
|
|
|
/* Makes sure that we have an object file, also cleans gets the
|
|
section headers in place. */
|
|
if (!bfd_check_format (handle, bfd_object))
|
|
{
|
|
/* wasn't an object file */
|
|
bfd_close (handle);
|
|
printf ("``%s'' is not appropriate object file.\n", prog);
|
|
return SIM_RC_FAIL;
|
|
}
|
|
|
|
/* Clean up after ourselves. */
|
|
bfd_close (handle);
|
|
}
|
|
|
|
/* from sh -- dac */
|
|
prog_bfd = sim_load_file (sd, myname, callback, prog, abfd,
|
|
sim_kind == SIM_OPEN_DEBUG,
|
|
0, sim_write);
|
|
if (prog_bfd == NULL)
|
|
return SIM_RC_FAIL;
|
|
|
|
if (abfd == NULL)
|
|
bfd_close (prog_bfd);
|
|
|
|
return SIM_RC_OK;
|
|
}
|
|
|
|
SIM_RC
|
|
sim_create_inferior (sd, prog_bfd, argv, env)
|
|
SIM_DESC sd;
|
|
struct bfd * prog_bfd;
|
|
char ** argv;
|
|
char ** env;
|
|
{
|
|
char ** avp;
|
|
int l, argc, i, tp;
|
|
sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
|
|
|
|
/* Set the initial register set. */
|
|
l = issue_messages;
|
|
issue_messages = 0;
|
|
set_initial_gprs ();
|
|
issue_messages = l;
|
|
|
|
if (prog_bfd != NULL)
|
|
cpu.asregs.regs[PC_REGNO] = bfd_get_start_address (prog_bfd);
|
|
|
|
/* Copy args into target memory. */
|
|
avp = argv;
|
|
for (argc = 0; avp && *avp; avp++)
|
|
argc++;
|
|
|
|
/* Target memory looks like this:
|
|
0x00000000 zero word
|
|
0x00000004 argc word
|
|
0x00000008 start of argv
|
|
.
|
|
0x0000???? end of argv
|
|
0x0000???? zero word
|
|
0x0000???? start of data pointed to by argv */
|
|
|
|
wlat (scpu, 0, 0, 0);
|
|
wlat (scpu, 0, 4, argc);
|
|
|
|
/* tp is the offset of our first argv data. */
|
|
tp = 4 + 4 + argc * 4 + 4;
|
|
|
|
for (i = 0; i < argc; i++)
|
|
{
|
|
/* Set the argv value. */
|
|
wlat (scpu, 0, 4 + 4 + i * 4, tp);
|
|
|
|
/* Store the string. */
|
|
sim_core_write_buffer (sd, scpu, write_map, argv[i],
|
|
tp, strlen(argv[i])+1);
|
|
tp += strlen (argv[i]) + 1;
|
|
}
|
|
|
|
wlat (scpu, 0, 4 + 4 + i * 4, 0);
|
|
|
|
load_dtb (sd, DTB);
|
|
|
|
return SIM_RC_OK;
|
|
}
|
|
|
|
void
|
|
sim_kill (sd)
|
|
SIM_DESC sd;
|
|
{
|
|
if (tracefile)
|
|
fclose(tracefile);
|
|
}
|
|
|
|
void
|
|
sim_do_command (sd, cmd)
|
|
SIM_DESC sd;
|
|
char * cmd;
|
|
{
|
|
if (sim_args_command (sd, cmd) != SIM_RC_OK)
|
|
sim_io_printf (sd,
|
|
"Error: \"%s\" is not a valid moxie simulator command.\n",
|
|
cmd);
|
|
}
|
|
|
|
void
|
|
sim_set_callbacks (ptr)
|
|
host_callback * ptr;
|
|
{
|
|
callback = ptr;
|
|
}
|