Mike Frysinger 39c1f96aef sim: bfin: use store buffer for VIT_MAX insns ... The VIT_MAX insns can be used in parallel, so we need to use the store buffer so we don't clobber the output register before we get a chance to do a memory store with it. Reported-by: Kai Iskratsch <kai@stella.at> Signed-off-by: Mike Frysinger <vapier@gentoo.org>		2011-09-29 03:19:47 +00:00
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.gitignore
7641.s
10272_small.s
10436.s
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c_seq_ex1_raise_call_mv_pop.S
c_seq_ex1_raise_j_mv_pop.S
c_seq_ex2_brcc_mp_mv_pop.S
c_seq_ex2_mmr_mvpop.S
c_seq_ex2_mmrj_mvpop.S
c_seq_ex2_raise_mmr_mvpop.S
c_seq_ex2_raise_mmrj_mvpop.S
c_seq_ex3_ls_brcc_mvp.S
c_seq_ex3_ls_mmr_mvp.S
c_seq_ex3_ls_mmrj_mvp.S
c_seq_ex3_raise_ls_mmrj_mvp.S
c_seq_wb_cs_lsmmrj_mvp.S
c_seq_wb_raisecs_lsmmrj_mvp.S
c_seq_wb_rti_lsmmrj_mvp.S
c_seq_wb_rtn_lsmmrj_mvp.S
c_seq_wb_rtx_lsmmrj_mvp.S
c_ujump.s
cc-alu.S
cc-astat-bits.s
cc0.s
cc1.s
cc5.S
cec-exact-exception.S
cec-ifetch.S
cec-multi-pending.S
cec-no-snen-reti.S
cec-non-operating-env.s
cec-raise-reti.S
cec-snen-reti.S
cec-syscfg-ssstep.S
cec-system-call.S
ChangeLog	sim: bfin: use store buffer for VIT_MAX insns	2011-09-29 03:19:47 +00:00
cir.s
cir1.s
cli-sti.s
cmpacc.s
cmpdreg.S
compare.s
conv_enc_gen.s
cycles.s
d0.s
d1.s
d2.s
dbg_brprd_ntkn_src_kill.S
dbg_brtkn_nprd_src_kill.S
dbg_jmp_src_kill.S
dbg_tr_basic.S
dbg_tr_simplejp.S
dbg_tr_tbuf0.S
dbg_tr_umode.S
disalnexcpt_implicit.S
div0.s
divq.s
dotproduct.s
dotproduct2.s
double_prec_mult.s
dsp_a4.s
dsp_a7.s
dsp_a8.s
dsp_d0.s
dsp_d1.s
dsp_neg.S
dsp_s1.s
e0.s
edn_snafu.s
eu_dsp32mac_s.s
events.s
f221.s
fact.s
fir.s
fsm.s
greg2.s
hwloop-bits.S
hwloop-branch-in.s
hwloop-branch-out.s
hwloop-lt-bits.s
hwloop-nested.s
i0.s
iir.s
issue83.s
issue89.s
issue103.s
issue109.s
issue112.s
issue113.s
issue117.s
issue118.s
issue119.s
issue121.s
issue123.s
issue124.s
issue125.s
issue126.s
issue127.s
issue129.s
issue139.S
issue140.S
issue142.s
issue144.s
issue146.S
issue175.s
issue205.s
issue257.s
issue272.S
l0.s
l0shift.s
l2_loop.s
link-2.s
link.s
lmu_cplb_multiple0.S
lmu_cplb_multiple1.S
lmu_excpt_align.S
lmu_excpt_default.S
lmu_excpt_illaddr.S
lmu_excpt_prot0.S
lmu_excpt_prot1.S
load.s
logic.s
loop_snafu.s
loop_strncpy.s
lp0.s
lp1.s
lsetup.s
m0boundary.s
m1.S
m2.s
m3.s
m4.s
m5.s
m6.s
m7.s
m8.s
m9.s
m10.s
m11.s
m12.s
m13.s
m14.s
m15.s
m16.s
m17.s
mac2halfreg.S
math.s
max_min_flags.s
mc_s2.s
mdma-8bit-1d-neg-count.c
mdma-8bit-1d.c
mdma-32bit-1d-neg-count.c
mdma-32bit-1d.c
mdma-skel.h
mem3.s
mmr-exception.s
move.s
msa_acp_5.10.S
msa_acp_5.12_1.S
msa_acp_5.12_2.S
msa_acp_5_10.s
mult.s
neg-2.S
neg-3.S
neg.S
nshift.s
PN_generator.s
pr.s
push-pop-multiple.s
push-pop.s
pushpopreg_1.s
quadaddsub.s
random_0001.s
random_0002.S
random_0003.S
random_0004.S
random_0005.S
random_0006.S
random_0007.S
random_0008.S
random_0009.S
random_0010.S
random_0011.S
random_0012.S
random_0013.S
random_0019.S	sim: bfin: add tests for recent dsp fixes	2011-06-18 20:27:26 +00:00
random_0020.S	sim: bfin: add tests for recent dsp fixes	2011-06-18 20:27:26 +00:00
random_0021.S	sim: bfin: add tests for recent dsp fixes	2011-06-18 20:27:26 +00:00
random_0022.S	sim: bfin: add tests for recent dsp fixes	2011-06-18 20:27:26 +00:00
random_0023.S	sim: bfin: add tests for recent dsp fixes	2011-06-18 20:27:26 +00:00
random_0024.S	sim: bfin: add tests for recent dsp fixes	2011-06-18 20:27:26 +00:00
random_0026.S	sim: bfin: add tests for recent dsp fixes	2011-06-18 20:27:26 +00:00
random_0027.S	sim: bfin: add tests for recent dsp fixes	2011-06-18 20:27:26 +00:00
random_0028.S	sim: bfin: add tests for recent dsp fixes	2011-06-18 20:27:26 +00:00
random_0029.S	sim: bfin: add tests for recent dsp fixes	2011-06-18 20:27:26 +00:00
random_0030.S	sim: bfin: add tests for recent dsp fixes	2011-06-18 20:27:26 +00:00
random_0031.S
random_0032.S	sim: bfin: add tests for recent dsp fixes	2011-06-18 20:27:26 +00:00
random_0033.S
random_0034.S
random_0035.S	sim: bfin: add tests for recent dsp fixes	2011-06-18 20:27:26 +00:00
run-tests.sh
s0.s
s1.s
s2.s
s3.s
s4.s
s5.s
s6.s
s7.s
s8.s
s9.s
s10.s
s11.s
s12.s
s13.s
s14.s
s15.s
s16.s
s17.s
s18.s
s19.s
s20.s
s21.s
s30.s
saatest.s
se_all16bitopcodes.S
se_all32bitopcodes.lds
se_all32bitopcodes.S
se_brtarget_stall.S
se_bug_ui.S
se_bug_ui2.S
se_bug_ui3.S
se_cc2stat_haz.S
se_cc_kill.S
se_cof.S
se_event_quad.S
se_excpt_dagprotviol.S
se_excpt_ifprotviol.S
se_excpt_ssstep.S
se_illegalcombination.S
se_kill_wbbr.S
se_kills2.S
se_loop_disable.S
se_loop_kill.S
se_loop_kill_01.S
se_loop_kill_dcr.S
se_loop_kill_dcr_01.S
se_loop_lr.S
se_loop_mv2lb_stall.S
se_loop_mv2lc.S
se_loop_mv2lc_stall.S
se_loop_mv2lt_stall.S
se_loop_nest_ppm.S
se_loop_nest_ppm_1.S
se_loop_nest_ppm_2.S
se_loop_ppm.S
se_loop_ppm_1.S
se_loop_ppm_int.S
se_lsetup_kill.S
se_misaligned_fetch.S
se_more_ret_haz.S
se_mv2lp.S
se_oneins_zoff.S
se_popkill.S
se_regmv_usp_sysreg.S
se_rets_hazard.s
se_rts_rti.S
se_ssstep_dagprotviol.S
se_ssync.S
se_stall_if2.S
se_undefinedinstruction1.S
se_undefinedinstruction2.S
se_undefinedinstruction3.S
se_undefinedinstruction4.S
se_usermode_protviol.S
seqstat.s
sign.s
simple0.s
sri.s
stk.s
stk2.s
stk3.s
stk4.s
stk5.s
stk6.s
syscfg.s
tar10622.s
test-dma.h
test.h
testset.s
testset2.s
testutils.inc
unlink.S
up0.s
usp.S
vec-abs-2.S
vec-abs-3.S
vec-abs.S
vec-neg-2.S
vec-neg-3.S
vec-neg.S
vecadd.s
vit_max.s
vit_max2.s	sim: bfin: use store buffer for VIT_MAX insns	2011-09-29 03:19:47 +00:00
viterbi2.s
wtf.s
x1.s
zcall.s
zeroflagrnd.s