296b1496f7
This commit makes nat/x86-dregs.c include common-defs.h rather than defs.h or server.h. An extra header required including in order to support this change. gdb/ChangeLog: * nat/x86-dregs.c: Include common-defs.h and break-common.h. Don't include defs.h or server.h.
655 lines
21 KiB
C
655 lines
21 KiB
C
/* Debug register code for x86 (i386 and x86-64).
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Copyright (C) 2001-2014 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "common-defs.h"
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#include "x86-dregs.h"
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#include "break-common.h"
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/* Support for hardware watchpoints and breakpoints using the x86
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debug registers.
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This provides several functions for inserting and removing
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hardware-assisted breakpoints and watchpoints, testing if one or
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more of the watchpoints triggered and at what address, checking
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whether a given region can be watched, etc.
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The functions below implement debug registers sharing by reference
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counts, and allow to watch regions up to 16 bytes long. */
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/* Accessor macros for low-level function vector. */
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/* Can we update the inferior's debug registers? */
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#define x86_dr_low_can_set_addr() (x86_dr_low.set_addr != NULL)
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/* Update the inferior's debug register REGNUM from STATE. */
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#define x86_dr_low_set_addr(new_state, i) \
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(x86_dr_low.set_addr ((i), (new_state)->dr_mirror[(i)]))
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/* Return the inferior's debug register REGNUM. */
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#define x86_dr_low_get_addr(i) (x86_dr_low.get_addr ((i)))
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/* Can we update the inferior's DR7 control register? */
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#define x86_dr_low_can_set_control() (x86_dr_low.set_control != NULL)
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/* Update the inferior's DR7 debug control register from STATE. */
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#define x86_dr_low_set_control(new_state) \
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(x86_dr_low.set_control ((new_state)->dr_control_mirror))
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/* Return the value of the inferior's DR7 debug control register. */
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#define x86_dr_low_get_control() (x86_dr_low.get_control ())
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/* Return the value of the inferior's DR6 debug status register. */
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#define x86_dr_low_get_status() (x86_dr_low.get_status ())
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/* Return the debug register size, in bytes. */
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#define x86_get_debug_register_length() \
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(x86_dr_low.debug_register_length)
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/* Support for 8-byte wide hw watchpoints. */
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#define TARGET_HAS_DR_LEN_8 (x86_get_debug_register_length () == 8)
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/* DR7 Debug Control register fields. */
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/* How many bits to skip in DR7 to get to R/W and LEN fields. */
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#define DR_CONTROL_SHIFT 16
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/* How many bits in DR7 per R/W and LEN field for each watchpoint. */
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#define DR_CONTROL_SIZE 4
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/* Watchpoint/breakpoint read/write fields in DR7. */
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#define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */
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#define DR_RW_WRITE (0x1) /* Break on data writes. */
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#define DR_RW_READ (0x3) /* Break on data reads or writes. */
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/* This is here for completeness. No platform supports this
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functionality yet (as of March 2001). Note that the DE flag in the
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CR4 register needs to be set to support this. */
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#ifndef DR_RW_IORW
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#define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */
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#endif
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/* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
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is so we could OR this with the read/write field defined above. */
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#define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */
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#define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */
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#define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */
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#define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */
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/* Local and Global Enable flags in DR7.
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When the Local Enable flag is set, the breakpoint/watchpoint is
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enabled only for the current task; the processor automatically
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clears this flag on every task switch. When the Global Enable flag
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is set, the breakpoint/watchpoint is enabled for all tasks; the
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processor never clears this flag.
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Currently, all watchpoint are locally enabled. If you need to
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enable them globally, read the comment which pertains to this in
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x86_insert_aligned_watchpoint below. */
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#define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */
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#define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */
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#define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */
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/* Local and global exact breakpoint enable flags (a.k.a. slowdown
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flags). These are only required on i386, to allow detection of the
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exact instruction which caused a watchpoint to break; i486 and
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later processors do that automatically. We set these flags for
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backwards compatibility. */
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#define DR_LOCAL_SLOWDOWN (0x100)
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#define DR_GLOBAL_SLOWDOWN (0x200)
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/* Fields reserved by Intel. This includes the GD (General Detect
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Enable) flag, which causes a debug exception to be generated when a
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MOV instruction accesses one of the debug registers.
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FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
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#define DR_CONTROL_RESERVED (0xFC00)
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/* Auxiliary helper macros. */
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/* A value that masks all fields in DR7 that are reserved by Intel. */
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#define X86_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
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/* The I'th debug register is vacant if its Local and Global Enable
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bits are reset in the Debug Control register. */
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#define X86_DR_VACANT(state, i) \
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(((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
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/* Locally enable the break/watchpoint in the I'th debug register. */
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#define X86_DR_LOCAL_ENABLE(state, i) \
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do { \
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(state)->dr_control_mirror |= \
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(1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
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} while (0)
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/* Globally enable the break/watchpoint in the I'th debug register. */
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#define X86_DR_GLOBAL_ENABLE(state, i) \
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do { \
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(state)->dr_control_mirror |= \
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(1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
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} while (0)
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/* Disable the break/watchpoint in the I'th debug register. */
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#define X86_DR_DISABLE(state, i) \
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do { \
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(state)->dr_control_mirror &= \
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~(3 << (DR_ENABLE_SIZE * (i))); \
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} while (0)
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/* Set in DR7 the RW and LEN fields for the I'th debug register. */
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#define X86_DR_SET_RW_LEN(state, i, rwlen) \
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do { \
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(state)->dr_control_mirror &= \
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~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
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(state)->dr_control_mirror |= \
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((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
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} while (0)
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/* Get from DR7 the RW and LEN fields for the I'th debug register. */
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#define X86_DR_GET_RW_LEN(dr7, i) \
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(((dr7) \
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>> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
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/* Did the watchpoint whose address is in the I'th register break? */
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#define X86_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i)))
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/* Types of operations supported by x86_handle_nonaligned_watchpoint. */
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typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } x86_wp_op_t;
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/* Print the values of the mirrored debug registers. */
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static void
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x86_show_dr (struct x86_debug_reg_state *state,
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const char *func, CORE_ADDR addr,
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int len, enum target_hw_bp_type type)
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{
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int i;
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debug_printf ("%s", func);
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if (addr || len)
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debug_printf (" (addr=%s, len=%d, type=%s)",
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phex (addr, 8), len,
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type == hw_write ? "data-write"
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: (type == hw_read ? "data-read"
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: (type == hw_access ? "data-read/write"
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: (type == hw_execute ? "instruction-execute"
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/* FIXME: if/when I/O read/write
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watchpoints are supported, add them
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here. */
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: "??unknown??"))));
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debug_printf (":\n");
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debug_printf ("\tCONTROL (DR7): %s STATUS (DR6): %s\n",
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phex (state->dr_control_mirror, 8),
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phex (state->dr_status_mirror, 8));
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ALL_DEBUG_ADDRESS_REGISTERS (i)
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{
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debug_printf ("\
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\tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n",
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i, phex (state->dr_mirror[i],
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x86_get_debug_register_length ()),
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state->dr_ref_count[i],
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i + 1, phex (state->dr_mirror[i + 1],
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x86_get_debug_register_length ()),
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state->dr_ref_count[i + 1]);
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i++;
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}
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}
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/* Return the value of a 4-bit field for DR7 suitable for watching a
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region of LEN bytes for accesses of type TYPE. LEN is assumed to
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have the value of 1, 2, or 4. */
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static unsigned
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x86_length_and_rw_bits (int len, enum target_hw_bp_type type)
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{
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unsigned rw;
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switch (type)
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{
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case hw_execute:
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rw = DR_RW_EXECUTE;
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break;
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case hw_write:
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rw = DR_RW_WRITE;
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break;
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case hw_read:
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internal_error (__FILE__, __LINE__,
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_("The i386 doesn't support "
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"data-read watchpoints.\n"));
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case hw_access:
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rw = DR_RW_READ;
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break;
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#if 0
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/* Not yet supported. */
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case hw_io_access:
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rw = DR_RW_IORW;
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break;
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#endif
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default:
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internal_error (__FILE__, __LINE__, _("\
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Invalid hardware breakpoint type %d in x86_length_and_rw_bits.\n"),
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(int) type);
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}
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switch (len)
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{
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case 1:
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return (DR_LEN_1 | rw);
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case 2:
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return (DR_LEN_2 | rw);
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case 4:
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return (DR_LEN_4 | rw);
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case 8:
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if (TARGET_HAS_DR_LEN_8)
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return (DR_LEN_8 | rw);
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/* ELSE FALL THROUGH */
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default:
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internal_error (__FILE__, __LINE__, _("\
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Invalid hardware breakpoint length %d in x86_length_and_rw_bits.\n"), len);
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}
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}
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/* Insert a watchpoint at address ADDR, which is assumed to be aligned
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according to the length of the region to watch. LEN_RW_BITS is the
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value of the bits from DR7 which describes the length and access
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type of the region to be watched by this watchpoint. Return 0 on
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success, -1 on failure. */
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static int
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x86_insert_aligned_watchpoint (struct x86_debug_reg_state *state,
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CORE_ADDR addr, unsigned len_rw_bits)
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{
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int i;
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if (!x86_dr_low_can_set_addr () || !x86_dr_low_can_set_control ())
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return -1;
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/* First, look for an occupied debug register with the same address
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and the same RW and LEN definitions. If we find one, we can
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reuse it for this watchpoint as well (and save a register). */
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ALL_DEBUG_ADDRESS_REGISTERS (i)
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{
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if (!X86_DR_VACANT (state, i)
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&& state->dr_mirror[i] == addr
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&& X86_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits)
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{
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state->dr_ref_count[i]++;
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return 0;
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}
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}
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/* Next, look for a vacant debug register. */
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ALL_DEBUG_ADDRESS_REGISTERS (i)
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{
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if (X86_DR_VACANT (state, i))
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break;
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}
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/* No more debug registers! */
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if (i >= DR_NADDR)
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return -1;
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/* Now set up the register I to watch our region. */
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/* Record the info in our local mirrored array. */
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state->dr_mirror[i] = addr;
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state->dr_ref_count[i] = 1;
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X86_DR_SET_RW_LEN (state, i, len_rw_bits);
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/* Note: we only enable the watchpoint locally, i.e. in the current
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task. Currently, no x86 target allows or supports global
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watchpoints; however, if any target would want that in the
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future, GDB should probably provide a command to control whether
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to enable watchpoints globally or locally, and the code below
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should use global or local enable and slow-down flags as
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appropriate. */
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X86_DR_LOCAL_ENABLE (state, i);
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state->dr_control_mirror |= DR_LOCAL_SLOWDOWN;
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state->dr_control_mirror &= X86_DR_CONTROL_MASK;
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return 0;
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}
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/* Remove a watchpoint at address ADDR, which is assumed to be aligned
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according to the length of the region to watch. LEN_RW_BITS is the
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value of the bits from DR7 which describes the length and access
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type of the region watched by this watchpoint. Return 0 on
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success, -1 on failure. */
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static int
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x86_remove_aligned_watchpoint (struct x86_debug_reg_state *state,
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CORE_ADDR addr, unsigned len_rw_bits)
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{
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int i, retval = -1;
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int all_vacant = 1;
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ALL_DEBUG_ADDRESS_REGISTERS (i)
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{
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if (!X86_DR_VACANT (state, i)
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&& state->dr_mirror[i] == addr
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&& X86_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits)
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{
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if (--state->dr_ref_count[i] == 0) /* No longer in use? */
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{
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/* Reset our mirror. */
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state->dr_mirror[i] = 0;
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X86_DR_DISABLE (state, i);
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/* Even though not strictly necessary, clear out all
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bits in DR_CONTROL related to this debug register.
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Debug output is clearer when we don't have stale bits
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in place. This also allows the assertion below. */
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X86_DR_SET_RW_LEN (state, i, 0);
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}
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retval = 0;
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}
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if (!X86_DR_VACANT (state, i))
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all_vacant = 0;
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}
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if (all_vacant)
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{
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/* Even though not strictly necessary, clear out all of
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DR_CONTROL, so that when we have no debug registers in use,
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we end up with DR_CONTROL == 0. The Linux support relies on
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this for an optimization. Plus, it makes for clearer debug
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output. */
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state->dr_control_mirror &= ~DR_LOCAL_SLOWDOWN;
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gdb_assert (state->dr_control_mirror == 0);
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}
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return retval;
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}
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/* Insert or remove a (possibly non-aligned) watchpoint, or count the
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number of debug registers required to watch a region at address
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ADDR whose length is LEN for accesses of type TYPE. Return 0 on
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successful insertion or removal, a positive number when queried
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about the number of registers, or -1 on failure. If WHAT is not a
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valid value, bombs through internal_error. */
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static int
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x86_handle_nonaligned_watchpoint (struct x86_debug_reg_state *state,
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x86_wp_op_t what, CORE_ADDR addr, int len,
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enum target_hw_bp_type type)
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{
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int retval = 0;
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int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4;
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static const int size_try_array[8][8] =
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{
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{1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */
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{2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */
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{2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */
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{4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */
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{4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */
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{4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */
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{4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */
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{8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */
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};
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while (len > 0)
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{
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int align = addr % max_wp_len;
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/* Four (eight on AMD64) is the maximum length a debug register
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can watch. */
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int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1);
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int size = size_try_array[try][align];
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if (what == WP_COUNT)
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{
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/* size_try_array[] is defined such that each iteration
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through the loop is guaranteed to produce an address and a
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size that can be watched with a single debug register.
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Thus, for counting the registers required to watch a
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region, we simply need to increment the count on each
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iteration. */
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retval++;
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}
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else
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{
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unsigned len_rw = x86_length_and_rw_bits (size, type);
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if (what == WP_INSERT)
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retval = x86_insert_aligned_watchpoint (state, addr, len_rw);
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else if (what == WP_REMOVE)
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retval = x86_remove_aligned_watchpoint (state, addr, len_rw);
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else
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internal_error (__FILE__, __LINE__, _("\
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Invalid value %d of operation in x86_handle_nonaligned_watchpoint.\n"),
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(int) what);
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if (retval)
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break;
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}
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addr += size;
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len -= size;
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}
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return retval;
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}
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/* Update the inferior debug registers state, in STATE, with the
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new debug registers state, in NEW_STATE. */
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static void
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x86_update_inferior_debug_regs (struct x86_debug_reg_state *state,
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struct x86_debug_reg_state *new_state)
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{
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int i;
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ALL_DEBUG_ADDRESS_REGISTERS (i)
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{
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if (X86_DR_VACANT (new_state, i) != X86_DR_VACANT (state, i))
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x86_dr_low_set_addr (new_state, i);
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else
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gdb_assert (new_state->dr_mirror[i] == state->dr_mirror[i]);
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}
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if (new_state->dr_control_mirror != state->dr_control_mirror)
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x86_dr_low_set_control (new_state);
|
|
|
|
*state = *new_state;
|
|
}
|
|
|
|
/* Insert a watchpoint to watch a memory region which starts at
|
|
address ADDR and whose length is LEN bytes. Watch memory accesses
|
|
of the type TYPE. Return 0 on success, -1 on failure. */
|
|
|
|
int
|
|
x86_dr_insert_watchpoint (struct x86_debug_reg_state *state,
|
|
enum target_hw_bp_type type,
|
|
CORE_ADDR addr, int len)
|
|
{
|
|
int retval;
|
|
/* Work on a local copy of the debug registers, and on success,
|
|
commit the change back to the inferior. */
|
|
struct x86_debug_reg_state local_state = *state;
|
|
|
|
if (type == hw_read)
|
|
return 1; /* unsupported */
|
|
|
|
if (((len != 1 && len != 2 && len != 4)
|
|
&& !(TARGET_HAS_DR_LEN_8 && len == 8))
|
|
|| addr % len != 0)
|
|
{
|
|
retval = x86_handle_nonaligned_watchpoint (&local_state,
|
|
WP_INSERT,
|
|
addr, len, type);
|
|
}
|
|
else
|
|
{
|
|
unsigned len_rw = x86_length_and_rw_bits (len, type);
|
|
|
|
retval = x86_insert_aligned_watchpoint (&local_state,
|
|
addr, len_rw);
|
|
}
|
|
|
|
if (retval == 0)
|
|
x86_update_inferior_debug_regs (state, &local_state);
|
|
|
|
if (show_debug_regs)
|
|
x86_show_dr (state, "insert_watchpoint", addr, len, type);
|
|
|
|
return retval;
|
|
}
|
|
|
|
/* Remove a watchpoint that watched the memory region which starts at
|
|
address ADDR, whose length is LEN bytes, and for accesses of the
|
|
type TYPE. Return 0 on success, -1 on failure. */
|
|
|
|
int
|
|
x86_dr_remove_watchpoint (struct x86_debug_reg_state *state,
|
|
enum target_hw_bp_type type,
|
|
CORE_ADDR addr, int len)
|
|
{
|
|
int retval;
|
|
/* Work on a local copy of the debug registers, and on success,
|
|
commit the change back to the inferior. */
|
|
struct x86_debug_reg_state local_state = *state;
|
|
|
|
if (((len != 1 && len != 2 && len != 4)
|
|
&& !(TARGET_HAS_DR_LEN_8 && len == 8))
|
|
|| addr % len != 0)
|
|
{
|
|
retval = x86_handle_nonaligned_watchpoint (&local_state,
|
|
WP_REMOVE,
|
|
addr, len, type);
|
|
}
|
|
else
|
|
{
|
|
unsigned len_rw = x86_length_and_rw_bits (len, type);
|
|
|
|
retval = x86_remove_aligned_watchpoint (&local_state,
|
|
addr, len_rw);
|
|
}
|
|
|
|
if (retval == 0)
|
|
x86_update_inferior_debug_regs (state, &local_state);
|
|
|
|
if (show_debug_regs)
|
|
x86_show_dr (state, "remove_watchpoint", addr, len, type);
|
|
|
|
return retval;
|
|
}
|
|
|
|
/* Return non-zero if we can watch a memory region that starts at
|
|
address ADDR and whose length is LEN bytes. */
|
|
|
|
int
|
|
x86_dr_region_ok_for_watchpoint (struct x86_debug_reg_state *state,
|
|
CORE_ADDR addr, int len)
|
|
{
|
|
int nregs;
|
|
|
|
/* Compute how many aligned watchpoints we would need to cover this
|
|
region. */
|
|
nregs = x86_handle_nonaligned_watchpoint (state, WP_COUNT,
|
|
addr, len, hw_write);
|
|
return nregs <= DR_NADDR ? 1 : 0;
|
|
}
|
|
|
|
/* If the inferior has some break/watchpoint that triggered, set the
|
|
address associated with that break/watchpoint and return non-zero.
|
|
Otherwise, return zero. */
|
|
|
|
int
|
|
x86_dr_stopped_data_address (struct x86_debug_reg_state *state,
|
|
CORE_ADDR *addr_p)
|
|
{
|
|
CORE_ADDR addr = 0;
|
|
int i;
|
|
int rc = 0;
|
|
/* The current thread's DR_STATUS. We always need to read this to
|
|
check whether some watchpoint caused the trap. */
|
|
unsigned status;
|
|
/* We need DR_CONTROL as well, but only iff DR_STATUS indicates a
|
|
data breakpoint trap. Only fetch it when necessary, to avoid an
|
|
unnecessary extra syscall when no watchpoint triggered. */
|
|
int control_p = 0;
|
|
unsigned control = 0;
|
|
|
|
/* In non-stop/async, threads can be running while we change the
|
|
global dr_mirror (and friends). Say, we set a watchpoint, and
|
|
let threads resume. Now, say you delete the watchpoint, or
|
|
add/remove watchpoints such that dr_mirror changes while threads
|
|
are running. On targets that support non-stop,
|
|
inserting/deleting watchpoints updates the global dr_mirror only.
|
|
It does not update the real thread's debug registers; that's only
|
|
done prior to resume. Instead, if threads are running when the
|
|
mirror changes, a temporary and transparent stop on all threads
|
|
is forced so they can get their copy of the debug registers
|
|
updated on re-resume. Now, say, a thread hit a watchpoint before
|
|
having been updated with the new dr_mirror contents, and we
|
|
haven't yet handled the corresponding SIGTRAP. If we trusted
|
|
dr_mirror below, we'd mistake the real trapped address (from the
|
|
last time we had updated debug registers in the thread) with
|
|
whatever was currently in dr_mirror. So to fix this, dr_mirror
|
|
always represents intention, what we _want_ threads to have in
|
|
debug registers. To get at the address and cause of the trap, we
|
|
need to read the state the thread still has in its debug
|
|
registers.
|
|
|
|
In sum, always get the current debug register values the current
|
|
thread has, instead of trusting the global mirror. If the thread
|
|
was running when we last changed watchpoints, the mirror no
|
|
longer represents what was set in this thread's debug
|
|
registers. */
|
|
status = x86_dr_low_get_status ();
|
|
|
|
ALL_DEBUG_ADDRESS_REGISTERS (i)
|
|
{
|
|
if (!X86_DR_WATCH_HIT (status, i))
|
|
continue;
|
|
|
|
if (!control_p)
|
|
{
|
|
control = x86_dr_low_get_control ();
|
|
control_p = 1;
|
|
}
|
|
|
|
/* This second condition makes sure DRi is set up for a data
|
|
watchpoint, not a hardware breakpoint. The reason is that
|
|
GDB doesn't call the target_stopped_data_address method
|
|
except for data watchpoints. In other words, I'm being
|
|
paranoiac. */
|
|
if (X86_DR_GET_RW_LEN (control, i) != 0)
|
|
{
|
|
addr = x86_dr_low_get_addr (i);
|
|
rc = 1;
|
|
if (show_debug_regs)
|
|
x86_show_dr (state, "watchpoint_hit", addr, -1, hw_write);
|
|
}
|
|
}
|
|
|
|
if (show_debug_regs && addr == 0)
|
|
x86_show_dr (state, "stopped_data_addr", 0, 0, hw_write);
|
|
|
|
if (rc)
|
|
*addr_p = addr;
|
|
return rc;
|
|
}
|
|
|
|
/* Return non-zero if the inferior has some watchpoint that triggered.
|
|
Otherwise return zero. */
|
|
|
|
int
|
|
x86_dr_stopped_by_watchpoint (struct x86_debug_reg_state *state)
|
|
{
|
|
CORE_ADDR addr = 0;
|
|
return x86_dr_stopped_data_address (state, &addr);
|
|
}
|