184 lines
5.8 KiB
C
184 lines
5.8 KiB
C
/* Definitions for opcode table for the sparc.
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Copyright 1989, 1991, 1992 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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the GNU Binutils.
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GAS/GDB is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS/GDB is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS or GDB; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* The SPARC opcode table (and other related data) is defined in
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the opcodes library in sparc-opc.c. If you change anything here, make
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sure you fix up that file, and vice versa. */
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/* FIXME-someday: perhaps the ,a's and such should be embedded in the
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instruction's name rather than the args. This would make gas faster, pinsn
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slower, but would mess up some macros a bit. xoxorich. */
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#define sparc_architecture bfd_sparc_architecture
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#define architecture_pname bfd_sparc_architecture_pname
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#define sparc_opcode bfd_sparc_opcode
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#define sparc_opcodes bfd_sparc_opcodes
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/*
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* Structure of an opcode table entry.
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* This enumerator must parallel the architecture_pname array
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* in bfd/opc-sparc.c.
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*/
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enum sparc_architecture {
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v6 = 0,
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v7,
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v8,
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sparclite,
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v9
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};
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extern const char *architecture_pname[];
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/* Sparclite and v9 are both supersets of v8; we can't bump between them. */
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#define ARCHITECTURES_CONFLICT_P(ARCH1, ARCH2) ((ARCH1) == sparclite && (ARCH2) == v9)
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struct sparc_opcode {
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const char *name;
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unsigned long match; /* Bits that must be set. */
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unsigned long lose; /* Bits that must not be set. */
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const char *args;
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/* This was called "delayed" in versions before the flags. */
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char flags;
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enum sparc_architecture architecture;
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};
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#define F_DELAYED 1 /* Delayed branch */
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#define F_ALIAS 2 /* Alias for a "real" instruction */
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#define F_UNBR 4 /* Unconditional branch */
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#define F_CONDBR 8 /* Conditional branch */
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#define F_JSR 16 /* Subroutine call */
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/* FIXME: Add F_ANACHRONISTIC flag for v9. */
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/* FIXME: Add F_OBSOLETE flag for v9, for instructions that no longer exist? */
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/*
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All sparc opcodes are 32 bits, except for the `set' instruction (really a
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macro), which is 64 bits. It is handled as a special case.
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The match component is a mask saying which bits must match a particular
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opcode in order for an instruction to be an instance of that opcode.
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The args component is a string containing one character for each operand of the
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instruction.
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Kinds of operands:
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# Number used by optimizer. It is ignored.
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1 rs1 register.
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2 rs2 register.
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d rd register.
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e frs1 floating point register.
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v frs1 floating point register (double/even).
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V frs1 floating point register (quad/multiple of 4).
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f frs2 floating point register.
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B frs2 floating point register (double/even).
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R frs2 floating point register (quad/multiple of 4).
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g frsd floating point register.
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H frsd floating point register (double/even).
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J frsd floating point register (quad/multiple of 4).
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b crs1 coprocessor register
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c crs2 coprocessor register
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D crsd coprocessor register
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m alternate space register (asr) in rd
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M alternate space register (asr) in rs1
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h 22 high bits.
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K MEMBAR mask (7 bits). (v9)
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j 10 bit Immediate. (v9)
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I 11 bit Immediate. (v9)
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i 13 bit Immediate.
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n 22 bit immediate.
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k 2+14 bit PC relative immediate. (v9)
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G 19 bit PC relative immediate. (v9)
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l 22 bit PC relative immediate.
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L 30 bit PC relative immediate.
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a Annul. The annul bit is set.
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A Alternate address space. Stored as 8 bits.
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C Coprocessor state register.
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F floating point state register.
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p Processor state register.
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N Branch predict clear ",pn" (v9)
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T Branch predict set ",pt" (v9)
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z %icc. (v9)
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Z %xcc. (v9)
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q Floating point queue.
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r Single register that is both rs1 and rsd.
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Q Coprocessor queue.
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S Special case.
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t Trap base register.
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w Window invalid mask register.
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y Y register.
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E %ccr. (v9)
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s %fprs. (v9)
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P %pc. (v9)
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W %tick. (v9)
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o %asi. (v9)
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6 %fcc0. (v9)
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7 %fcc1. (v9)
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8 %fcc2. (v9)
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9 %fcc3. (v9)
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! Privileged Register in rd (v9)
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? Privileged Register in rs1 (v9)
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* Prefetch function constant. (v9)
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x OPF field (v9 impdep).
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The following chars are unused: (note: ,[] are used as punctuation)
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[uxOUXY3450]
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*/
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#define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */
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#define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */
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#define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */
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#define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */
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#define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */
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#define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */
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#define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */
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#define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */
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#define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */
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#define F1(x) (OP(x))
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#define DISP30(x) ((x)&0x3fffffff)
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#define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */
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#define RS2(x) ((x)&0x1f) /* rs2 field */
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#define SIMM13(x) ((x)&0x1fff) /* simm13 field */
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#define RD(x) (((x)&0x1f) << 25) /* destination register field */
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#define RS1(x) (((x)&0x1f) << 14) /* rs1 field */
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#define ASI_RS2(x) (SIMM13(x))
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#define ANNUL (1<<29)
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#define BPRED (1<<19) /* v9 */
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#define IMMED F3I(1)
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#define RD_G0 RD(~0)
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#define RS1_G0 RS1(~0)
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#define RS2_G0 RS2(~0)
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extern struct sparc_opcode sparc_opcodes[];
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extern const int bfd_sparc_num_opcodes;
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#define NUMOPCODES bfd_sparc_num_opcodes
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/*
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* Local Variables:
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* fill-column: 131
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* comment-column: 0
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* End:
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*/
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/* end of sparc.h */
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