846 lines
25 KiB
C
846 lines
25 KiB
C
/* Assembler interface for targets using CGEN. -*- C -*-
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CGEN: Cpu tools GENerator
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THIS FILE IS USED TO GENERATE m32r-asm.c.
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "sysdep.h"
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#include <ctype.h>
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#include <stdio.h>
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#include "ansidecl.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "m32r-opc.h"
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#include "opintl.h"
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/* ??? The layout of this stuff is still work in progress.
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For speed in assembly/disassembly, we use inline functions. That of course
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will only work for GCC. When this stuff is finished, we can decide whether
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to keep the inline functions (and only get the performance increase when
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compiled with GCC), or switch to macros, or use something else.
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*/
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static const char * insert_normal
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PARAMS ((long, unsigned int, int, int, int, char *));
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static const char * parse_insn_normal
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PARAMS ((const CGEN_INSN *, const char **, CGEN_FIELDS *));
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static const char * insert_insn_normal
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PARAMS ((const CGEN_INSN *, CGEN_FIELDS *, cgen_insn_t *, bfd_vma));
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/* -- assembler routines inserted here */
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/* -- asm.c */
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/* Handle '#' prefixes (i.e. skip over them). */
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static const char *
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parse_hash (strp, opindex, valuep)
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const char **strp;
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int opindex;
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unsigned long *valuep;
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{
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if (**strp == '#')
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++*strp;
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return NULL;
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}
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/* Handle shigh(), high(). */
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static const char *
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parse_hi16 (strp, opindex, valuep)
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const char **strp;
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int opindex;
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unsigned long *valuep;
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{
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const char *errmsg;
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enum cgen_parse_operand_result result_type;
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if (**strp == '#')
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++*strp;
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if (strncasecmp (*strp, "high(", 5) == 0)
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{
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*strp += 5;
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errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_ULO,
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&result_type, valuep);
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if (**strp != ')')
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return "missing `)'";
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++*strp;
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if (errmsg == NULL
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&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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*valuep >>= 16;
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return errmsg;
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}
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else if (strncasecmp (*strp, "shigh(", 6) == 0)
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{
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*strp += 6;
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errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_SLO,
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&result_type, valuep);
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if (**strp != ')')
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return "missing `)'";
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++*strp;
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if (errmsg == NULL
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&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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*valuep = (*valuep >> 16) + ((*valuep) & 0x8000 ? 1 : 0);
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return errmsg;
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}
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return cgen_parse_unsigned_integer (strp, opindex, valuep);
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}
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/* Handle low() in a signed context. Also handle sda().
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The signedness of the value doesn't matter to low(), but this also
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handles the case where low() isn't present. */
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static const char *
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parse_slo16 (strp, opindex, valuep)
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const char **strp;
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int opindex;
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long *valuep;
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{
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const char *errmsg;
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enum cgen_parse_operand_result result_type;
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if (**strp == '#')
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++*strp;
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if (strncasecmp (*strp, "low(", 4) == 0)
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{
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*strp += 4;
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errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16,
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&result_type, valuep);
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if (**strp != ')')
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return "missing `)'";
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++*strp;
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if (errmsg == NULL
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&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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*valuep &= 0xffff;
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return errmsg;
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}
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if (strncasecmp (*strp, "sda(", 4) == 0)
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{
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*strp += 4;
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errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_SDA16, NULL, valuep);
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if (**strp != ')')
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return "missing `)'";
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++*strp;
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return errmsg;
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}
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return cgen_parse_signed_integer (strp, opindex, valuep);
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}
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/* Handle low() in an unsigned context.
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The signedness of the value doesn't matter to low(), but this also
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handles the case where low() isn't present. */
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static const char *
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parse_ulo16 (strp, opindex, valuep)
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const char **strp;
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int opindex;
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unsigned long *valuep;
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{
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const char *errmsg;
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enum cgen_parse_operand_result result_type;
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if (**strp == '#')
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++*strp;
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if (strncasecmp (*strp, "low(", 4) == 0)
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{
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*strp += 4;
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errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16,
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&result_type, valuep);
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if (**strp != ')')
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return "missing `)'";
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++*strp;
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if (errmsg == NULL
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&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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*valuep &= 0xffff;
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return errmsg;
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}
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return cgen_parse_unsigned_integer (strp, opindex, valuep);
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}
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/* -- */
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/* Main entry point for operand parsing.
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This function is basically just a big switch statement. Earlier versions
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used tables to look up the function to use, but
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- if the table contains both assembler and disassembler functions then
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the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
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- using a switch statement avoids the function call overhead.
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This function could be moved into `parse_insn_normal', but keeping it
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separate makes clear the interface between `parse_insn_normal' and each of
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the handlers.
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*/
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const char *
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m32r_cgen_parse_operand (opindex, strp, fields)
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int opindex;
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const char ** strp;
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CGEN_FIELDS * fields;
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{
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const char * errmsg;
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switch (opindex)
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{
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case M32R_OPERAND_SR :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, & fields->f_r2);
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break;
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case M32R_OPERAND_DR :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, & fields->f_r1);
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break;
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case M32R_OPERAND_SRC1 :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, & fields->f_r1);
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break;
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case M32R_OPERAND_SRC2 :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, & fields->f_r2);
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break;
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case M32R_OPERAND_SCR :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, & fields->f_r2);
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break;
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case M32R_OPERAND_DCR :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, & fields->f_r1);
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break;
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case M32R_OPERAND_SIMM8 :
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errmsg = cgen_parse_signed_integer (strp, M32R_OPERAND_SIMM8, &fields->f_simm8);
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break;
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case M32R_OPERAND_SIMM16 :
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errmsg = cgen_parse_signed_integer (strp, M32R_OPERAND_SIMM16, &fields->f_simm16);
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break;
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case M32R_OPERAND_UIMM4 :
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errmsg = cgen_parse_unsigned_integer (strp, M32R_OPERAND_UIMM4, &fields->f_uimm4);
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break;
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case M32R_OPERAND_UIMM5 :
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errmsg = cgen_parse_unsigned_integer (strp, M32R_OPERAND_UIMM5, &fields->f_uimm5);
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break;
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case M32R_OPERAND_UIMM16 :
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errmsg = cgen_parse_unsigned_integer (strp, M32R_OPERAND_UIMM16, &fields->f_uimm16);
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break;
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/* start-sanitize-m32rx */
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case M32R_OPERAND_IMM1 :
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errmsg = cgen_parse_unsigned_integer (strp, M32R_OPERAND_IMM1, &fields->f_imm1);
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break;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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case M32R_OPERAND_ACCD :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_accums, & fields->f_accd);
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break;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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case M32R_OPERAND_ACCS :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_accums, & fields->f_accs);
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break;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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case M32R_OPERAND_ACC :
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errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_accums, & fields->f_acc);
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break;
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/* end-sanitize-m32rx */
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case M32R_OPERAND_HASH :
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errmsg = parse_hash (strp, M32R_OPERAND_HASH, &fields->f_nil);
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break;
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case M32R_OPERAND_HI16 :
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errmsg = parse_hi16 (strp, M32R_OPERAND_HI16, &fields->f_hi16);
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break;
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case M32R_OPERAND_SLO16 :
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errmsg = parse_slo16 (strp, M32R_OPERAND_SLO16, &fields->f_simm16);
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break;
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case M32R_OPERAND_ULO16 :
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errmsg = parse_ulo16 (strp, M32R_OPERAND_ULO16, &fields->f_uimm16);
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break;
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case M32R_OPERAND_UIMM24 :
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errmsg = cgen_parse_address (strp, M32R_OPERAND_UIMM24, 0, NULL, & fields->f_uimm24);
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break;
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case M32R_OPERAND_DISP8 :
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errmsg = cgen_parse_address (strp, M32R_OPERAND_DISP8, 0, NULL, & fields->f_disp8);
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break;
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case M32R_OPERAND_DISP16 :
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errmsg = cgen_parse_address (strp, M32R_OPERAND_DISP16, 0, NULL, & fields->f_disp16);
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break;
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case M32R_OPERAND_DISP24 :
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errmsg = cgen_parse_address (strp, M32R_OPERAND_DISP24, 0, NULL, & fields->f_disp24);
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break;
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default :
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/* xgettext:c-format */
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fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex);
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abort ();
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}
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return errmsg;
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}
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/* Main entry point for operand insertion.
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This function is basically just a big switch statement. Earlier versions
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used tables to look up the function to use, but
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- if the table contains both assembler and disassembler functions then
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the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
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- using a switch statement avoids the function call overhead.
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This function could be moved into `parse_insn_normal', but keeping it
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separate makes clear the interface between `parse_insn_normal' and each of
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the handlers. It's also needed by GAS to insert operands that couldn't be
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resolved during parsing.
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*/
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const char *
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m32r_cgen_insert_operand (opindex, fields, buffer, pc)
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int opindex;
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CGEN_FIELDS * fields;
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char * buffer;
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bfd_vma pc;
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{
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const char * errmsg;
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switch (opindex)
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{
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case M32R_OPERAND_SR :
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errmsg = insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_DR :
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errmsg = insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SRC1 :
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errmsg = insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SRC2 :
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errmsg = insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SCR :
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errmsg = insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_DCR :
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errmsg = insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SIMM8 :
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errmsg = insert_normal (fields->f_simm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 8, 8, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SIMM16 :
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errmsg = insert_normal (fields->f_simm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_UIMM4 :
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errmsg = insert_normal (fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_UIMM5 :
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errmsg = insert_normal (fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_UIMM16 :
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errmsg = insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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/* start-sanitize-m32rx */
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case M32R_OPERAND_IMM1 :
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{
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long value = fields->f_imm1;
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value = ((value) - (1));
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errmsg = insert_normal (value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 15, 1, CGEN_FIELDS_BITSIZE (fields), buffer);
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}
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break;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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case M32R_OPERAND_ACCD :
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errmsg = insert_normal (fields->f_accd, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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case M32R_OPERAND_ACCS :
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errmsg = insert_normal (fields->f_accs, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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case M32R_OPERAND_ACC :
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errmsg = insert_normal (fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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/* end-sanitize-m32rx */
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case M32R_OPERAND_HASH :
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errmsg = insert_normal (fields->f_nil, 0, 0, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_HI16 :
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errmsg = insert_normal (fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_SLO16 :
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errmsg = insert_normal (fields->f_simm16, 0, 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_ULO16 :
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errmsg = insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_UIMM24 :
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errmsg = insert_normal (fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, CGEN_FIELDS_BITSIZE (fields), buffer);
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break;
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case M32R_OPERAND_DISP8 :
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{
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long value = fields->f_disp8;
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value = ((int) (((value) - (((pc) & (-4))))) >> (2));
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errmsg = insert_normal (value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, CGEN_FIELDS_BITSIZE (fields), buffer);
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}
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break;
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case M32R_OPERAND_DISP16 :
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{
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long value = fields->f_disp16;
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value = ((int) (((value) - (pc))) >> (2));
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errmsg = insert_normal (value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
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}
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break;
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case M32R_OPERAND_DISP24 :
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{
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long value = fields->f_disp24;
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value = ((int) (((value) - (pc))) >> (2));
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errmsg = insert_normal (value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, CGEN_FIELDS_BITSIZE (fields), buffer);
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}
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break;
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default :
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/* xgettext:c-format */
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fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
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opindex);
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abort ();
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}
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return errmsg;
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}
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||
|
||
cgen_parse_fn * m32r_cgen_parse_handlers[] =
|
||
{
|
||
0, /* default */
|
||
parse_insn_normal,
|
||
};
|
||
|
||
cgen_insert_fn * m32r_cgen_insert_handlers[] =
|
||
{
|
||
0, /* default */
|
||
insert_insn_normal,
|
||
};
|
||
|
||
void
|
||
m32r_cgen_init_asm (mach, endian)
|
||
int mach;
|
||
enum cgen_endian endian;
|
||
{
|
||
m32r_cgen_init_tables (mach);
|
||
cgen_set_cpu (& m32r_cgen_opcode_table, mach, endian);
|
||
cgen_asm_init ();
|
||
}
|
||
|
||
|
||
/* Default insertion routine.
|
||
|
||
ATTRS is a mask of the boolean attributes.
|
||
LENGTH is the length of VALUE in bits.
|
||
TOTAL_LENGTH is the total length of the insn (currently 8,16,32).
|
||
|
||
The result is an error message or NULL if success. */
|
||
|
||
/* ??? This duplicates functionality with bfd's howto table and
|
||
bfd_install_relocation. */
|
||
/* ??? For architectures where insns can be representable as ints,
|
||
store insn in `field' struct and add registers, etc. while parsing? */
|
||
|
||
static const char *
|
||
insert_normal (value, attrs, start, length, total_length, buffer)
|
||
long value;
|
||
unsigned int attrs;
|
||
int start;
|
||
int length;
|
||
int total_length;
|
||
char * buffer;
|
||
{
|
||
bfd_vma x;
|
||
static char buf[100];
|
||
/* Written this way to avoid undefined behaviour.
|
||
Yes, `long' will be bfd_vma but not yet. */
|
||
long mask = (((1L << (length - 1)) - 1) << 1) | 1;
|
||
|
||
/* If LENGTH is zero, this operand doesn't contribute to the value. */
|
||
if (length == 0)
|
||
return NULL;
|
||
|
||
/* Ensure VALUE will fit. */
|
||
if ((attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED)) != 0)
|
||
{
|
||
unsigned long max = mask;
|
||
if ((unsigned long) value > max)
|
||
{
|
||
/* xgettext:c-format */
|
||
sprintf (buf, _("operand out of range (%lu not between 0 and %lu)"),
|
||
value, max);
|
||
return buf;
|
||
}
|
||
}
|
||
else
|
||
{
|
||
long min = - (1L << (length - 1));
|
||
long max = (1L << (length - 1)) - 1;
|
||
if (value < min || value > max)
|
||
{
|
||
sprintf
|
||
/* xgettext:c-format */
|
||
(buf, _("operand out of range (%ld not between %ld and %ld)"),
|
||
value, min, max);
|
||
return buf;
|
||
}
|
||
}
|
||
|
||
#if 0 /*def CGEN_INT_INSN*/
|
||
*buffer |= (value & mask) << (total_length - (start + length));
|
||
#else
|
||
switch (total_length)
|
||
{
|
||
case 8:
|
||
x = * (unsigned char *) buffer;
|
||
break;
|
||
case 16:
|
||
if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
|
||
x = bfd_getb16 (buffer);
|
||
else
|
||
x = bfd_getl16 (buffer);
|
||
break;
|
||
case 32:
|
||
if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
|
||
x = bfd_getb32 (buffer);
|
||
else
|
||
x = bfd_getl32 (buffer);
|
||
break;
|
||
default :
|
||
abort ();
|
||
}
|
||
|
||
x |= (value & mask) << (total_length - (start + length));
|
||
|
||
switch (total_length)
|
||
{
|
||
case 8:
|
||
* buffer = value;
|
||
break;
|
||
case 16:
|
||
if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
|
||
bfd_putb16 (x, buffer);
|
||
else
|
||
bfd_putl16 (x, buffer);
|
||
break;
|
||
case 32:
|
||
if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
|
||
bfd_putb32 (x, buffer);
|
||
else
|
||
bfd_putl32 (x, buffer);
|
||
break;
|
||
default :
|
||
abort ();
|
||
}
|
||
#endif
|
||
|
||
return NULL;
|
||
}
|
||
|
||
/* Default insn parser.
|
||
|
||
The syntax string is scanned and operands are parsed and stored in FIELDS.
|
||
Relocs are queued as we go via other callbacks.
|
||
|
||
??? Note that this is currently an all-or-nothing parser. If we fail to
|
||
parse the instruction, we return 0 and the caller will start over from
|
||
the beginning. Backtracking will be necessary in parsing subexpressions,
|
||
but that can be handled there. Not handling backtracking here may get
|
||
expensive in the case of the m68k. Deal with later.
|
||
|
||
Returns NULL for success, an error message for failure.
|
||
*/
|
||
|
||
static const char *
|
||
parse_insn_normal (insn, strp, fields)
|
||
const CGEN_INSN * insn;
|
||
const char ** strp;
|
||
CGEN_FIELDS * fields;
|
||
{
|
||
const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn);
|
||
const char * str = *strp;
|
||
const char * errmsg;
|
||
const char * p;
|
||
const unsigned char * syn;
|
||
#ifdef CGEN_MNEMONIC_OPERANDS
|
||
/* FIXME: wip */
|
||
int past_opcode_p;
|
||
#endif
|
||
|
||
/* For now we assume the mnemonic is first (there are no leading operands).
|
||
We can parse it without needing to set up operand parsing. */
|
||
p = CGEN_INSN_MNEMONIC (insn);
|
||
while (* p && * p == * str)
|
||
++ p, ++ str;
|
||
|
||
if (* p || (* str && !isspace (* str)))
|
||
return _("unrecognized instruction");
|
||
|
||
CGEN_INIT_PARSE ();
|
||
cgen_init_parse_operand ();
|
||
#ifdef CGEN_MNEMONIC_OPERANDS
|
||
past_opcode_p = 0;
|
||
#endif
|
||
|
||
/* We don't check for (*str != '\0') here because we want to parse
|
||
any trailing fake arguments in the syntax string. */
|
||
syn = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
|
||
|
||
/* Mnemonics come first for now, ensure valid string. */
|
||
if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
|
||
abort ();
|
||
|
||
++syn;
|
||
|
||
while (* syn != 0)
|
||
{
|
||
/* Non operand chars must match exactly. */
|
||
if (CGEN_SYNTAX_CHAR_P (* syn))
|
||
{
|
||
if (*str == CGEN_SYNTAX_CHAR (* syn))
|
||
{
|
||
#ifdef CGEN_MNEMONIC_OPERANDS
|
||
if (* syn == ' ')
|
||
past_opcode_p = 1;
|
||
#endif
|
||
++ syn;
|
||
++ str;
|
||
}
|
||
else
|
||
{
|
||
/* Syntax char didn't match. Can't be this insn. */
|
||
/* FIXME: would like to return something like
|
||
"expected char `c'" */
|
||
return _("syntax error");
|
||
}
|
||
continue;
|
||
}
|
||
|
||
/* We have an operand of some sort. */
|
||
errmsg = m32r_cgen_parse_operand (CGEN_SYNTAX_FIELD (*syn),
|
||
&str, fields);
|
||
if (errmsg)
|
||
return errmsg;
|
||
|
||
/* Done with this operand, continue with next one. */
|
||
++ syn;
|
||
}
|
||
|
||
/* If we're at the end of the syntax string, we're done. */
|
||
if (* syn == '\0')
|
||
{
|
||
/* FIXME: For the moment we assume a valid `str' can only contain
|
||
blanks now. IE: We needn't try again with a longer version of
|
||
the insn and it is assumed that longer versions of insns appear
|
||
before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
|
||
while (isspace (* str))
|
||
++ str;
|
||
|
||
if (* str != '\0')
|
||
return _("junk at end of line"); /* FIXME: would like to include `str' */
|
||
|
||
return NULL;
|
||
}
|
||
|
||
/* We couldn't parse it. */
|
||
return "unrecognized instruction";
|
||
}
|
||
|
||
/* Default insn builder (insert handler).
|
||
The instruction is recorded in target byte order.
|
||
The result is an error message or NULL if success. */
|
||
/* FIXME: change buffer to char *? */
|
||
|
||
static const char *
|
||
insert_insn_normal (insn, fields, buffer, pc)
|
||
const CGEN_INSN * insn;
|
||
CGEN_FIELDS * fields;
|
||
cgen_insn_t * buffer;
|
||
bfd_vma pc;
|
||
{
|
||
const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn);
|
||
bfd_vma value;
|
||
const unsigned char * syn;
|
||
|
||
CGEN_INIT_INSERT ();
|
||
value = CGEN_INSN_VALUE (insn);
|
||
|
||
/* If we're recording insns as numbers (rather than a string of bytes),
|
||
target byte order handling is deferred until later. */
|
||
#undef min
|
||
#define min(a,b) ((a) < (b) ? (a) : (b))
|
||
#if 0 /*def CGEN_INT_INSN*/
|
||
*buffer = value;
|
||
#else
|
||
switch (min (CGEN_BASE_INSN_BITSIZE, CGEN_FIELDS_BITSIZE (fields)))
|
||
{
|
||
case 8:
|
||
* buffer = value;
|
||
break;
|
||
case 16:
|
||
if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
|
||
bfd_putb16 (value, (char *) buffer);
|
||
else
|
||
bfd_putl16 (value, (char *) buffer);
|
||
break;
|
||
case 32:
|
||
if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
|
||
bfd_putb32 (value, (char *) buffer);
|
||
else
|
||
bfd_putl32 (value, (char *) buffer);
|
||
break;
|
||
default:
|
||
abort ();
|
||
}
|
||
#endif
|
||
|
||
/* ??? Rather than scanning the syntax string again, we could store
|
||
in `fields' a null terminated list of the fields that are present. */
|
||
|
||
for (syn = CGEN_SYNTAX_STRING (syntax); * syn != '\0'; ++ syn)
|
||
{
|
||
const char *errmsg;
|
||
|
||
if (CGEN_SYNTAX_CHAR_P (* syn))
|
||
continue;
|
||
|
||
errmsg = m32r_cgen_insert_operand (CGEN_SYNTAX_FIELD (*syn), fields,
|
||
(char *) buffer, pc);
|
||
if (errmsg)
|
||
return errmsg;
|
||
}
|
||
|
||
return NULL;
|
||
}
|
||
|
||
/* Main entry point.
|
||
This routine is called for each instruction to be assembled.
|
||
STR points to the insn to be assembled.
|
||
We assume all necessary tables have been initialized.
|
||
The assembled instruction, less any fixups, is stored in buf.
|
||
[??? What byte order?]
|
||
The result is a pointer to the insn's entry in the opcode table,
|
||
or NULL if an error occured (an error message will have already been
|
||
printed).
|
||
|
||
Note that when processing (non-alias) macro-insns,
|
||
this function recurses. */
|
||
|
||
const CGEN_INSN *
|
||
m32r_cgen_assemble_insn (str, fields, buf, errmsg)
|
||
const char * str;
|
||
CGEN_FIELDS * fields;
|
||
cgen_insn_t * buf;
|
||
char ** errmsg;
|
||
{
|
||
const char * start;
|
||
CGEN_INSN_LIST * ilist;
|
||
|
||
/* Skip leading white space. */
|
||
while (isspace (* str))
|
||
++ str;
|
||
|
||
/* The instructions are stored in hashed lists.
|
||
Get the first in the list. */
|
||
ilist = CGEN_ASM_LOOKUP_INSN (str);
|
||
|
||
/* Keep looking until we find a match. */
|
||
|
||
start = str;
|
||
for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
|
||
{
|
||
const CGEN_INSN *insn = ilist->insn;
|
||
|
||
#if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */
|
||
/* Is this insn supported by the selected cpu? */
|
||
if (! m32r_cgen_insn_supported (insn))
|
||
continue;
|
||
#endif
|
||
|
||
/* If the RELAX attribute is set, this is an insn that shouldn't be
|
||
chosen immediately. Instead, it is used during assembler/linker
|
||
relaxation if possible. */
|
||
if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX) != 0)
|
||
continue;
|
||
|
||
str = start;
|
||
|
||
/* Record a default length for the insn. This will get set to the
|
||
correct value while parsing. */
|
||
/* FIXME: wip */
|
||
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
|
||
|
||
if (! CGEN_PARSE_FN (insn) (insn, & str, fields))
|
||
{
|
||
/* ??? 0 is passed for `pc' */
|
||
if (CGEN_INSERT_FN (insn) (insn, fields, buf, (bfd_vma) 0) != NULL)
|
||
continue;
|
||
/* It is up to the caller to actually output the insn and any
|
||
queued relocs. */
|
||
return insn;
|
||
}
|
||
|
||
/* Try the next entry. */
|
||
}
|
||
|
||
/* FIXME: We can return a better error message than this.
|
||
Need to track why it failed and pick the right one. */
|
||
{
|
||
static char errbuf[100];
|
||
if (strlen (start) > 50)
|
||
/* xgettext:c-format */
|
||
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
|
||
else
|
||
/* xgettext:c-format */
|
||
sprintf (errbuf, _("bad instruction `%.50s'"), start);
|
||
|
||
*errmsg = errbuf;
|
||
return NULL;
|
||
}
|
||
}
|
||
|
||
#if 0 /* This calls back to GAS which we can't do without care. */
|
||
|
||
/* Record each member of OPVALS in the assembler's symbol table.
|
||
This lets GAS parse registers for us.
|
||
??? Interesting idea but not currently used. */
|
||
|
||
/* Record each member of OPVALS in the assembler's symbol table.
|
||
FIXME: Not currently used. */
|
||
|
||
void
|
||
m32r_cgen_asm_hash_keywords (opvals)
|
||
CGEN_KEYWORD * opvals;
|
||
{
|
||
CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
|
||
const CGEN_KEYWORD_ENTRY * ke;
|
||
|
||
while ((ke = cgen_keyword_search_next (& search)) != NULL)
|
||
{
|
||
#if 0 /* Unnecessary, should be done in the search routine. */
|
||
if (! m32r_cgen_opval_supported (ke))
|
||
continue;
|
||
#endif
|
||
cgen_asm_record_register (ke->name, ke->value);
|
||
}
|
||
}
|
||
|
||
#endif /* 0 */
|