626d0adf84
* mips.h: Fix missing space in comment.
(INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, INSN_ISA5)
(INSN_ISA32, INSN_ISA32R2, INSN_ISA64): Shift values right
by four bits.
890 lines
28 KiB
C
890 lines
28 KiB
C
/* mips.h. Mips opcode list for GDB, the GNU debugger.
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Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
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Free Software Foundation, Inc.
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Contributed by Ralph Campbell and OSF
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Commented and modified by Ian Lance Taylor, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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1, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef _MIPS_H_
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#define _MIPS_H_
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/* These are bit masks and shift counts to use to access the various
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fields of an instruction. To retrieve the X field of an
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instruction, use the expression
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(i >> OP_SH_X) & OP_MASK_X
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To set the same field (to j), use
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i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
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Make sure you use fields that are appropriate for the instruction,
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of course.
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The 'i' format uses OP, RS, RT and IMMEDIATE.
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The 'j' format uses OP and TARGET.
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The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
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The 'b' format uses OP, RS, RT and DELTA.
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The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
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The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
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A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
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breakpoint instruction are not defined; Kane says the breakpoint
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code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
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only use ten bits). An optional two-operand form of break/sdbbp
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allows the lower ten bits to be set too, and MIPS32 and later
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architectures allow 20 bits to be set with a signal operand
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(using CODE20).
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The syscall instruction uses CODE20.
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The general coprocessor instructions use COPZ. */
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#define OP_MASK_OP 0x3f
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#define OP_SH_OP 26
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#define OP_MASK_RS 0x1f
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#define OP_SH_RS 21
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#define OP_MASK_FR 0x1f
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#define OP_SH_FR 21
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#define OP_MASK_FMT 0x1f
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#define OP_SH_FMT 21
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#define OP_MASK_BCC 0x7
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#define OP_SH_BCC 18
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#define OP_MASK_CODE 0x3ff
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#define OP_SH_CODE 16
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#define OP_MASK_CODE2 0x3ff
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#define OP_SH_CODE2 6
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#define OP_MASK_RT 0x1f
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#define OP_SH_RT 16
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#define OP_MASK_FT 0x1f
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#define OP_SH_FT 16
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#define OP_MASK_CACHE 0x1f
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#define OP_SH_CACHE 16
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#define OP_MASK_RD 0x1f
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#define OP_SH_RD 11
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#define OP_MASK_FS 0x1f
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#define OP_SH_FS 11
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#define OP_MASK_PREFX 0x1f
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#define OP_SH_PREFX 11
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#define OP_MASK_CCC 0x7
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#define OP_SH_CCC 8
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#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
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#define OP_SH_CODE20 6
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#define OP_MASK_SHAMT 0x1f
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#define OP_SH_SHAMT 6
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#define OP_MASK_FD 0x1f
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#define OP_SH_FD 6
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#define OP_MASK_TARGET 0x3ffffff
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#define OP_SH_TARGET 0
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#define OP_MASK_COPZ 0x1ffffff
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#define OP_SH_COPZ 0
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#define OP_MASK_IMMEDIATE 0xffff
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#define OP_SH_IMMEDIATE 0
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#define OP_MASK_DELTA 0xffff
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#define OP_SH_DELTA 0
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#define OP_MASK_FUNCT 0x3f
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#define OP_SH_FUNCT 0
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#define OP_MASK_SPEC 0x3f
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#define OP_SH_SPEC 0
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#define OP_SH_LOCC 8 /* FP condition code. */
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#define OP_SH_HICC 18 /* FP condition code. */
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#define OP_MASK_CC 0x7
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#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
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#define OP_MASK_COP1NORM 0x1 /* a single bit. */
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#define OP_SH_COP1SPEC 21 /* COP1 encodings. */
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#define OP_MASK_COP1SPEC 0xf
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#define OP_MASK_COP1SCLR 0x4
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#define OP_MASK_COP1CMP 0x3
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#define OP_SH_COP1CMP 4
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#define OP_SH_FORMAT 21 /* FP short format field. */
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#define OP_MASK_FORMAT 0x7
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#define OP_SH_TRUE 16
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#define OP_MASK_TRUE 0x1
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#define OP_SH_GE 17
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#define OP_MASK_GE 0x01
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#define OP_SH_UNSIGNED 16
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#define OP_MASK_UNSIGNED 0x1
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#define OP_SH_HINT 16
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#define OP_MASK_HINT 0x1f
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#define OP_SH_MMI 0 /* Multimedia (parallel) op. */
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#define OP_MASK_MMI 0x3f
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#define OP_SH_MMISUB 6
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#define OP_MASK_MMISUB 0x1f
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#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
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#define OP_SH_PERFREG 1
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#define OP_SH_SEL 0 /* Coprocessor select field. */
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#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
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#define OP_SH_CODE19 6 /* 19 bit wait code. */
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#define OP_MASK_CODE19 0x7ffff
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#define OP_SH_ALN 21
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#define OP_MASK_ALN 0x7
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#define OP_SH_VSEL 21
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#define OP_MASK_VSEL 0x1f
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#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
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but 0x8-0xf don't select bytes. */
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#define OP_SH_VECBYTE 22
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#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
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#define OP_SH_VECALIGN 21
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#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
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#define OP_SH_INSMSB 11
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#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
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#define OP_SH_EXTMSBD 11
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#define OP_OP_COP0 0x10
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#define OP_OP_COP1 0x11
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#define OP_OP_COP2 0x12
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#define OP_OP_COP3 0x13
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#define OP_OP_LWC1 0x31
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#define OP_OP_LWC2 0x32
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#define OP_OP_LWC3 0x33 /* a.k.a. pref */
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#define OP_OP_LDC1 0x35
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#define OP_OP_LDC2 0x36
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#define OP_OP_LDC3 0x37 /* a.k.a. ld */
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#define OP_OP_SWC1 0x39
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#define OP_OP_SWC2 0x3a
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#define OP_OP_SWC3 0x3b
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#define OP_OP_SDC1 0x3d
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#define OP_OP_SDC2 0x3e
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#define OP_OP_SDC3 0x3f /* a.k.a. sd */
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/* Values in the 'VSEL' field. */
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#define MDMX_FMTSEL_IMM_QH 0x1d
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#define MDMX_FMTSEL_IMM_OB 0x1e
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#define MDMX_FMTSEL_VEC_QH 0x15
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#define MDMX_FMTSEL_VEC_OB 0x16
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/* This structure holds information for a particular instruction. */
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struct mips_opcode
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{
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/* The name of the instruction. */
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const char *name;
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/* A string describing the arguments for this instruction. */
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const char *args;
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/* The basic opcode for the instruction. When assembling, this
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opcode is modified by the arguments to produce the actual opcode
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that is used. If pinfo is INSN_MACRO, then this is 0. */
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unsigned long match;
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/* If pinfo is not INSN_MACRO, then this is a bit mask for the
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relevant portions of the opcode when disassembling. If the
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actual opcode anded with the match field equals the opcode field,
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then we have found the correct instruction. If pinfo is
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INSN_MACRO, then this field is the macro identifier. */
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unsigned long mask;
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/* For a macro, this is INSN_MACRO. Otherwise, it is a collection
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of bits describing the instruction, notably any relevant hazard
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information. */
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unsigned long pinfo;
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/* A collection of bits describing the instruction sets of which this
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instruction or macro is a member. */
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unsigned long membership;
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};
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/* These are the characters which may appears in the args field of an
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instruction. They appear in the order in which the fields appear
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when the instruction is used. Commas and parentheses in the args
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string are ignored when assembling, and written into the output
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when disassembling.
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Each of these characters corresponds to a mask field defined above.
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"<" 5 bit shift amount (OP_*_SHAMT)
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">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
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"a" 26 bit target address (OP_*_TARGET)
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"b" 5 bit base register (OP_*_RS)
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"c" 10 bit breakpoint code (OP_*_CODE)
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"d" 5 bit destination register specifier (OP_*_RD)
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"h" 5 bit prefx hint (OP_*_PREFX)
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"i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
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"j" 16 bit signed immediate (OP_*_DELTA)
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"k" 5 bit cache opcode in target register position (OP_*_CACHE)
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Also used for immediate operands in vr5400 vector insns.
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"o" 16 bit signed offset (OP_*_DELTA)
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"p" 16 bit PC relative branch target address (OP_*_DELTA)
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"q" 10 bit extra breakpoint code (OP_*_CODE2)
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"r" 5 bit same register used as both source and target (OP_*_RS)
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"s" 5 bit source register specifier (OP_*_RS)
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"t" 5 bit target register (OP_*_RT)
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"u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
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"v" 5 bit same register used as both source and destination (OP_*_RS)
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"w" 5 bit same register used as both target and destination (OP_*_RT)
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"U" 5 bit same destination register in both OP_*_RD and OP_*_RT
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(used by clo and clz)
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"C" 25 bit coprocessor function code (OP_*_COPZ)
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"B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
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"J" 19 bit wait function code (OP_*_CODE19)
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"x" accept and ignore register name
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"z" must be zero register
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"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
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"+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
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Enforces: 0 <= pos < 32.
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"+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
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Requires that "+A" occur first to set position.
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Enforces: 0 < (pos+size) <= 32.
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"+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
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Requires that "+A" occur first to set position.
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Enforces: 0 < (pos+size) <= 32.
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Floating point instructions:
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"D" 5 bit destination register (OP_*_FD)
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"M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
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"N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
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"S" 5 bit fs source 1 register (OP_*_FS)
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"T" 5 bit ft source 2 register (OP_*_FT)
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"R" 5 bit fr source 3 register (OP_*_FR)
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"V" 5 bit same register used as floating source and destination (OP_*_FS)
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"W" 5 bit same register used as floating target and destination (OP_*_FT)
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Coprocessor instructions:
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"E" 5 bit target register (OP_*_RT)
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"G" 5 bit destination register (OP_*_RD)
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"H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
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"P" 5 bit performance-monitor register (OP_*_PERFREG)
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"e" 5 bit vector register byte specifier (OP_*_VECBYTE)
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"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
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see also "k" above
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"+D" Combined destination register ("G") and sel ("H") for CP0 ops,
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for pretty-printing in disassembly only.
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Macro instructions:
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"A" General 32 bit expression
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"I" 32 bit immediate
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"F" 64 bit floating point constant in .rdata
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"L" 64 bit floating point constant in .lit8
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"f" 32 bit floating point constant
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"l" 32 bit floating point constant in .lit4
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MDMX instruction operands (note that while these use the FP register
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fields, they accept both $fN and $vN names for the registers):
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"O" MDMX alignment offset (OP_*_ALN)
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"Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
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"X" MDMX destination register (OP_*_FD)
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"Y" MDMX source register (OP_*_FS)
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"Z" MDMX source register (OP_*_FT)
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Other:
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"()" parens surrounding optional value
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"," separates operands
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"[]" brackets around index for vector-op scalar operand specifier (vr5400)
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"+" Start of extension sequence.
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Characters used so far, for quick reference when adding more:
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"%[]<>(),+"
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"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
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"abcdefhijklopqrstuvwxz"
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Extension character sequences used so far ("+" followed by the
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following), for quick reference when adding more:
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"ABCD"
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*/
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/* These are the bits which may be set in the pinfo field of an
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instructions, if it is not equal to INSN_MACRO. */
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/* Modifies the general purpose register in OP_*_RD. */
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#define INSN_WRITE_GPR_D 0x00000001
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/* Modifies the general purpose register in OP_*_RT. */
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#define INSN_WRITE_GPR_T 0x00000002
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/* Modifies general purpose register 31. */
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#define INSN_WRITE_GPR_31 0x00000004
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/* Modifies the floating point register in OP_*_FD. */
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#define INSN_WRITE_FPR_D 0x00000008
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/* Modifies the floating point register in OP_*_FS. */
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#define INSN_WRITE_FPR_S 0x00000010
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/* Modifies the floating point register in OP_*_FT. */
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#define INSN_WRITE_FPR_T 0x00000020
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/* Reads the general purpose register in OP_*_RS. */
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#define INSN_READ_GPR_S 0x00000040
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/* Reads the general purpose register in OP_*_RT. */
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#define INSN_READ_GPR_T 0x00000080
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/* Reads the floating point register in OP_*_FS. */
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#define INSN_READ_FPR_S 0x00000100
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/* Reads the floating point register in OP_*_FT. */
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#define INSN_READ_FPR_T 0x00000200
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/* Reads the floating point register in OP_*_FR. */
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#define INSN_READ_FPR_R 0x00000400
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/* Modifies coprocessor condition code. */
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#define INSN_WRITE_COND_CODE 0x00000800
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/* Reads coprocessor condition code. */
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#define INSN_READ_COND_CODE 0x00001000
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/* TLB operation. */
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#define INSN_TLB 0x00002000
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/* Reads coprocessor register other than floating point register. */
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#define INSN_COP 0x00004000
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/* Instruction loads value from memory, requiring delay. */
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#define INSN_LOAD_MEMORY_DELAY 0x00008000
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/* Instruction loads value from coprocessor, requiring delay. */
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#define INSN_LOAD_COPROC_DELAY 0x00010000
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/* Instruction has unconditional branch delay slot. */
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#define INSN_UNCOND_BRANCH_DELAY 0x00020000
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/* Instruction has conditional branch delay slot. */
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#define INSN_COND_BRANCH_DELAY 0x00040000
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/* Conditional branch likely: if branch not taken, insn nullified. */
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#define INSN_COND_BRANCH_LIKELY 0x00080000
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/* Moves to coprocessor register, requiring delay. */
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#define INSN_COPROC_MOVE_DELAY 0x00100000
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/* Loads coprocessor register from memory, requiring delay. */
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#define INSN_COPROC_MEMORY_DELAY 0x00200000
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/* Reads the HI register. */
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#define INSN_READ_HI 0x00400000
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/* Reads the LO register. */
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#define INSN_READ_LO 0x00800000
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/* Modifies the HI register. */
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#define INSN_WRITE_HI 0x01000000
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/* Modifies the LO register. */
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#define INSN_WRITE_LO 0x02000000
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/* Takes a trap (easier to keep out of delay slot). */
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#define INSN_TRAP 0x04000000
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/* Instruction stores value into memory. */
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#define INSN_STORE_MEMORY 0x08000000
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/* Instruction uses single precision floating point. */
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#define FP_S 0x10000000
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/* Instruction uses double precision floating point. */
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#define FP_D 0x20000000
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/* Instruction is part of the tx39's integer multiply family. */
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#define INSN_MULT 0x40000000
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/* Instruction synchronize shared memory. */
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#define INSN_SYNC 0x80000000
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/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */
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#define INSN_READ_MDMX_ACC 0
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/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */
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#define INSN_WRITE_MDMX_ACC 0
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/* Instruction is actually a macro. It should be ignored by the
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disassembler, and requires special treatment by the assembler. */
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#define INSN_MACRO 0xffffffff
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/* Masks used to mark instructions to indicate which MIPS ISA level
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they were introduced in. ISAs, as defined below, are logical
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ORs of these bits, indicating that they support the instructions
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defined at the given level. */
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#define INSN_ISA_MASK 0x00000fff
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#define INSN_ISA1 0x00000001
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#define INSN_ISA2 0x00000002
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#define INSN_ISA3 0x00000004
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#define INSN_ISA4 0x00000008
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#define INSN_ISA5 0x00000010
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#define INSN_ISA32 0x00000020
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#define INSN_ISA64 0x00000040
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#define INSN_ISA32R2 0x00000080
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/* Masks used for MIPS-defined ASEs. */
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#define INSN_ASE_MASK 0x0000f000
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/* MIPS 16 ASE */
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#define INSN_MIPS16 0x00002000
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/* MIPS-3D ASE */
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#define INSN_MIPS3D 0x00004000
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/* MDMX ASE */
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#define INSN_MDMX 0x00008000
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/* Chip specific instructions. These are bitmasks. */
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/* MIPS R4650 instruction. */
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#define INSN_4650 0x00010000
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/* LSI R4010 instruction. */
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#define INSN_4010 0x00020000
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/* NEC VR4100 instruction. */
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#define INSN_4100 0x00040000
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/* Toshiba R3900 instruction. */
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#define INSN_3900 0x00080000
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/* MIPS R10000 instruction. */
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#define INSN_10000 0x00100000
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/* Broadcom SB-1 instruction. */
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#define INSN_SB1 0x00200000
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/* NEC VR4111/VR4181 instruction. */
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#define INSN_4111 0x00400000
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/* NEC VR4120 instruction. */
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#define INSN_4120 0x00800000
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/* NEC VR5400 instruction. */
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#define INSN_5400 0x01000000
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/* NEC VR5500 instruction. */
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#define INSN_5500 0x02000000
|
||
|
||
/* MIPS ISA defines, use instead of hardcoding ISA level. */
|
||
|
||
#define ISA_UNKNOWN 0 /* Gas internal use. */
|
||
#define ISA_MIPS1 (INSN_ISA1)
|
||
#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
|
||
#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
|
||
#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
|
||
#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
|
||
|
||
#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
|
||
#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
|
||
|
||
#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2)
|
||
|
||
/* CPU defines, use instead of hardcoding processor number. Keep this
|
||
in sync with bfd/archures.c in order for machine selection to work. */
|
||
#define CPU_UNKNOWN 0 /* Gas internal use. */
|
||
#define CPU_R3000 3000
|
||
#define CPU_R3900 3900
|
||
#define CPU_R4000 4000
|
||
#define CPU_R4010 4010
|
||
#define CPU_VR4100 4100
|
||
#define CPU_R4111 4111
|
||
#define CPU_VR4120 4120
|
||
#define CPU_R4300 4300
|
||
#define CPU_R4400 4400
|
||
#define CPU_R4600 4600
|
||
#define CPU_R4650 4650
|
||
#define CPU_R5000 5000
|
||
#define CPU_VR5400 5400
|
||
#define CPU_VR5500 5500
|
||
#define CPU_R6000 6000
|
||
#define CPU_R8000 8000
|
||
#define CPU_R10000 10000
|
||
#define CPU_R12000 12000
|
||
#define CPU_MIPS16 16
|
||
#define CPU_MIPS32 32
|
||
#define CPU_MIPS32R2 33
|
||
#define CPU_MIPS5 5
|
||
#define CPU_MIPS64 64
|
||
#define CPU_SB1 12310201 /* octal 'SB', 01. */
|
||
|
||
/* Test for membership in an ISA including chip specific ISAs. INSN
|
||
is pointer to an element of the opcode table; ISA is the specified
|
||
ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
|
||
test, or zero if no CPU specific ISA test is desired. */
|
||
|
||
#define OPCODE_IS_MEMBER(insn, isa, cpu) \
|
||
(((insn)->membership & isa) != 0 \
|
||
|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
|
||
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|
||
|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
|
||
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
|
||
|| ((cpu == CPU_R10000 || cpu == CPU_R12000) \
|
||
&& ((insn)->membership & INSN_10000) != 0) \
|
||
|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
|
||
|| (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
|
||
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
|
||
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
|
||
|| (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
|
||
|| 0) /* Please keep this term for easier source merging. */
|
||
|
||
/* This is a list of macro expanded instructions.
|
||
|
||
_I appended means immediate
|
||
_A appended means address
|
||
_AB appended means address with base register
|
||
_D appended means 64 bit floating point constant
|
||
_S appended means 32 bit floating point constant. */
|
||
|
||
enum
|
||
{
|
||
M_ABS,
|
||
M_ADD_I,
|
||
M_ADDU_I,
|
||
M_AND_I,
|
||
M_BEQ,
|
||
M_BEQ_I,
|
||
M_BEQL_I,
|
||
M_BGE,
|
||
M_BGEL,
|
||
M_BGE_I,
|
||
M_BGEL_I,
|
||
M_BGEU,
|
||
M_BGEUL,
|
||
M_BGEU_I,
|
||
M_BGEUL_I,
|
||
M_BGT,
|
||
M_BGTL,
|
||
M_BGT_I,
|
||
M_BGTL_I,
|
||
M_BGTU,
|
||
M_BGTUL,
|
||
M_BGTU_I,
|
||
M_BGTUL_I,
|
||
M_BLE,
|
||
M_BLEL,
|
||
M_BLE_I,
|
||
M_BLEL_I,
|
||
M_BLEU,
|
||
M_BLEUL,
|
||
M_BLEU_I,
|
||
M_BLEUL_I,
|
||
M_BLT,
|
||
M_BLTL,
|
||
M_BLT_I,
|
||
M_BLTL_I,
|
||
M_BLTU,
|
||
M_BLTUL,
|
||
M_BLTU_I,
|
||
M_BLTUL_I,
|
||
M_BNE,
|
||
M_BNE_I,
|
||
M_BNEL_I,
|
||
M_DABS,
|
||
M_DADD_I,
|
||
M_DADDU_I,
|
||
M_DDIV_3,
|
||
M_DDIV_3I,
|
||
M_DDIVU_3,
|
||
M_DDIVU_3I,
|
||
M_DIV_3,
|
||
M_DIV_3I,
|
||
M_DIVU_3,
|
||
M_DIVU_3I,
|
||
M_DLA_AB,
|
||
M_DLI,
|
||
M_DMUL,
|
||
M_DMUL_I,
|
||
M_DMULO,
|
||
M_DMULO_I,
|
||
M_DMULOU,
|
||
M_DMULOU_I,
|
||
M_DREM_3,
|
||
M_DREM_3I,
|
||
M_DREMU_3,
|
||
M_DREMU_3I,
|
||
M_DSUB_I,
|
||
M_DSUBU_I,
|
||
M_DSUBU_I_2,
|
||
M_J_A,
|
||
M_JAL_1,
|
||
M_JAL_2,
|
||
M_JAL_A,
|
||
M_L_DOB,
|
||
M_L_DAB,
|
||
M_LA_AB,
|
||
M_LB_A,
|
||
M_LB_AB,
|
||
M_LBU_A,
|
||
M_LBU_AB,
|
||
M_LD_A,
|
||
M_LD_OB,
|
||
M_LD_AB,
|
||
M_LDC1_AB,
|
||
M_LDC2_AB,
|
||
M_LDC3_AB,
|
||
M_LDL_AB,
|
||
M_LDR_AB,
|
||
M_LH_A,
|
||
M_LH_AB,
|
||
M_LHU_A,
|
||
M_LHU_AB,
|
||
M_LI,
|
||
M_LI_D,
|
||
M_LI_DD,
|
||
M_LI_S,
|
||
M_LI_SS,
|
||
M_LL_AB,
|
||
M_LLD_AB,
|
||
M_LS_A,
|
||
M_LW_A,
|
||
M_LW_AB,
|
||
M_LWC0_A,
|
||
M_LWC0_AB,
|
||
M_LWC1_A,
|
||
M_LWC1_AB,
|
||
M_LWC2_A,
|
||
M_LWC2_AB,
|
||
M_LWC3_A,
|
||
M_LWC3_AB,
|
||
M_LWL_A,
|
||
M_LWL_AB,
|
||
M_LWR_A,
|
||
M_LWR_AB,
|
||
M_LWU_AB,
|
||
M_MOVE,
|
||
M_MUL,
|
||
M_MUL_I,
|
||
M_MULO,
|
||
M_MULO_I,
|
||
M_MULOU,
|
||
M_MULOU_I,
|
||
M_NOR_I,
|
||
M_OR_I,
|
||
M_REM_3,
|
||
M_REM_3I,
|
||
M_REMU_3,
|
||
M_REMU_3I,
|
||
M_DROL,
|
||
M_ROL,
|
||
M_DROL_I,
|
||
M_ROL_I,
|
||
M_DROR,
|
||
M_ROR,
|
||
M_DROR_I,
|
||
M_ROR_I,
|
||
M_S_DA,
|
||
M_S_DOB,
|
||
M_S_DAB,
|
||
M_S_S,
|
||
M_SC_AB,
|
||
M_SCD_AB,
|
||
M_SD_A,
|
||
M_SD_OB,
|
||
M_SD_AB,
|
||
M_SDC1_AB,
|
||
M_SDC2_AB,
|
||
M_SDC3_AB,
|
||
M_SDL_AB,
|
||
M_SDR_AB,
|
||
M_SEQ,
|
||
M_SEQ_I,
|
||
M_SGE,
|
||
M_SGE_I,
|
||
M_SGEU,
|
||
M_SGEU_I,
|
||
M_SGT,
|
||
M_SGT_I,
|
||
M_SGTU,
|
||
M_SGTU_I,
|
||
M_SLE,
|
||
M_SLE_I,
|
||
M_SLEU,
|
||
M_SLEU_I,
|
||
M_SLT_I,
|
||
M_SLTU_I,
|
||
M_SNE,
|
||
M_SNE_I,
|
||
M_SB_A,
|
||
M_SB_AB,
|
||
M_SH_A,
|
||
M_SH_AB,
|
||
M_SW_A,
|
||
M_SW_AB,
|
||
M_SWC0_A,
|
||
M_SWC0_AB,
|
||
M_SWC1_A,
|
||
M_SWC1_AB,
|
||
M_SWC2_A,
|
||
M_SWC2_AB,
|
||
M_SWC3_A,
|
||
M_SWC3_AB,
|
||
M_SWL_A,
|
||
M_SWL_AB,
|
||
M_SWR_A,
|
||
M_SWR_AB,
|
||
M_SUB_I,
|
||
M_SUBU_I,
|
||
M_SUBU_I_2,
|
||
M_TEQ_I,
|
||
M_TGE_I,
|
||
M_TGEU_I,
|
||
M_TLT_I,
|
||
M_TLTU_I,
|
||
M_TNE_I,
|
||
M_TRUNCWD,
|
||
M_TRUNCWS,
|
||
M_ULD,
|
||
M_ULD_A,
|
||
M_ULH,
|
||
M_ULH_A,
|
||
M_ULHU,
|
||
M_ULHU_A,
|
||
M_ULW,
|
||
M_ULW_A,
|
||
M_USH,
|
||
M_USH_A,
|
||
M_USW,
|
||
M_USW_A,
|
||
M_USD,
|
||
M_USD_A,
|
||
M_XOR_I,
|
||
M_COP0,
|
||
M_COP1,
|
||
M_COP2,
|
||
M_COP3,
|
||
M_NUM_MACROS
|
||
};
|
||
|
||
|
||
/* The order of overloaded instructions matters. Label arguments and
|
||
register arguments look the same. Instructions that can have either
|
||
for arguments must apear in the correct order in this table for the
|
||
assembler to pick the right one. In other words, entries with
|
||
immediate operands must apear after the same instruction with
|
||
registers.
|
||
|
||
Many instructions are short hand for other instructions (i.e., The
|
||
jal <register> instruction is short for jalr <register>). */
|
||
|
||
extern const struct mips_opcode mips_builtin_opcodes[];
|
||
extern const int bfd_mips_num_builtin_opcodes;
|
||
extern struct mips_opcode *mips_opcodes;
|
||
extern int bfd_mips_num_opcodes;
|
||
#define NUMOPCODES bfd_mips_num_opcodes
|
||
|
||
|
||
/* The rest of this file adds definitions for the mips16 TinyRISC
|
||
processor. */
|
||
|
||
/* These are the bitmasks and shift counts used for the different
|
||
fields in the instruction formats. Other than OP, no masks are
|
||
provided for the fixed portions of an instruction, since they are
|
||
not needed.
|
||
|
||
The I format uses IMM11.
|
||
|
||
The RI format uses RX and IMM8.
|
||
|
||
The RR format uses RX, and RY.
|
||
|
||
The RRI format uses RX, RY, and IMM5.
|
||
|
||
The RRR format uses RX, RY, and RZ.
|
||
|
||
The RRI_A format uses RX, RY, and IMM4.
|
||
|
||
The SHIFT format uses RX, RY, and SHAMT.
|
||
|
||
The I8 format uses IMM8.
|
||
|
||
The I8_MOVR32 format uses RY and REGR32.
|
||
|
||
The IR_MOV32R format uses REG32R and MOV32Z.
|
||
|
||
The I64 format uses IMM8.
|
||
|
||
The RI64 format uses RY and IMM5.
|
||
*/
|
||
|
||
#define MIPS16OP_MASK_OP 0x1f
|
||
#define MIPS16OP_SH_OP 11
|
||
#define MIPS16OP_MASK_IMM11 0x7ff
|
||
#define MIPS16OP_SH_IMM11 0
|
||
#define MIPS16OP_MASK_RX 0x7
|
||
#define MIPS16OP_SH_RX 8
|
||
#define MIPS16OP_MASK_IMM8 0xff
|
||
#define MIPS16OP_SH_IMM8 0
|
||
#define MIPS16OP_MASK_RY 0x7
|
||
#define MIPS16OP_SH_RY 5
|
||
#define MIPS16OP_MASK_IMM5 0x1f
|
||
#define MIPS16OP_SH_IMM5 0
|
||
#define MIPS16OP_MASK_RZ 0x7
|
||
#define MIPS16OP_SH_RZ 2
|
||
#define MIPS16OP_MASK_IMM4 0xf
|
||
#define MIPS16OP_SH_IMM4 0
|
||
#define MIPS16OP_MASK_REGR32 0x1f
|
||
#define MIPS16OP_SH_REGR32 0
|
||
#define MIPS16OP_MASK_REG32R 0x1f
|
||
#define MIPS16OP_SH_REG32R 3
|
||
#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
|
||
#define MIPS16OP_MASK_MOVE32Z 0x7
|
||
#define MIPS16OP_SH_MOVE32Z 0
|
||
#define MIPS16OP_MASK_IMM6 0x3f
|
||
#define MIPS16OP_SH_IMM6 5
|
||
|
||
/* These are the characters which may appears in the args field of an
|
||
instruction. They appear in the order in which the fields appear
|
||
when the instruction is used. Commas and parentheses in the args
|
||
string are ignored when assembling, and written into the output
|
||
when disassembling.
|
||
|
||
"y" 3 bit register (MIPS16OP_*_RY)
|
||
"x" 3 bit register (MIPS16OP_*_RX)
|
||
"z" 3 bit register (MIPS16OP_*_RZ)
|
||
"Z" 3 bit register (MIPS16OP_*_MOVE32Z)
|
||
"v" 3 bit same register as source and destination (MIPS16OP_*_RX)
|
||
"w" 3 bit same register as source and destination (MIPS16OP_*_RY)
|
||
"0" zero register ($0)
|
||
"S" stack pointer ($sp or $29)
|
||
"P" program counter
|
||
"R" return address register ($ra or $31)
|
||
"X" 5 bit MIPS register (MIPS16OP_*_REGR32)
|
||
"Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
|
||
"6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
|
||
"a" 26 bit jump address
|
||
"e" 11 bit extension value
|
||
"l" register list for entry instruction
|
||
"L" register list for exit instruction
|
||
|
||
The remaining codes may be extended. Except as otherwise noted,
|
||
the full extended operand is a 16 bit signed value.
|
||
"<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
|
||
">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
|
||
"[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
|
||
"]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
|
||
"4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
|
||
"5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
|
||
"H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
|
||
"W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
|
||
"D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
|
||
"j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
|
||
"8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
|
||
"V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
|
||
"C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
|
||
"U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
|
||
"k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
|
||
"K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
|
||
"p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
|
||
"q" 11 bit branch address (MIPS16OP_*_IMM11)
|
||
"A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
|
||
"B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
|
||
"E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
|
||
*/
|
||
|
||
/* For the mips16, we use the same opcode table format and a few of
|
||
the same flags. However, most of the flags are different. */
|
||
|
||
/* Modifies the register in MIPS16OP_*_RX. */
|
||
#define MIPS16_INSN_WRITE_X 0x00000001
|
||
/* Modifies the register in MIPS16OP_*_RY. */
|
||
#define MIPS16_INSN_WRITE_Y 0x00000002
|
||
/* Modifies the register in MIPS16OP_*_RZ. */
|
||
#define MIPS16_INSN_WRITE_Z 0x00000004
|
||
/* Modifies the T ($24) register. */
|
||
#define MIPS16_INSN_WRITE_T 0x00000008
|
||
/* Modifies the SP ($29) register. */
|
||
#define MIPS16_INSN_WRITE_SP 0x00000010
|
||
/* Modifies the RA ($31) register. */
|
||
#define MIPS16_INSN_WRITE_31 0x00000020
|
||
/* Modifies the general purpose register in MIPS16OP_*_REG32R. */
|
||
#define MIPS16_INSN_WRITE_GPR_Y 0x00000040
|
||
/* Reads the register in MIPS16OP_*_RX. */
|
||
#define MIPS16_INSN_READ_X 0x00000080
|
||
/* Reads the register in MIPS16OP_*_RY. */
|
||
#define MIPS16_INSN_READ_Y 0x00000100
|
||
/* Reads the register in MIPS16OP_*_MOVE32Z. */
|
||
#define MIPS16_INSN_READ_Z 0x00000200
|
||
/* Reads the T ($24) register. */
|
||
#define MIPS16_INSN_READ_T 0x00000400
|
||
/* Reads the SP ($29) register. */
|
||
#define MIPS16_INSN_READ_SP 0x00000800
|
||
/* Reads the RA ($31) register. */
|
||
#define MIPS16_INSN_READ_31 0x00001000
|
||
/* Reads the program counter. */
|
||
#define MIPS16_INSN_READ_PC 0x00002000
|
||
/* Reads the general purpose register in MIPS16OP_*_REGR32. */
|
||
#define MIPS16_INSN_READ_GPR_X 0x00004000
|
||
/* Is a branch insn. */
|
||
#define MIPS16_INSN_BRANCH 0x00010000
|
||
|
||
/* The following flags have the same value for the mips16 opcode
|
||
table:
|
||
INSN_UNCOND_BRANCH_DELAY
|
||
INSN_COND_BRANCH_DELAY
|
||
INSN_COND_BRANCH_LIKELY (never used)
|
||
INSN_READ_HI
|
||
INSN_READ_LO
|
||
INSN_WRITE_HI
|
||
INSN_WRITE_LO
|
||
INSN_TRAP
|
||
INSN_ISA3
|
||
*/
|
||
|
||
extern const struct mips_opcode mips16_opcodes[];
|
||
extern const int bfd_mips16_num_opcodes;
|
||
|
||
#endif /* _MIPS_H_ */
|