28e7fd6234
Two modifications:
1. The addition of 2013 to the copyright year range for every file;
2. The use of a single year range, instead of potentially multiple
year ranges, as approved by the FSF.
390 lines
11 KiB
C
390 lines
11 KiB
C
/* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
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Copyright (C) 1995-2013 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "server.h"
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#include "linux-low.h"
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#include <sys/ptrace.h>
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/* Defined in auto-generated file reg-crisv32.c. */
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void init_registers_crisv32 (void);
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/* CRISv32 */
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#define cris_num_regs 49
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/* Note: Ignoring USP (having the stack pointer in two locations causes trouble
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without any significant gain). */
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/* Locations need to match <include/asm/arch/ptrace.h>. */
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static int cris_regmap[] = {
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1*4, 2*4, 3*4, 4*4,
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5*4, 6*4, 7*4, 8*4,
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9*4, 10*4, 11*4, 12*4,
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13*4, 14*4, 24*4, 15*4,
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-1, -1, -1, 16*4,
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-1, 22*4, 23*4, 17*4,
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-1, -1, 21*4, 20*4,
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-1, 19*4, -1, 18*4,
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25*4,
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26*4, -1, -1, 29*4,
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30*4, 31*4, 32*4, 33*4,
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34*4, 35*4, 36*4, 37*4,
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38*4, 39*4, 40*4, -1
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};
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extern int debug_threads;
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static CORE_ADDR
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cris_get_pc (struct regcache *regcache)
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{
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unsigned long pc;
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collect_register_by_name (regcache, "pc", &pc);
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if (debug_threads)
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fprintf (stderr, "stop pc is %08lx\n", pc);
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return pc;
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}
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static void
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cris_set_pc (struct regcache *regcache, CORE_ADDR pc)
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{
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unsigned long newpc = pc;
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supply_register_by_name (regcache, "pc", &newpc);
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}
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static const unsigned short cris_breakpoint = 0xe938;
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#define cris_breakpoint_len 2
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static int
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cris_breakpoint_at (CORE_ADDR where)
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{
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unsigned short insn;
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(*the_target->read_memory) (where, (unsigned char *) &insn,
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cris_breakpoint_len);
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if (insn == cris_breakpoint)
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return 1;
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/* If necessary, recognize more trap instructions here. GDB only uses the
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one. */
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return 0;
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}
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/* We only place breakpoints in empty marker functions, and thread locking
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is outside of the function. So rather than importing software single-step,
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we can just run until exit. */
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/* FIXME: This function should not be needed, since we have PTRACE_SINGLESTEP
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for CRISv32. Without it, td_ta_event_getmsg in thread_db_create_event
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will fail when debugging multi-threaded applications. */
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static CORE_ADDR
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cris_reinsert_addr (void)
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{
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struct regcache *regcache = get_thread_regcache (current_inferior, 1);
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unsigned long pc;
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collect_register_by_name (regcache, "srp", &pc);
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return pc;
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}
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static void
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cris_write_data_breakpoint (struct regcache *regcache,
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int bp, unsigned long start, unsigned long end)
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{
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switch (bp)
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{
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case 0:
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supply_register_by_name (regcache, "s3", &start);
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supply_register_by_name (regcache, "s4", &end);
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break;
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case 1:
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supply_register_by_name (regcache, "s5", &start);
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supply_register_by_name (regcache, "s6", &end);
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break;
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case 2:
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supply_register_by_name (regcache, "s7", &start);
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supply_register_by_name (regcache, "s8", &end);
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break;
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case 3:
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supply_register_by_name (regcache, "s9", &start);
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supply_register_by_name (regcache, "s10", &end);
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break;
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case 4:
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supply_register_by_name (regcache, "s11", &start);
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supply_register_by_name (regcache, "s12", &end);
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break;
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case 5:
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supply_register_by_name (regcache, "s13", &start);
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supply_register_by_name (regcache, "s14", &end);
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break;
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}
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}
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static int
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cris_insert_point (char type, CORE_ADDR addr, int len)
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{
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int bp;
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unsigned long bp_ctrl;
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unsigned long start, end;
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unsigned long ccs;
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struct regcache *regcache;
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/* Breakpoint/watchpoint types (GDB terminology):
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0 = memory breakpoint for instructions
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(not supported; done via memory write instead)
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1 = hardware breakpoint for instructions (not supported)
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2 = write watchpoint (supported)
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3 = read watchpoint (supported)
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4 = access watchpoint (supported). */
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if (type < '2' || type > '4')
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{
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/* Unsupported. */
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return 1;
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}
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regcache = get_thread_regcache (current_inferior, 1);
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/* Read watchpoints are set as access watchpoints, because of GDB's
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inability to deal with pure read watchpoints. */
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if (type == '3')
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type = '4';
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/* Get the configuration register. */
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collect_register_by_name (regcache, "s0", &bp_ctrl);
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/* The watchpoint allocation scheme is the simplest possible.
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For example, if a region is watched for read and
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a write watch is requested, a new watchpoint will
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be used. Also, if a watch for a region that is already
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covered by one or more existing watchpoints, a new
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watchpoint will be used. */
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/* First, find a free data watchpoint. */
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for (bp = 0; bp < 6; bp++)
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{
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/* Each data watchpoint's control registers occupy 2 bits
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(hence the 3), starting at bit 2 for D0 (hence the 2)
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with 4 bits between for each watchpoint (yes, the 4). */
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if (!(bp_ctrl & (0x3 << (2 + (bp * 4)))))
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break;
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}
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if (bp > 5)
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{
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/* We're out of watchpoints. */
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return -1;
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}
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/* Configure the control register first. */
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if (type == '3' || type == '4')
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{
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/* Trigger on read. */
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bp_ctrl |= (1 << (2 + bp * 4));
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}
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if (type == '2' || type == '4')
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{
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/* Trigger on write. */
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bp_ctrl |= (2 << (2 + bp * 4));
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}
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/* Setup the configuration register. */
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supply_register_by_name (regcache, "s0", &bp_ctrl);
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/* Setup the range. */
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start = addr;
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end = addr + len - 1;
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/* Configure the watchpoint register. */
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cris_write_data_breakpoint (regcache, bp, start, end);
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collect_register_by_name (regcache, "ccs", &ccs);
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/* Set the S1 flag to enable watchpoints. */
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ccs |= (1 << 19);
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supply_register_by_name (regcache, "ccs", &ccs);
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return 0;
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}
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static int
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cris_remove_point (char type, CORE_ADDR addr, int len)
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{
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int bp;
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unsigned long bp_ctrl;
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unsigned long start, end;
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struct regcache *regcache;
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unsigned long bp_d_regs[12];
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/* Breakpoint/watchpoint types:
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0 = memory breakpoint for instructions
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(not supported; done via memory write instead)
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1 = hardware breakpoint for instructions (not supported)
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2 = write watchpoint (supported)
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3 = read watchpoint (supported)
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4 = access watchpoint (supported). */
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if (type < '2' || type > '4')
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return -1;
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regcache = get_thread_regcache (current_inferior, 1);
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/* Read watchpoints are set as access watchpoints, because of GDB's
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inability to deal with pure read watchpoints. */
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if (type == '3')
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type = '4';
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/* Get the configuration register. */
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collect_register_by_name (regcache, "s0", &bp_ctrl);
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/* Try to find a watchpoint that is configured for the
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specified range, then check that read/write also matches. */
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/* Ugly pointer arithmetic, since I cannot rely on a
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single switch (addr) as there may be several watchpoints with
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the same start address for example. */
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/* Get all range registers to simplify search. */
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collect_register_by_name (regcache, "s3", &bp_d_regs[0]);
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collect_register_by_name (regcache, "s4", &bp_d_regs[1]);
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collect_register_by_name (regcache, "s5", &bp_d_regs[2]);
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collect_register_by_name (regcache, "s6", &bp_d_regs[3]);
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collect_register_by_name (regcache, "s7", &bp_d_regs[4]);
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collect_register_by_name (regcache, "s8", &bp_d_regs[5]);
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collect_register_by_name (regcache, "s9", &bp_d_regs[6]);
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collect_register_by_name (regcache, "s10", &bp_d_regs[7]);
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collect_register_by_name (regcache, "s11", &bp_d_regs[8]);
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collect_register_by_name (regcache, "s12", &bp_d_regs[9]);
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collect_register_by_name (regcache, "s13", &bp_d_regs[10]);
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collect_register_by_name (regcache, "s14", &bp_d_regs[11]);
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for (bp = 0; bp < 6; bp++)
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{
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if (bp_d_regs[bp * 2] == addr
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&& bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
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/* Matching range. */
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int bitpos = 2 + bp * 4;
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int rw_bits;
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/* Read/write bits for this BP. */
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rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos;
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if ((type == '3' && rw_bits == 0x1)
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|| (type == '2' && rw_bits == 0x2)
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|| (type == '4' && rw_bits == 0x3))
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{
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/* Read/write matched. */
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break;
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}
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}
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}
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if (bp > 5)
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{
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/* No watchpoint matched. */
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return -1;
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}
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/* Found a matching watchpoint. Now, deconfigure it by
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both disabling read/write in bp_ctrl and zeroing its
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start/end addresses. */
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bp_ctrl &= ~(3 << (2 + (bp * 4)));
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/* Setup the configuration register. */
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supply_register_by_name (regcache, "s0", &bp_ctrl);
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start = end = 0;
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/* Configure the watchpoint register. */
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cris_write_data_breakpoint (regcache, bp, start, end);
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/* Note that we don't clear the S1 flag here. It's done when continuing. */
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return 0;
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}
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static int
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cris_stopped_by_watchpoint (void)
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{
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unsigned long exs;
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struct regcache *regcache = get_thread_regcache (current_inferior, 1);
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collect_register_by_name (regcache, "exs", &exs);
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return (((exs & 0xff00) >> 8) == 0xc);
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}
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static CORE_ADDR
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cris_stopped_data_address (void)
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{
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unsigned long eda;
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struct regcache *regcache = get_thread_regcache (current_inferior, 1);
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collect_register_by_name (regcache, "eda", &eda);
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/* FIXME: Possibly adjust to match watched range. */
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return eda;
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}
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static void
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cris_fill_gregset (struct regcache *regcache, void *buf)
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{
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int i;
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for (i = 0; i < cris_num_regs; i++)
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{
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if (cris_regmap[i] != -1)
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collect_register (regcache, i, ((char *) buf) + cris_regmap[i]);
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}
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}
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static void
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cris_store_gregset (struct regcache *regcache, const void *buf)
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{
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int i;
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for (i = 0; i < cris_num_regs; i++)
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{
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if (cris_regmap[i] != -1)
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supply_register (regcache, i, ((char *) buf) + cris_regmap[i]);
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}
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}
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struct regset_info target_regsets[] = {
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{ PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4,
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GENERAL_REGS, cris_fill_gregset, cris_store_gregset },
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{ 0, 0, 0, -1, -1, NULL, NULL }
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};
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struct linux_target_ops the_low_target = {
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init_registers_crisv32,
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-1,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL, /* fetch_register */
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cris_get_pc,
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cris_set_pc,
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(const unsigned char *) &cris_breakpoint,
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cris_breakpoint_len,
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cris_reinsert_addr,
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0,
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cris_breakpoint_at,
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cris_insert_point,
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cris_remove_point,
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cris_stopped_by_watchpoint,
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cris_stopped_data_address,
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};
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