3539aa13fb
Bits 20 ~ 23 of CPSR are reserved (RAZ, read as zero), but they are not zero if the arm program runs on aarch64-linux. AArch64 tracer gets PSTATE from arm 32-bit tracee as CPSR, but bits 20 ~ 23 are used in PSTATE. I think kernel should clear these bits when it is read through ptrace, but the fix in user space is still needed. This patch fixes these two fails, -FAIL: gdb.reverse/insn-reverse.exp: ext_reg_push_pop: compare registers on insn 0:vldr d7, [r11, #-12] -FAIL: gdb.reverse/insn-reverse.exp: ext_reg_push_pop: compare registers on insn 0:vldr d7, [r7] gdb: 2016-04-22 Yao Qi <yao.qi@linaro.org> * aarch32-linux-nat.c (aarch32_gp_regcache_supply): Clear CPSR bits 20 to 23. gdb/gdbserver: 2016-04-22 Yao Qi <yao.qi@linaro.org> * linux-aarch32-low.c (arm_store_gregset): Clear CPSR bits 20 to 23.
104 lines
3.2 KiB
C
104 lines
3.2 KiB
C
/* Copyright (C) 1999-2016 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "regcache.h"
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#include "arm-tdep.h"
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#include "arm-linux-tdep.h"
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#include "arch/arm-linux.h"
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#include "aarch32-linux-nat.h"
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/* Supply GP registers contents, stored in REGS, to REGCACHE. ARM_APCS_32
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is true if the 32-bit mode is in use, otherwise, it is false. */
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void
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aarch32_gp_regcache_supply (struct regcache *regcache, uint32_t *regs,
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int arm_apcs_32)
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{
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int regno;
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for (regno = ARM_A1_REGNUM; regno < ARM_PC_REGNUM; regno++)
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regcache_raw_supply (regcache, regno, ®s[regno]);
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if (arm_apcs_32)
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{
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/* Clear reserved bits bit 20 to bit 23. */
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regs[ARM_CPSR_GREGNUM] &= 0xff0fffff;
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regcache_raw_supply (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]);
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}
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else
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regcache_raw_supply (regcache, ARM_PS_REGNUM, ®s[ARM_PC_REGNUM]);
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regs[ARM_PC_REGNUM] = gdbarch_addr_bits_remove
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(get_regcache_arch (regcache), regs[ARM_PC_REGNUM]);
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regcache_raw_supply (regcache, ARM_PC_REGNUM, ®s[ARM_PC_REGNUM]);
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}
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/* Collect GP registers from REGCACHE to buffer REGS. ARM_APCS_32 is
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true if the 32-bit mode is in use, otherwise, it is false. */
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void
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aarch32_gp_regcache_collect (const struct regcache *regcache, uint32_t *regs,
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int arm_apcs_32)
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{
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int regno;
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for (regno = ARM_A1_REGNUM; regno <= ARM_PC_REGNUM; regno++)
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{
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if (REG_VALID == regcache_register_status (regcache, regno))
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regcache_raw_collect (regcache, regno, ®s[regno]);
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}
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if (arm_apcs_32
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&& REG_VALID == regcache_register_status (regcache, ARM_PS_REGNUM))
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regcache_raw_collect (regcache, ARM_PS_REGNUM,
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®s[ARM_CPSR_GREGNUM]);
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}
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/* Supply VFP registers contents, stored in REGS, to REGCACHE.
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VFP_REGISTER_COUNT is the number of VFP registers. */
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void
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aarch32_vfp_regcache_supply (struct regcache *regcache, gdb_byte *regs,
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const int vfp_register_count)
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{
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int regno;
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for (regno = 0; regno < vfp_register_count; regno++)
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regcache_raw_supply (regcache, regno + ARM_D0_REGNUM,
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regs + regno * 8);
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regcache_raw_supply (regcache, ARM_FPSCR_REGNUM,
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regs + 32 * 8);
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}
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/* Collect VFP registers from REGCACHE to buffer REGS.
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VFP_REGISTER_COUNT is the number VFP registers. */
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void
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aarch32_vfp_regcache_collect (const struct regcache *regcache, gdb_byte *regs,
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const int vfp_register_count)
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{
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int regno;
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for (regno = 0; regno < vfp_register_count; regno++)
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regcache_raw_collect (regcache, regno + ARM_D0_REGNUM, regs + regno * 8);
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regcache_raw_collect (regcache, ARM_FPSCR_REGNUM, regs + 32 * 8);
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}
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