4563a86028
* elf32-arm.c (arm_stub_required_alignment): New.
(arm_build_one_stub): Use above to partition stubs.
(make_branch_to_a8_stub): Use arm_stub_a8_veneer_lwm not
arm_stub_a8_veneer_b_cond.
ld/testsuite/
* ld-arm/arm-elf.exp (armelftests): Add cortex-a8-fix-blx-bcond.s.
* ld-arm/cortex-a8-fix-blx-bcond.s: New.
* ld-arm/cortex-a8-fix-blx-bcond.d: New.
81 lines
849 B
ArmAsm
81 lines
849 B
ArmAsm
.syntax unified
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.cpu cortex-a8
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.thumb
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.text
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@ expansion 32 bytes
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.macro bw1
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1:
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add.w r0, r1, r2
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blx.w arm_target
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add.w r0, r1, r2
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blx.w arm_target
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add.w r0, r1, r2
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blx.w arm_target
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add.w r0, r1, r2
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blx.w arm_target
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.endm
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@ expansion 128 bytes
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.macro bw2
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bw1
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bw1
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bw1
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bw1
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.endm
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@ expansion 32 bytes
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.macro bw3
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1:
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add.w r0, r1, r2
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bne.w 1b
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add.w r0, r1, r2
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bne.w 1b
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add.w r0, r1, r2
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bne.w 1b
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add.w r0, r1, r2
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bne.w 1b
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.endm
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@ expansion 128 bytes
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.macro bw4
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bw3
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bw3
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bw3
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bw3
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.endm
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.align 3
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.global _start
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.thumb
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.thumb_func
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.type _start, %function
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_start:
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nop
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@ Trigger Cortex-A8 erratum workaround with b<cond> instructions.
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bw4
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bw4
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nop
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.rept 957
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nop.w
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.endr
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.arm
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arm_target:
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add r3, r4, r5
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bx lr
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.thumb
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bl_insns:
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nop
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@ ...and again with bl instructions.
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bw2
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bw2
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bx lr
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