1198 lines
31 KiB
C
1198 lines
31 KiB
C
/* This file is part of the program psim.
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Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef _VM_C_
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#define _VM_C_
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#if 0
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#include "basics.h"
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#include "registers.h"
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#include "device.h"
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#include "corefile.h"
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#include "vm.h"
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#include "interrupts.h"
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#include "mon.h"
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#endif
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#include "cpu.h"
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/* OEA vs VEA
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For the VEA model, the VM layer is almost transparent. It's only
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purpose is to maintain separate core_map's for the instruction
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and data address spaces. This being so that writes to instruction
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space or execution of a data space is prevented.
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For the OEA model things are more complex. The reason for separate
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instruction and data models becomes crucial. The OEA model is
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built out of three parts. An instruction map, a data map and an
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underlying structure that provides access to the VM data kept in
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main memory. */
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/* OEA data structures:
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The OEA model maintains internal data structures that shadow the
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semantics of the various OEA VM registers (BAT, SR, etc). This
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allows a simple efficient model of the VM to be implemented.
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Consistency between OEA registers and this model's internal data
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structures is maintained by updating the structures at
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`synchronization' points. Of particular note is that (at the time
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of writing) the memory data types for BAT registers are rebuilt
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when ever the processor moves between problem and system states.
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Unpacked values are stored in the OEA so that they correctly align
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to where they will be needed by the PTE address. */
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/* Protection table:
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Matrix of processor state, type of access and validity */
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typedef enum {
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om_supervisor_state,
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om_problem_state,
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nr_om_modes
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} om_processor_modes;
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typedef enum {
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om_data_read, om_data_write,
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om_instruction_read, om_access_any,
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nr_om_access_types
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} om_access_types;
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static int om_valid_access[2][4][nr_om_access_types] = {
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/* read, write, instruction, any */
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/* K bit == 0 */
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{ /*r w i a pp */
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{ 1, 1, 1, 1 }, /* 00 */
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{ 1, 1, 1, 1 }, /* 01 */
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{ 1, 1, 1, 1 }, /* 10 */
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{ 1, 0, 1, 1 }, /* 11 */
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},
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/* K bit == 1 or P bit valid */
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{ /*r w i a pp */
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{ 0, 0, 0, 0 }, /* 00 */
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{ 1, 0, 1, 1 }, /* 01 */
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{ 1, 1, 1, 1 }, /* 10 */
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{ 1, 0, 1, 1 }, /* 11 */
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}
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};
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/* Bat translation:
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The bat data structure only contains information on valid BAT
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translations for the current processor mode and type of access. */
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typedef struct _om_bat {
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unsigned_word block_effective_page_index;
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unsigned_word block_effective_page_index_mask;
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unsigned_word block_length_mask;
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unsigned_word block_real_page_number;
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int protection_bits;
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} om_bat;
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enum _nr_om_bat_registers {
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nr_om_bat_registers = 4
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};
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typedef struct _om_bats {
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int nr_valid_bat_registers;
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om_bat bat[nr_om_bat_registers];
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} om_bats;
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/* Segment TLB:
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In this model the 32 and 64 bit segment tables are treated in very
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similar ways. The 32bit segment registers are treated as a
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simplification of the 64bit segment tlb */
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enum _om_segment_tlb_constants {
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#if (WITH_TARGET_WORD_BITSIZE == 64)
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sizeof_segment_table_entry_group = 128,
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sizeof_segment_table_entry = 16,
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#endif
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om_segment_tlb_index_start_bit = 32,
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om_segment_tlb_index_stop_bit = 35,
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nr_om_segment_tlb_entries = 16,
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nr_om_segment_tlb_constants
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};
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typedef struct _om_segment_tlb_entry {
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int key[nr_om_modes];
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om_access_types invalid_access; /* set to instruction if no_execute bit */
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unsigned_word masked_virtual_segment_id; /* aligned ready for pte group addr */
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#if (WITH_TARGET_WORD_BITSIZE == 64)
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int is_valid;
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unsigned_word masked_effective_segment_id;
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#endif
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} om_segment_tlb_entry;
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typedef struct _om_segment_tlb {
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om_segment_tlb_entry entry[nr_om_segment_tlb_entries];
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} om_segment_tlb;
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/* Page TLB:
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This OEA model includes a small direct map Page TLB. The tlb is to
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cut down on the need for the OEA to perform walks of the page hash
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table. */
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enum _om_page_tlb_constants {
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om_page_tlb_index_start_bit = 46,
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om_page_tlb_index_stop_bit = 51,
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nr_om_page_tlb_entries = 64,
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#if (WITH_TARGET_WORD_BITSIZE == 64)
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sizeof_pte_group = 128,
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sizeof_pte = 16,
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#endif
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#if (WITH_TARGET_WORD_BITSIZE == 32)
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sizeof_pte_group = 64,
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sizeof_pte = 8,
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#endif
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nr_om_page_tlb_constants
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};
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typedef struct _om_page_tlb_entry {
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int protection;
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int changed;
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unsigned_word real_address_of_pte_1;
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unsigned_word masked_virtual_segment_id;
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unsigned_word masked_page;
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unsigned_word masked_real_page_number;
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} om_page_tlb_entry;
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typedef struct _om_page_tlb {
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om_page_tlb_entry entry[nr_om_page_tlb_entries];
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} om_page_tlb;
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/* memory translation:
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OEA memory translation possibly involves BAT, SR, TLB and HTAB
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information*/
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typedef struct _om_map {
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/* local cache of register values */
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int is_relocate;
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int is_problem_state;
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/* block address translation */
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om_bats *bat_registers;
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/* failing that, translate ea to va using segment tlb */
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#if (WITH_TARGET_WORD_BITSIZE == 64)
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unsigned_word real_address_of_segment_table;
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#endif
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om_segment_tlb *segment_tlb;
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/* then va to ra using hashed page table and tlb */
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unsigned_word real_address_of_page_table;
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unsigned_word page_table_hash_mask;
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om_page_tlb *page_tlb;
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/* physical memory for fetching page table entries */
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core_map *physical;
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/* address xor for PPC endian */
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unsigned xor[WITH_XOR_ENDIAN];
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} om_map;
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/* VM objects:
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External objects defined by vm.h */
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struct _vm_instruction_map {
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/* real memory for last part */
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core_map *code;
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/* translate effective to real */
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om_map translation;
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};
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struct _vm_data_map {
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/* translate effective to real */
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om_map translation;
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/* real memory for translated address */
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core_map *read;
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core_map *write;
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};
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/* VM:
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Underlying memory object. For the VEA this is just the
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core_map. For OEA it is the instruction and data memory
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translation's */
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struct _vm {
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/* OEA: base address registers */
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om_bats ibats;
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om_bats dbats;
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/* OEA: segment registers */
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om_segment_tlb segment_tlb;
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/* OEA: translation lookaside buffers */
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om_page_tlb instruction_tlb;
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om_page_tlb data_tlb;
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/* real memory */
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core *physical;
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/* memory maps */
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vm_instruction_map instruction_map;
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vm_data_map data_map;
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};
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/* OEA Support procedures */
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STATIC_INLINE_VM\
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(unsigned_word)
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om_segment_tlb_index(unsigned_word ea)
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{
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unsigned_word index = EXTRACTED(ea,
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om_segment_tlb_index_start_bit,
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om_segment_tlb_index_stop_bit);
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return index;
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}
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STATIC_INLINE_VM\
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(unsigned_word)
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om_page_tlb_index(unsigned_word ea)
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{
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unsigned_word index = EXTRACTED(ea,
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om_page_tlb_index_start_bit,
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om_page_tlb_index_stop_bit);
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return index;
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}
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STATIC_INLINE_VM\
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(unsigned_word)
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om_hash_page(unsigned_word masked_vsid,
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unsigned_word ea)
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{
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unsigned_word extracted_ea = EXTRACTED(ea, 36, 51);
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#if (WITH_TARGET_WORD_BITSIZE == 32)
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unsigned_word masked_ea = INSERTED32(extracted_ea, 7, 31-6);
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unsigned_word hash = masked_vsid ^ masked_ea;
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#endif
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#if (WITH_TARGET_WORD_BITSIZE == 64)
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unsigned_word masked_ea = INSERTED64(extracted_ea, 18, 63-7);
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unsigned_word hash = masked_vsid ^ masked_ea;
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#endif
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TRACE(trace_vm, ("ea=0x%lx - masked-vsid=0x%lx masked-ea=0x%lx hash=0x%lx\n",
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(unsigned long)ea,
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(unsigned long)masked_vsid,
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(unsigned long)masked_ea,
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(unsigned long)hash));
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return hash;
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}
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STATIC_INLINE_VM\
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(unsigned_word)
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om_pte_0_api(unsigned_word pte_0)
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{
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#if (WITH_TARGET_WORD_BITSIZE == 32)
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return EXTRACTED32(pte_0, 26, 31);
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#endif
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#if (WITH_TARGET_WORD_BITSIZE == 64)
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return EXTRACTED64(pte_0, 52, 56);
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#endif
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}
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STATIC_INLINE_VM\
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(unsigned_word)
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om_pte_0_hash(unsigned_word pte_0)
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{
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#if (WITH_TARGET_WORD_BITSIZE == 32)
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return EXTRACTED32(pte_0, 25, 25);
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#endif
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#if (WITH_TARGET_WORD_BITSIZE == 64)
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return EXTRACTED64(pte_0, 62, 62);
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#endif
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}
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STATIC_INLINE_VM\
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(int)
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om_pte_0_valid(unsigned_word pte_0)
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{
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#if (WITH_TARGET_WORD_BITSIZE == 32)
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return MASKED32(pte_0, 0, 0) != 0;
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#endif
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#if (WITH_TARGET_WORD_BITSIZE == 64)
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return MASKED64(pte_0, 63, 63) != 0;
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#endif
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}
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STATIC_INLINE_VM\
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(unsigned_word)
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om_ea_masked_page(unsigned_word ea)
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{
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return MASKED(ea, 36, 51);
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}
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STATIC_INLINE_VM\
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(unsigned_word)
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om_ea_masked_byte(unsigned_word ea)
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{
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return MASKED(ea, 52, 63);
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}
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/* return the VSID aligned for pte group addr */
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STATIC_INLINE_VM\
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(unsigned_word)
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om_pte_0_masked_vsid(unsigned_word pte_0)
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{
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#if (WITH_TARGET_WORD_BITSIZE == 32)
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return INSERTED32(EXTRACTED32(pte_0, 1, 24), 31-6-24+1, 31-6);
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#endif
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#if (WITH_TARGET_WORD_BITSIZE == 64)
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return INSERTED64(EXTRACTED64(pte_0, 0, 51), 63-7-52+1, 63-7);
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#endif
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}
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STATIC_INLINE_VM\
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(unsigned_word)
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om_pte_1_pp(unsigned_word pte_1)
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{
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return MASKED(pte_1, 62, 63); /*PP*/
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}
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STATIC_INLINE_VM\
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(int)
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om_pte_1_referenced(unsigned_word pte_1)
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{
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return EXTRACTED(pte_1, 55, 55);
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}
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STATIC_INLINE_VM\
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(int)
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om_pte_1_changed(unsigned_word pte_1)
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{
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return EXTRACTED(pte_1, 56, 56);
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}
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STATIC_INLINE_VM\
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(int)
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om_pte_1_masked_rpn(unsigned_word pte_1)
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{
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return MASKED(pte_1, 0, 51); /*RPN*/
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}
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STATIC_INLINE_VM\
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(unsigned_word)
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om_ea_api(unsigned_word ea)
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{
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return EXTRACTED(ea, 36, 41);
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}
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/* Page and Segment table read/write operators, these need to still
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account for the PPC's XOR operation */
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STATIC_INLINE_VM\
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(unsigned_word)
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om_read_word(om_map *map,
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unsigned_word ra,
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cpu *processor,
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unsigned_word cia)
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{
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if (WITH_XOR_ENDIAN)
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ra ^= map->xor[sizeof(instruction_word) - 1];
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return core_map_read_word(map->physical, ra, processor, cia);
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}
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STATIC_INLINE_VM\
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(void)
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om_write_word(om_map *map,
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unsigned_word ra,
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unsigned_word val,
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cpu *processor,
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unsigned_word cia)
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{
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if (WITH_XOR_ENDIAN)
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ra ^= map->xor[sizeof(instruction_word) - 1];
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core_map_write_word(map->physical, ra, val, processor, cia);
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}
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/* Bring things into existance */
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INLINE_VM\
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(vm *)
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vm_create(core *physical)
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{
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vm *virtual;
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/* internal checks */
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if (nr_om_segment_tlb_entries
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!= (1 << (om_segment_tlb_index_stop_bit
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- om_segment_tlb_index_start_bit + 1)))
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error("internal error - vm_create - problem with om_segment constants\n");
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if (nr_om_page_tlb_entries
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!= (1 << (om_page_tlb_index_stop_bit
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- om_page_tlb_index_start_bit + 1)))
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error("internal error - vm_create - problem with om_page constants\n");
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/* create the new vm register file */
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virtual = ZALLOC(vm);
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/* set up core */
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virtual->physical = physical;
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/* set up the address decoders */
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virtual->instruction_map.translation.bat_registers = &virtual->ibats;
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virtual->instruction_map.translation.segment_tlb = &virtual->segment_tlb;
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virtual->instruction_map.translation.page_tlb = &virtual->instruction_tlb;
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virtual->instruction_map.translation.is_relocate = 0;
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virtual->instruction_map.translation.is_problem_state = 0;
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virtual->instruction_map.translation.physical = core_readable(physical);
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virtual->instruction_map.code = core_readable(physical);
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virtual->data_map.translation.bat_registers = &virtual->dbats;
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virtual->data_map.translation.segment_tlb = &virtual->segment_tlb;
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virtual->data_map.translation.page_tlb = &virtual->data_tlb;
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virtual->data_map.translation.is_relocate = 0;
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virtual->data_map.translation.is_problem_state = 0;
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virtual->data_map.translation.physical = core_readable(physical);
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virtual->data_map.read = core_readable(physical);
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virtual->data_map.write = core_writeable(physical);
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return virtual;
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}
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STATIC_INLINE_VM\
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(om_bat *)
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om_effective_to_bat(om_map *map,
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unsigned_word ea)
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{
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int curr_bat = 0;
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om_bats *bats = map->bat_registers;
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int nr_bats = bats->nr_valid_bat_registers;
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for (curr_bat = 0; curr_bat < nr_bats; curr_bat++) {
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om_bat *bat = bats->bat + curr_bat;
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if ((ea & bat->block_effective_page_index_mask)
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!= bat->block_effective_page_index)
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continue;
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return bat;
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}
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return NULL;
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}
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STATIC_INLINE_VM\
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(om_segment_tlb_entry *)
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om_effective_to_virtual(om_map *map,
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unsigned_word ea,
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cpu *processor,
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unsigned_word cia)
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{
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/* first try the segment tlb */
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om_segment_tlb_entry *segment_tlb_entry = (map->segment_tlb->entry
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+ om_segment_tlb_index(ea));
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#if (WITH_TARGET_WORD_BITSIZE == 32)
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TRACE(trace_vm, ("ea=0x%lx - sr[%ld] - masked-vsid=0x%lx va=0x%lx%07lx\n",
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(unsigned long)ea,
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(long)om_segment_tlb_index(ea),
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(unsigned long)segment_tlb_entry->masked_virtual_segment_id,
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(unsigned long)EXTRACTED32(segment_tlb_entry->masked_virtual_segment_id, 31-6-24+1, 31-6),
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(unsigned long)EXTRACTED32(ea, 4, 31)));
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return segment_tlb_entry;
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#endif
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#if (WITH_TARGET_WORD_BITSIZE == 64)
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if (segment_tlb_entry->is_valid
|
|
&& (segment_tlb_entry->masked_effective_segment_id == MASKED(ea, 0, 35))) {
|
|
error("fixme - is there a need to update any bits\n");
|
|
return segment_tlb_entry;
|
|
}
|
|
|
|
/* drats, segment tlb missed */
|
|
{
|
|
unsigned_word segment_id_hash = ea;
|
|
int current_hash = 0;
|
|
for (current_hash = 0; current_hash < 2; current_hash += 1) {
|
|
unsigned_word segment_table_entry_group =
|
|
(map->real_address_of_segment_table
|
|
| (MASKED64(segment_id_hash, 31, 35) >> (56-35)));
|
|
unsigned_word segment_table_entry;
|
|
for (segment_table_entry = segment_table_entry_group;
|
|
segment_table_entry < (segment_table_entry_group
|
|
+ sizeof_segment_table_entry_group);
|
|
segment_table_entry += sizeof_segment_table_entry) {
|
|
/* byte order? */
|
|
unsigned_word segment_table_entry_dword_0 =
|
|
om_read_word(map->physical, segment_table_entry, processor, cia);
|
|
unsigned_word segment_table_entry_dword_1 =
|
|
om_read_word(map->physical, segment_table_entry + 8,
|
|
processor, cia);
|
|
int is_valid = MASKED64(segment_table_entry_dword_0, 56, 56) != 0;
|
|
unsigned_word masked_effective_segment_id =
|
|
MASKED64(segment_table_entry_dword_0, 0, 35);
|
|
if (is_valid && masked_effective_segment_id == MASKED64(ea, 0, 35)) {
|
|
/* don't permit some things */
|
|
if (MASKED64(segment_table_entry_dword_0, 57, 57))
|
|
error("om_effective_to_virtual() - T=1 in STE not supported\n");
|
|
/* update segment tlb */
|
|
segment_tlb_entry->is_valid = is_valid;
|
|
segment_tlb_entry->masked_effective_segment_id =
|
|
masked_effective_segment_id;
|
|
segment_tlb_entry->key[om_supervisor_state] =
|
|
EXTRACTED64(segment_table_entry_dword_0, 58, 58);
|
|
segment_tlb_entry->key[om_problem_state] =
|
|
EXTRACTED64(segment_table_entry_dword_0, 59, 59);
|
|
segment_tlb_entry->invalid_access =
|
|
(MASKED64(segment_table_entry_dword_0, 60, 60)
|
|
? om_instruction_read
|
|
: om_access_any);
|
|
segment_tlb_entry->masked_virtual_segment_id =
|
|
INSERTED64(EXTRACTED64(segment_table_entry_dword_1, 0, 51),
|
|
18-13, 63-7); /* aligned ready for pte group addr */
|
|
return segment_tlb_entry;
|
|
}
|
|
}
|
|
segment_id_hash = ~segment_id_hash;
|
|
}
|
|
}
|
|
return NULL;
|
|
#endif
|
|
}
|
|
|
|
|
|
|
|
STATIC_INLINE_VM\
|
|
(om_page_tlb_entry *)
|
|
om_virtual_to_real(om_map *map,
|
|
unsigned_word ea,
|
|
om_segment_tlb_entry *segment_tlb_entry,
|
|
om_access_types access,
|
|
cpu *processor,
|
|
unsigned_word cia)
|
|
{
|
|
om_page_tlb_entry *page_tlb_entry = (map->page_tlb->entry
|
|
+ om_page_tlb_index(ea));
|
|
|
|
/* is it a tlb hit? */
|
|
if ((page_tlb_entry->masked_virtual_segment_id
|
|
== segment_tlb_entry->masked_virtual_segment_id)
|
|
&& (page_tlb_entry->masked_page
|
|
== om_ea_masked_page(ea))) {
|
|
TRACE(trace_vm, ("ea=0x%lx - tlb hit - tlb=0x%lx\n",
|
|
(long)ea, (long)page_tlb_entry));
|
|
return page_tlb_entry;
|
|
}
|
|
|
|
/* drats, it is a tlb miss */
|
|
{
|
|
unsigned_word page_hash =
|
|
om_hash_page(segment_tlb_entry->masked_virtual_segment_id, ea);
|
|
int current_hash;
|
|
for (current_hash = 0; current_hash < 2; current_hash += 1) {
|
|
unsigned_word real_address_of_pte_group =
|
|
(map->real_address_of_page_table
|
|
| (page_hash & map->page_table_hash_mask));
|
|
unsigned_word real_address_of_pte_0;
|
|
TRACE(trace_vm,
|
|
("ea=0x%lx - htab search %d - htab=0x%lx hash=0x%lx mask=0x%lx pteg=0x%lx\n",
|
|
(long)ea, current_hash,
|
|
map->real_address_of_page_table,
|
|
page_hash,
|
|
map->page_table_hash_mask,
|
|
(long)real_address_of_pte_group));
|
|
for (real_address_of_pte_0 = real_address_of_pte_group;
|
|
real_address_of_pte_0 < (real_address_of_pte_group
|
|
+ sizeof_pte_group);
|
|
real_address_of_pte_0 += sizeof_pte) {
|
|
unsigned_word pte_0 = om_read_word(map,
|
|
real_address_of_pte_0,
|
|
processor, cia);
|
|
/* did we hit? */
|
|
if (om_pte_0_valid(pte_0)
|
|
&& (current_hash == om_pte_0_hash(pte_0))
|
|
&& (segment_tlb_entry->masked_virtual_segment_id
|
|
== om_pte_0_masked_vsid(pte_0))
|
|
&& (om_ea_api(ea) == om_pte_0_api(pte_0))) {
|
|
unsigned_word real_address_of_pte_1 = (real_address_of_pte_0
|
|
+ sizeof_pte / 2);
|
|
unsigned_word pte_1 = om_read_word(map,
|
|
real_address_of_pte_1,
|
|
processor, cia);
|
|
page_tlb_entry->protection = om_pte_1_pp(pte_1);
|
|
page_tlb_entry->changed = om_pte_1_changed(pte_1);
|
|
page_tlb_entry->masked_virtual_segment_id = segment_tlb_entry->masked_virtual_segment_id;
|
|
page_tlb_entry->masked_page = om_ea_masked_page(ea);
|
|
page_tlb_entry->masked_real_page_number = om_pte_1_masked_rpn(pte_1);
|
|
page_tlb_entry->real_address_of_pte_1 = real_address_of_pte_1;
|
|
if (!om_pte_1_referenced(pte_1)) {
|
|
om_write_word(map,
|
|
real_address_of_pte_1,
|
|
pte_1 | BIT(55),
|
|
processor, cia);
|
|
TRACE(trace_vm,
|
|
("ea=0x%lx - htab hit - set ref - tlb=0x%lx &pte1=0x%lx\n",
|
|
(long)ea, (long)page_tlb_entry, (long)real_address_of_pte_1));
|
|
}
|
|
else {
|
|
TRACE(trace_vm,
|
|
("ea=0x%lx - htab hit - tlb=0x%lx &pte1=0x%lx\n",
|
|
(long)ea, (long)page_tlb_entry, (long)real_address_of_pte_1));
|
|
}
|
|
return page_tlb_entry;
|
|
}
|
|
}
|
|
page_hash = ~page_hash; /*???*/
|
|
}
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
|
|
STATIC_INLINE_VM\
|
|
(void)
|
|
om_interrupt(cpu *processor,
|
|
unsigned_word cia,
|
|
unsigned_word ea,
|
|
om_access_types access,
|
|
storage_interrupt_reasons reason)
|
|
{
|
|
switch (access) {
|
|
case om_data_read:
|
|
data_storage_interrupt(processor, cia, ea, reason, 0/*!is_store*/);
|
|
break;
|
|
case om_data_write:
|
|
data_storage_interrupt(processor, cia, ea, reason, 1/*is_store*/);
|
|
break;
|
|
case om_instruction_read:
|
|
instruction_storage_interrupt(processor, cia, reason);
|
|
break;
|
|
default:
|
|
error("internal error - om_interrupt - unexpected access type %d", access);
|
|
}
|
|
}
|
|
|
|
|
|
STATIC_INLINE_VM\
|
|
(unsigned_word)
|
|
om_translate_effective_to_real(om_map *map,
|
|
unsigned_word ea,
|
|
om_access_types access,
|
|
cpu *processor,
|
|
unsigned_word cia,
|
|
int abort)
|
|
{
|
|
om_bat *bat = NULL;
|
|
om_segment_tlb_entry *segment_tlb_entry = NULL;
|
|
om_page_tlb_entry *page_tlb_entry = NULL;
|
|
unsigned_word ra;
|
|
|
|
if (!map->is_relocate) {
|
|
ra = ea;
|
|
TRACE(trace_vm, ("ea=0x%lx - direct map - ra=0x%lx\n",
|
|
(long)ea, (long)ra));
|
|
return ra;
|
|
}
|
|
|
|
/* match with BAT? */
|
|
bat = om_effective_to_bat(map, ea);
|
|
if (bat != NULL) {
|
|
if (!om_valid_access[1][bat->protection_bits][access]) {
|
|
TRACE(trace_vm, ("ea=0x%lx - bat access violation\n", (long)ea));
|
|
if (abort)
|
|
om_interrupt(processor, cia, ea, access,
|
|
protection_violation_storage_interrupt);
|
|
else
|
|
return MASK(0, 63);
|
|
}
|
|
|
|
ra = ((ea & bat->block_length_mask) | bat->block_real_page_number);
|
|
TRACE(trace_vm, ("ea=0x%lx - bat translation - ra=0x%lx\n",
|
|
(long)ea, (long)ra));
|
|
return ra;
|
|
}
|
|
|
|
/* translate ea to va using segment map */
|
|
segment_tlb_entry = om_effective_to_virtual(map, ea, processor, cia);
|
|
#if (WITH_TARGET_WORD_BITSIZE == 64)
|
|
if (segment_tlb_entry == NULL) {
|
|
TRACE(trace_vm, ("ea=0x%lx - segment tlb miss\n", (long)ea));
|
|
if (abort)
|
|
om_interrupt(processor, cia, ea, access,
|
|
segment_table_miss_storage_interrupt);
|
|
else
|
|
return MASK(0, 63);
|
|
}
|
|
#endif
|
|
/* check for invalid segment access type */
|
|
if (segment_tlb_entry->invalid_access == access) {
|
|
TRACE(trace_vm, ("ea=0x%lx - segment access invalid\n", (long)ea));
|
|
if (abort)
|
|
om_interrupt(processor, cia, ea, access,
|
|
protection_violation_storage_interrupt);
|
|
else
|
|
return MASK(0, 63);
|
|
}
|
|
|
|
/* lookup in PTE */
|
|
page_tlb_entry = om_virtual_to_real(map, ea, segment_tlb_entry,
|
|
access,
|
|
processor, cia);
|
|
if (page_tlb_entry == NULL) {
|
|
TRACE(trace_vm, ("ea=0x%lx - page tlb miss\n", (long)ea));
|
|
if (abort)
|
|
om_interrupt(processor, cia, ea, access,
|
|
hash_table_miss_storage_interrupt);
|
|
else
|
|
return MASK(0, 63);
|
|
}
|
|
if (!(om_valid_access
|
|
[segment_tlb_entry->key[map->is_problem_state]]
|
|
[page_tlb_entry->protection]
|
|
[access])) {
|
|
TRACE(trace_vm, ("ea=0x%lx - page tlb access violation\n", (long)ea));
|
|
if (abort)
|
|
om_interrupt(processor, cia, ea, access,
|
|
protection_violation_storage_interrupt);
|
|
else
|
|
return MASK(0, 63);
|
|
}
|
|
|
|
/* update change bit as needed */
|
|
if (access == om_data_write &&!page_tlb_entry->changed) {
|
|
unsigned_word pte_1 = om_read_word(map,
|
|
page_tlb_entry->real_address_of_pte_1,
|
|
processor, cia);
|
|
om_write_word(map,
|
|
page_tlb_entry->real_address_of_pte_1,
|
|
pte_1 | BIT(56),
|
|
processor, cia);
|
|
TRACE(trace_vm, ("ea=0x%lx - set change bit - tlb=0x%lx &pte1=0x%lx\n",
|
|
(long)ea, (long)page_tlb_entry,
|
|
(long)page_tlb_entry->real_address_of_pte_1));
|
|
}
|
|
|
|
ra = (page_tlb_entry->masked_real_page_number | om_ea_masked_byte(ea));
|
|
TRACE(trace_vm, ("ea=0x%lx - page translation - ra=0x%lx\n",
|
|
(long)ea, (long)ra));
|
|
return ra;
|
|
}
|
|
|
|
|
|
/*
|
|
* Definition of operations for memory management
|
|
*/
|
|
|
|
|
|
/* rebuild all the relevant bat information */
|
|
STATIC_INLINE_VM\
|
|
(void)
|
|
om_unpack_bat(om_bat *bat,
|
|
spreg ubat,
|
|
spreg lbat)
|
|
{
|
|
/* for extracting out the offset within a page */
|
|
bat->block_length_mask = ((MASKED(ubat, 51, 61) << (17-2))
|
|
| MASK(63-17+1, 63));
|
|
|
|
/* for checking the effective page index */
|
|
bat->block_effective_page_index = MASKED(ubat, 0, 46);
|
|
bat->block_effective_page_index_mask = ~bat->block_length_mask;
|
|
|
|
/* protection information */
|
|
bat->protection_bits = EXTRACTED(lbat, 62, 63);
|
|
bat->block_real_page_number = MASKED(lbat, 0, 46);
|
|
}
|
|
|
|
|
|
/* rebuild the given bat table */
|
|
STATIC_INLINE_VM\
|
|
(void)
|
|
om_unpack_bats(om_bats *bats,
|
|
spreg *raw_bats,
|
|
msreg msr)
|
|
{
|
|
int i;
|
|
bats->nr_valid_bat_registers = 0;
|
|
for (i = 0; i < nr_om_bat_registers*2; i += 2) {
|
|
spreg ubat = raw_bats[i];
|
|
spreg lbat = raw_bats[i+1];
|
|
if ((msr & msr_problem_state)
|
|
? EXTRACTED(ubat, 63, 63)
|
|
: EXTRACTED(ubat, 62, 62)) {
|
|
om_unpack_bat(&bats->bat[bats->nr_valid_bat_registers],
|
|
ubat, lbat);
|
|
bats->nr_valid_bat_registers += 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
#if (WITH_TARGET_WORD_BITSIZE == 32)
|
|
STATIC_INLINE_VM\
|
|
(void)
|
|
om_unpack_sr(vm *virtual,
|
|
sreg *srs,
|
|
int which_sr,
|
|
cpu *processor,
|
|
unsigned_word cia)
|
|
{
|
|
om_segment_tlb_entry *segment_tlb_entry = 0;
|
|
sreg new_sr_value = 0;
|
|
|
|
/* check register in range */
|
|
ASSERT(which_sr >= 0 && which_sr < nr_om_segment_tlb_entries);
|
|
|
|
/* get the working values */
|
|
segment_tlb_entry = &virtual->segment_tlb.entry[which_sr];
|
|
new_sr_value = srs[which_sr];
|
|
|
|
/* do we support this */
|
|
if (MASKED32(new_sr_value, 0, 0))
|
|
cpu_error(processor, cia, "unsupported value of T in segment register %d",
|
|
which_sr);
|
|
|
|
/* update info */
|
|
segment_tlb_entry->key[om_supervisor_state] = EXTRACTED32(new_sr_value, 1, 1);
|
|
segment_tlb_entry->key[om_problem_state] = EXTRACTED32(new_sr_value, 2, 2);
|
|
segment_tlb_entry->invalid_access = (MASKED32(new_sr_value, 3, 3)
|
|
? om_instruction_read
|
|
: om_access_any);
|
|
segment_tlb_entry->masked_virtual_segment_id =
|
|
INSERTED32(EXTRACTED32(new_sr_value, 8, 31),
|
|
31-6-24+1, 31-6); /* aligned ready for pte group addr */
|
|
}
|
|
#endif
|
|
|
|
|
|
#if (WITH_TARGET_WORD_BITSIZE == 32)
|
|
STATIC_INLINE_VM\
|
|
(void)
|
|
om_unpack_srs(vm *virtual,
|
|
sreg *srs,
|
|
cpu *processor,
|
|
unsigned_word cia)
|
|
{
|
|
int which_sr;
|
|
for (which_sr = 0; which_sr < nr_om_segment_tlb_entries; which_sr++) {
|
|
om_unpack_sr(virtual, srs, which_sr,
|
|
processor, cia);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
|
|
/* Rebuild all the data structures for the new context as specifed by
|
|
the passed registers */
|
|
INLINE_VM\
|
|
(void)
|
|
vm_synchronize_context(vm *virtual,
|
|
spreg *sprs,
|
|
sreg *srs,
|
|
msreg msr,
|
|
/**/
|
|
cpu *processor,
|
|
unsigned_word cia)
|
|
{
|
|
|
|
/* enable/disable translation */
|
|
int problem_state = (msr & msr_problem_state) != 0;
|
|
int data_relocate = (msr & msr_data_relocate) != 0;
|
|
int instruction_relocate = (msr & msr_instruction_relocate) != 0;
|
|
int little_endian = (msr & msr_little_endian_mode) != 0;
|
|
|
|
unsigned_word page_table_hash_mask;
|
|
unsigned_word real_address_of_page_table;
|
|
|
|
/* update current processor mode */
|
|
virtual->instruction_map.translation.is_relocate = instruction_relocate;
|
|
virtual->instruction_map.translation.is_problem_state = problem_state;
|
|
virtual->data_map.translation.is_relocate = data_relocate;
|
|
virtual->data_map.translation.is_problem_state = problem_state;
|
|
|
|
/* update bat registers for the new context */
|
|
om_unpack_bats(&virtual->ibats, &sprs[spr_ibat0u], msr);
|
|
om_unpack_bats(&virtual->dbats, &sprs[spr_dbat0u], msr);
|
|
|
|
/* unpack SDR1 - the storage description register 1 */
|
|
#if (WITH_TARGET_WORD_BITSIZE == 64)
|
|
real_address_of_page_table = MASKED64(sprs[spr_sdr1], 0, 45);
|
|
page_table_hash_mask = MASK64(18+28-EXTRACTED64(sprs[spr_sdr1], 59, 63),
|
|
63-7);
|
|
#endif
|
|
#if (WITH_TARGET_WORD_BITSIZE == 32)
|
|
real_address_of_page_table = MASKED32(sprs[spr_sdr1], 0, 15);
|
|
page_table_hash_mask = (INSERTED32(EXTRACTED32(sprs[spr_sdr1], 23, 31),
|
|
7, 7+9-1)
|
|
| MASK32(7+9, 31-6));
|
|
#endif
|
|
virtual->instruction_map.translation.real_address_of_page_table = real_address_of_page_table;
|
|
virtual->instruction_map.translation.page_table_hash_mask = page_table_hash_mask;
|
|
virtual->data_map.translation.real_address_of_page_table = real_address_of_page_table;
|
|
virtual->data_map.translation.page_table_hash_mask = page_table_hash_mask;
|
|
|
|
|
|
/* unpack the segment tlb registers */
|
|
#if (WITH_TARGET_WORD_BITSIZE == 32)
|
|
om_unpack_srs(virtual, srs,
|
|
processor, cia);
|
|
#endif
|
|
|
|
/* set up the XOR registers if the current endian mode conflicts
|
|
with what is in the MSR */
|
|
if (WITH_XOR_ENDIAN) {
|
|
int i = 1;
|
|
unsigned mask;
|
|
if ((little_endian && CURRENT_TARGET_BYTE_ORDER == LITTLE_ENDIAN)
|
|
|| (!little_endian && CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN))
|
|
mask = 0;
|
|
else
|
|
mask = WITH_XOR_ENDIAN - 1;
|
|
while (i - 1 < WITH_XOR_ENDIAN) {
|
|
virtual->instruction_map.translation.xor[i-1] = mask;
|
|
virtual->data_map.translation.xor[i-1] = mask;
|
|
mask = (mask << 1) & (WITH_XOR_ENDIAN - 1);
|
|
i = i * 2;
|
|
}
|
|
}
|
|
else {
|
|
/* don't allow the processor to change endian modes */
|
|
if ((little_endian && CURRENT_TARGET_BYTE_ORDER != LITTLE_ENDIAN)
|
|
|| (!little_endian && CURRENT_TARGET_BYTE_ORDER != BIG_ENDIAN))
|
|
cpu_error(processor, cia, "attempt to change hardwired byte order");
|
|
}
|
|
}
|
|
|
|
/* update vm data structures due to a TLB operation */
|
|
|
|
INLINE_VM\
|
|
(void)
|
|
vm_page_tlb_invalidate_entry(vm *memory,
|
|
unsigned_word ea)
|
|
{
|
|
int i = om_page_tlb_index(ea);
|
|
memory->instruction_tlb.entry[i].masked_virtual_segment_id = MASK(0, 63);
|
|
memory->data_tlb.entry[i].masked_virtual_segment_id = MASK(0, 63);
|
|
TRACE(trace_vm, ("ea=0x%lx - tlb invalidate entry\n", (long)ea));
|
|
}
|
|
|
|
INLINE_VM\
|
|
(void)
|
|
vm_page_tlb_invalidate_all(vm *memory)
|
|
{
|
|
int i;
|
|
for (i = 0; i < nr_om_page_tlb_entries; i++) {
|
|
memory->instruction_tlb.entry[i].masked_virtual_segment_id = MASK(0, 63);
|
|
memory->data_tlb.entry[i].masked_virtual_segment_id = MASK(0, 63);
|
|
}
|
|
TRACE(trace_vm, ("tlb invalidate all\n"));
|
|
}
|
|
|
|
|
|
|
|
INLINE_VM\
|
|
(vm_data_map *)
|
|
vm_create_data_map(vm *memory)
|
|
{
|
|
return &memory->data_map;
|
|
}
|
|
|
|
|
|
INLINE_VM\
|
|
(vm_instruction_map *)
|
|
vm_create_instruction_map(vm *memory)
|
|
{
|
|
return &memory->instruction_map;
|
|
}
|
|
|
|
|
|
STATIC_INLINE_VM\
|
|
(unsigned_word)
|
|
vm_translate(om_map *map,
|
|
unsigned_word ea,
|
|
om_access_types access,
|
|
cpu *processor,
|
|
unsigned_word cia,
|
|
int abort)
|
|
{
|
|
switch (CURRENT_ENVIRONMENT) {
|
|
case USER_ENVIRONMENT:
|
|
case VIRTUAL_ENVIRONMENT:
|
|
return ea;
|
|
case OPERATING_ENVIRONMENT:
|
|
return om_translate_effective_to_real(map, ea, access,
|
|
processor, cia,
|
|
abort);
|
|
default:
|
|
error("internal error - vm_translate - bad switch");
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
|
|
INLINE_VM\
|
|
(unsigned_word)
|
|
vm_real_data_addr(vm_data_map *map,
|
|
unsigned_word ea,
|
|
int is_read,
|
|
cpu *processor,
|
|
unsigned_word cia)
|
|
{
|
|
return vm_translate(&map->translation,
|
|
ea,
|
|
is_read ? om_data_read : om_data_write,
|
|
processor,
|
|
cia,
|
|
1); /*abort*/
|
|
}
|
|
|
|
|
|
INLINE_VM\
|
|
(unsigned_word)
|
|
vm_real_instruction_addr(vm_instruction_map *map,
|
|
cpu *processor,
|
|
unsigned_word cia)
|
|
{
|
|
return vm_translate(&map->translation,
|
|
cia,
|
|
om_instruction_read,
|
|
processor,
|
|
cia,
|
|
1); /*abort*/
|
|
}
|
|
|
|
INLINE_VM\
|
|
(instruction_word)
|
|
vm_instruction_map_read(vm_instruction_map *map,
|
|
cpu *processor,
|
|
unsigned_word cia)
|
|
{
|
|
unsigned_word ra = vm_real_instruction_addr(map, processor, cia);
|
|
ASSERT((cia & 0x3) == 0); /* always aligned */
|
|
if (WITH_XOR_ENDIAN)
|
|
ra ^= map->translation.xor[sizeof(instruction_word) - 1];
|
|
return core_map_read_4(map->code, ra, processor, cia);
|
|
}
|
|
|
|
|
|
INLINE_VM\
|
|
(int)
|
|
vm_data_map_read_buffer(vm_data_map *map,
|
|
void *target,
|
|
unsigned_word addr,
|
|
unsigned nr_bytes,
|
|
cpu *processor,
|
|
unsigned_word cia)
|
|
{
|
|
unsigned count;
|
|
for (count = 0; count < nr_bytes; count++) {
|
|
unsigned_1 byte;
|
|
unsigned_word ea = addr + count;
|
|
unsigned_word ra = vm_translate(&map->translation,
|
|
ea, om_data_read,
|
|
processor, /*processor*/
|
|
cia, /*cia*/
|
|
processor != NULL); /*abort?*/
|
|
if (ra == MASK(0, 63))
|
|
break;
|
|
if (WITH_XOR_ENDIAN)
|
|
ra ^= map->translation.xor[0];
|
|
if (core_map_read_buffer(map->read, &byte, ra, sizeof(byte))
|
|
!= sizeof(byte))
|
|
break;
|
|
((unsigned_1*)target)[count] = T2H_1(byte);
|
|
}
|
|
return count;
|
|
}
|
|
|
|
|
|
INLINE_VM\
|
|
(int)
|
|
vm_data_map_write_buffer(vm_data_map *map,
|
|
const void *source,
|
|
unsigned_word addr,
|
|
unsigned nr_bytes,
|
|
int violate_read_only_section,
|
|
cpu *processor,
|
|
unsigned_word cia)
|
|
{
|
|
unsigned count;
|
|
unsigned_1 byte;
|
|
for (count = 0; count < nr_bytes; count++) {
|
|
unsigned_word ea = addr + count;
|
|
unsigned_word ra = vm_translate(&map->translation,
|
|
ea, om_data_write,
|
|
processor,
|
|
cia,
|
|
processor != NULL); /*abort?*/
|
|
if (ra == MASK(0, 63))
|
|
break;
|
|
if (WITH_XOR_ENDIAN)
|
|
ra ^= map->translation.xor[0];
|
|
byte = T2H_1(((unsigned_1*)source)[count]);
|
|
if (core_map_write_buffer((violate_read_only_section
|
|
? map->read
|
|
: map->write),
|
|
&byte, ra, sizeof(byte)) != sizeof(byte))
|
|
break;
|
|
}
|
|
return count;
|
|
}
|
|
|
|
|
|
/* define the read/write 1/2/4/8/word functions */
|
|
|
|
#define N 1
|
|
#include "vm_n.h"
|
|
#undef N
|
|
|
|
#define N 2
|
|
#include "vm_n.h"
|
|
#undef N
|
|
|
|
#define N 4
|
|
#include "vm_n.h"
|
|
#undef N
|
|
|
|
#define N 8
|
|
#include "vm_n.h"
|
|
#undef N
|
|
|
|
#define N word
|
|
#include "vm_n.h"
|
|
#undef N
|
|
|
|
|
|
|
|
#endif /* _VM_C_ */
|