139 lines
4.2 KiB
C
139 lines
4.2 KiB
C
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/****************************************************/
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/* This is a (Toronto created) wrapper program */
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/* to drive the sce_tests */
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/* */
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/* Copyright (C) 1998, Cygnus Solutions */
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/****************************************************/
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extern int printf(const char *, ...);
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extern char My_dma_start[];
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extern char gpu_refresh;
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/* ------------- VU defines --------------*/
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#define VPU_STAT (volatile int *)0x110073d0
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#define VPU_STAT_VBS1_MASK 0x00000100
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/* ----------end of VU defines -----------*/
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/* ------------- VIF defines -------------*/
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#define VIF1_STAT (volatile int *) 0x10003C00
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#define VIF1_STAT_FQC_MASK 0x1F000000
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#define VIF1_STAT_PPS_MASK 0x00000003
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/* ----------end of VIF defines -----------*/
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/* -------------- DMA defines -------------*/
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#define DMA_D0_CHCR (volatile int*)0x10008000
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#define DMA_D0_MADR (volatile int*)0x10008010
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#define DMA_D0_QWC (volatile int*)0x10008020
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#define DMA_D0_TADR (volatile int*)0x10008030
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#define DMA_D0_ASR0 (volatile int*)0x10008040
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#define DMA_D0_ASR1 (volatile int*)0x10008050
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#define DMA_D0_PKTFLAG (volatile int*)0x10008060 /* virtual reg to indicate presence of tag in data */
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#define DMA_D1_CHCR (volatile int*)0x10009000
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#define DMA_D1_MADR (volatile int*)0x10009010
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#define DMA_D1_QWC (volatile int*)0x10009020
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#define DMA_D1_TADR (volatile int*)0x10009030
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#define DMA_D1_ASR0 (volatile int*)0x10009040
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#define DMA_D1_ASR1 (volatile int*)0x10009050
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#define DMA_D1_PKTFLAG (volatile int*)0x10009060 /* virtual reg to indicate presence of tag in data */
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#define DMA_D2_CHCR (volatile int*)0x1000a000
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#define DMA_D2_MADR (volatile int*)0x1000a010
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#define DMA_D2_QWC (volatile int*)0x1000a020
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#define DMA_D2_TADR (volatile int*)0x1000a030
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#define DMA_D2_ASR0 (volatile int*)0x1000a040
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#define DMA_D2_ASR1 (volatile int*)0x1000a050
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#define DMA_D2_PKTFLAG (volatile int*)0x1000a060 /* virtual reg to indicate presence of tag in data */
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#define DMA_D_CTRL (volatile int*)0x1000e000
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#define DMA_D_CTRL__DMAE 0x00000001
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#define DMA_D_STAT (volatile int*)0x1000e010
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#define DMA_D_STAT__TOGGLE 0x63ff0000
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#define DMA_D_STAT__CLEAR 0x0000e3ff
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#define DMA_D_PCR (volatile int*)0x1000e020
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#define DMA_D_PCR__PCE 0x80000000
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#define DMA_D_PCR__CDE 0x03ff0000
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#define DMA_D_SQWC (volatile int*)0x1000e030
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#define DMA_D_RBSR (volatile int*)0x1000e040
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#define DMA_D_RBOR (volatile int*)0x1000e050
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#define DMA_D_STADR (volatile int*)0x1000e060
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/* Defines for DMA tag fields. */
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#define DMA_TAG_ID 0x70000000
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#define DMA_TAG_ID__REFE 0
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#define DMA_TAG_ID__CNT 1
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#define DMA_TAG_ID__NEXT 2
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#define DMA_TAG_ID__REF 3
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#define DMA_TAG_ID__REFS 4
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#define DMA_TAG_ID__CALL 5
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#define DMA_TAG_ID__RET 6
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#define DMA_TAG_ID__END 7
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/* Dn_CHCR definition values */
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#define MODE_NORM 0
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#define MODE_CHAIN (1 << 2)
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#define MODE_INTR (2 << 2)
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#define DMA_START (1 << 8)
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#define DMA_Dn_CHCR__TTE 0x00000040
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/* ----------end of VIF defines -----------*/
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void DMA_enable(void) {
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*DMA_D_CTRL = 0x01; /* DMA enable */
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}
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/* If DMA mode is source chain */
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void start_DMA_ch1_source_chain(void* data) {
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*DMA_D_CTRL = 0x01; /* DMA enable */
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*DMA_D1_QWC = 0x00;
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*DMA_D1_TADR = (int)data;
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*DMA_D1_CHCR = MODE_CHAIN | DMA_START | DMA_Dn_CHCR__TTE;
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}
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/* If DMA mode is normal */
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void start_DMA_ch1_normal(void* data, int qwc) {
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*DMA_D_CTRL = 0x01; /* DMA enable */
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*DMA_D1_QWC = qwc; /* 8 is sample */
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*DMA_D1_MADR = (int)data;
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*DMA_D1_CHCR = MODE_NORM | DMA_START | DMA_Dn_CHCR__TTE;
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}
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void wait_until_idle() {
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/* Hmmm... Not sure exactly what the right code is for this. I'll look for
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* VIF_STAT.PPS = 0 && VIF_STAT.FQC == 0 && VPU_STAT.VBS1 == 0 */
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int vif1_stat, vpu_stat;
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do {
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vif1_stat = *VIF1_STAT;
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vpu_stat = *VPU_STAT;
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} while (!( (vif1_stat & VIF1_STAT_PPS_MASK) == 0
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&& (vif1_stat & VIF1_STAT_FQC_MASK) == 0
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&& (vpu_stat & VPU_STAT_VBS1_MASK) == 0));
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}
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void wait_a_while() {
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int i;
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for (i = 0; i<200000; i++) {}
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}
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int main() {
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start_DMA_ch1_source_chain(&My_dma_start);
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wait_until_idle();
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start_DMA_ch1_source_chain(&gpu_refresh);
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wait_a_while();
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return 0;
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}
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